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-rw-r--r--MAINTAINERS5
-rw-r--r--hw/cs4231a.c38
-rw-r--r--hw/fdc.c53
-rw-r--r--hw/i8254.c16
-rw-r--r--hw/i8259.c65
-rw-r--r--hw/isa-bus.c14
-rw-r--r--hw/isa.h7
-rw-r--r--hw/mips_jazz.c21
-rw-r--r--hw/mips_malta.c20
-rw-r--r--hw/mips_r4k.c2
-rw-r--r--hw/nseries.c4
-rw-r--r--hw/omap.h21
-rw-r--r--hw/omap1.c142
-rw-r--r--hw/omap2.c92
-rw-r--r--hw/omap_intc.c175
-rw-r--r--hw/pc.h2
-rw-r--r--hw/pc_piix.c24
-rw-r--r--hw/pci.c5
-rw-r--r--hw/pci.h1
-rw-r--r--hw/pckbd.c59
-rw-r--r--hw/piix4.c2
-rw-r--r--hw/piix_pci.c2
-rw-r--r--hw/ppc_prep.c4
-rw-r--r--hw/serial.c15
-rw-r--r--hw/sun4u.c2
-rw-r--r--hw/vt82c686.c2
-rw-r--r--linux-user/elfload.c56
-rw-r--r--linux-user/main.c674
-rw-r--r--linux-user/qemu.h6
-rw-r--r--linux-user/syscall.c63
-rw-r--r--memory.c29
-rw-r--r--memory.h1
32 files changed, 1083 insertions, 539 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index d034ce4b5a..2b4c5d727e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -360,6 +360,11 @@ M: Kevin Wolf <kwolf@redhat.com>
S: Odd Fixes
F: hw/ide/
+OMAP
+M: Peter Maydell <peter.maydell@linaro.org>
+S: Maintained
+F: hw/omap*
+
PCI
M: Michael S. Tsirkin <mst@redhat.com>
S: Supported
diff --git a/hw/cs4231a.c b/hw/cs4231a.c
index 598f0322d9..e16665e196 100644
--- a/hw/cs4231a.c
+++ b/hw/cs4231a.c
@@ -59,6 +59,7 @@ static struct {
typedef struct CSState {
ISADevice dev;
QEMUSoundCard card;
+ MemoryRegion ioports;
qemu_irq pic;
uint32_t regs[CS_REGS];
uint8_t dregs[CS_DREGS];
@@ -74,14 +75,6 @@ typedef struct CSState {
int16_t *tab;
} CSState;
-#define IO_READ_PROTO(name) \
- static uint32_t name (void *opaque, uint32_t addr)
-
-#define IO_WRITE_PROTO(name) \
- static void name (void *opaque, uint32_t addr, uint32_t val)
-
-#define GET_SADDR(addr) (addr & 3)
-
#define MODE2 (1 << 6)
#define MCE (1 << 6)
#define PMCE (1 << 4)
@@ -353,12 +346,12 @@ static void cs_reset_voices (CSState *s, uint32_t val)
}
}
-IO_READ_PROTO (cs_read)
+static uint64_t cs_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, ret;
- saddr = GET_SADDR (addr);
+ saddr = addr;
iaddr = ~0U;
switch (saddr) {
@@ -390,12 +383,14 @@ IO_READ_PROTO (cs_read)
return ret;
}
-IO_WRITE_PROTO (cs_write)
+static void cs_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned size)
{
CSState *s = opaque;
- uint32_t saddr, iaddr;
+ uint32_t saddr, iaddr, val;
- saddr = GET_SADDR (addr);
+ saddr = addr;
+ val = val64;
switch (saddr) {
case Index_Address:
@@ -637,18 +632,23 @@ static const VMStateDescription vmstate_cs4231a = {
}
};
+static const MemoryRegionOps cs_ioport_ops = {
+ .read = cs_read,
+ .write = cs_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ }
+};
+
static int cs4231a_initfn (ISADevice *dev)
{
CSState *s = DO_UPCAST (CSState, dev, dev);
- int i;
isa_init_irq (dev, &s->pic, s->irq);
- for (i = 0; i < 4; i++) {
- isa_init_ioport(dev, i);
- register_ioport_write (s->port + i, 1, 1, cs_write, s);
- register_ioport_read (s->port + i, 1, 1, cs_read, s);
- }
+ memory_region_init_io(&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
+ isa_register_ioport(dev, &s->ioports, s->port);
DMA_register_channel (s->dma, cs_dma_read, s);
diff --git a/hw/fdc.c b/hw/fdc.c
index 433af73ad7..0f1cee9439 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -424,6 +424,7 @@ typedef struct FDCtrlSysBus {
typedef struct FDCtrlISABus {
ISADevice busdev;
+ MemoryRegion io_0, io_7;
struct FDCtrl state;
int32_t bootindexA;
int32_t bootindexB;
@@ -489,16 +490,6 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
}
}
-static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
-{
- return fdctrl_read(opaque, reg & 7);
-}
-
-static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
-{
- fdctrl_write(opaque, reg & 7, value);
-}
-
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
{
return fdctrl_read(opaque, (uint32_t)reg);
@@ -1889,6 +1880,34 @@ static int fdctrl_init_common(FDCtrl *fdctrl)
return fdctrl_connect_drives(fdctrl);
}
+static uint32_t fdctrl_read_port_7(void *opaque, uint32_t reg)
+{
+ return fdctrl_read(opaque, reg + 7);
+}
+
+static void fdctrl_write_port_7(void *opaque, uint32_t reg, uint32_t value)
+{
+ fdctrl_write(opaque, reg + 7, value);
+}
+
+static const MemoryRegionPortio fdc_portio_0[] = {
+ { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionPortio fdc_portio_7[] = {
+ { 0, 1, 1, .read = fdctrl_read_port_7, .write = fdctrl_write_port_7 },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps fdc_ioport_0_ops = {
+ .old_portio = fdc_portio_0
+};
+
+static const MemoryRegionOps fdc_ioport_7_ops = {
+ .old_portio = fdc_portio_7
+};
+
static int isabus_fdc_init1(ISADevice *dev)
{
FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
@@ -1898,16 +1917,10 @@ static int isabus_fdc_init1(ISADevice *dev)
int dma_chann = 2;
int ret;
- register_ioport_read(iobase + 0x01, 5, 1,
- &fdctrl_read_port, fdctrl);
- register_ioport_read(iobase + 0x07, 1, 1,
- &fdctrl_read_port, fdctrl);
- register_ioport_write(iobase + 0x01, 5, 1,
- &fdctrl_write_port, fdctrl);
- register_ioport_write(iobase + 0x07, 1, 1,
- &fdctrl_write_port, fdctrl);
- isa_init_ioport_range(dev, iobase, 6);
- isa_init_ioport(dev, iobase + 7);
+ memory_region_init_io(&isa->io_0, &fdc_ioport_0_ops, fdctrl, "fdc", 6);
+ memory_region_init_io(&isa->io_7, &fdc_ioport_7_ops, fdctrl, "fdc", 1);
+ isa_register_ioport(dev, &isa->io_0, iobase);
+ isa_register_ioport(dev, &isa->io_7, iobase + 7);
isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
fdctrl->dma_chann = dma_chann;
diff --git a/hw/i8254.c b/hw/i8254.c
index a9ca9f6f18..12571efc2a 100644
--- a/hw/i8254.c
+++ b/hw/i8254.c
@@ -55,6 +55,7 @@ typedef struct PITChannelState {
typedef struct PITState {
ISADevice dev;
+ MemoryRegion ioports;
uint32_t irq;
uint32_t iobase;
PITChannelState channels[3];
@@ -506,6 +507,16 @@ void hpet_pit_enable(void)
pit_load_count(s, 0);
}
+static const MemoryRegionPortio pit_portio[] = {
+ { 0, 4, 1, .write = pit_ioport_write },
+ { 0, 3, 1, .read = pit_ioport_read },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps pit_ioport_ops = {
+ .old_portio = pit_portio
+};
+
static int pit_initfn(ISADevice *dev)
{
PITState *pit = DO_UPCAST(PITState, dev, dev);
@@ -516,9 +527,8 @@ static int pit_initfn(ISADevice *dev)
s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
s->irq = isa_get_irq(pit->irq);
- register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
- register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
- isa_init_ioport(dev, pit->iobase);
+ memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4);
+ isa_register_ioport(dev, &pit->ioports, pit->iobase);
qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
diff --git a/hw/i8259.c b/hw/i8259.c
index c0b96ab5d0..e5323ffa4d 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -59,6 +59,8 @@ typedef struct PicState {
uint8_t elcr; /* PIIX edge/trigger selection*/
uint8_t elcr_mask;
PicState2 *pics_state;
+ MemoryRegion base_io;
+ MemoryRegion elcr_io;
} PicState;
struct PicState2 {
@@ -284,13 +286,15 @@ static void pic_reset(void *opaque)
/* Note: ELCR is not reset */
}
-static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
+ uint64_t val64, unsigned size)
{
PicState *s = opaque;
+ uint32_t addr = addr64;
+ uint32_t val = val64;
int priority, cmd, irq;
DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
- addr &= 1;
if (addr == 0) {
if (val & 0x10) {
/* init */
@@ -374,19 +378,21 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
}
}
-static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
+static uint32_t pic_poll_read(PicState *s)
{
int ret;
ret = pic_get_irq(s);
if (ret >= 0) {
- if (addr1 >> 7) {
+ bool slave = (s == &isa_pic->pics[1]);
+
+ if (slave) {
s->pics_state->pics[0].isr &= ~(1 << 2);
s->pics_state->pics[0].irr &= ~(1 << 2);
}
s->irr &= ~(1 << ret);
s->isr &= ~(1 << ret);
- if (addr1 >> 7 || ret != 2)
+ if (slave || ret != 2)
pic_update_irq(s->pics_state);
} else {
ret = 0x07;
@@ -396,16 +402,15 @@ static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
return ret;
}
-static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
+static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr1,
+ unsigned size)
{
PicState *s = opaque;
- unsigned int addr;
+ unsigned int addr = addr1;
int ret;
- addr = addr1;
- addr &= 1;
if (s->poll) {
- ret = pic_poll_read(s, addr1);
+ ret = pic_poll_read(s);
s->poll = 0;
} else {
if (addr == 0) {
@@ -417,7 +422,7 @@ static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
ret = s->imr;
}
}
- DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret);
+ DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
return ret;
}
@@ -427,22 +432,24 @@ uint32_t pic_intack_read(PicState2 *s)
{
int ret;
- ret = pic_poll_read(&s->pics[0], 0x00);
+ ret = pic_poll_read(&s->pics[0]);
if (ret == 2)
- ret = pic_poll_read(&s->pics[1], 0x80) + 8;
+ ret = pic_poll_read(&s->pics[1]) + 8;
/* Prepare for ISR read */
s->pics[0].read_reg_select = 1;
return ret;
}
-static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
+static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
PicState *s = opaque;
s->elcr = val & s->elcr_mask;
}
-static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
+static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
PicState *s = opaque;
return s->elcr;
@@ -474,15 +481,35 @@ static const VMStateDescription vmstate_pic = {
}
};
+static const MemoryRegionOps pic_base_ioport_ops = {
+ .read = pic_ioport_read,
+ .write = pic_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static const MemoryRegionOps pic_elcr_ioport_ops = {
+ .read = elcr_ioport_read,
+ .write = elcr_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
/* XXX: add generic master/slave system */
static void pic_init1(int io_addr, int elcr_addr, PicState *s)
{
- register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
- register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
+ memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
+ memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
+
+ isa_register_ioport(NULL, &s->base_io, io_addr);
if (elcr_addr >= 0) {
- register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
- register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
+ isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
}
+
vmstate_register(NULL, io_addr, &vmstate_pic, s);
qemu_register_reset(pic_reset, s);
}
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 1cb497f5ca..6c15a31fe8 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -24,6 +24,7 @@
struct ISABus {
BusState qbus;
+ MemoryRegion *address_space_io;
qemu_irq *irqs;
};
static ISABus *isabus;
@@ -39,7 +40,7 @@ static struct BusInfo isa_bus_info = {
.get_fw_dev_path = isabus_get_fw_dev_path,
};
-ISABus *isa_bus_new(DeviceState *dev)
+ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io)
{
if (isabus) {
fprintf(stderr, "Can't create a second ISA bus\n");
@@ -51,6 +52,7 @@ ISABus *isa_bus_new(DeviceState *dev)
}
isabus = FROM_QBUS(ISABus, qbus_create(&isa_bus_info, dev, NULL));
+ isabus->address_space_io = address_space_io;
return isabus;
}
@@ -106,6 +108,16 @@ void isa_init_ioport(ISADevice *dev, uint16_t ioport)
isa_init_ioport_range(dev, ioport, 1);
}
+void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start)
+{
+ memory_region_add_subregion(isabus->address_space_io, start, io);
+ if (dev != NULL) {
+ assert(dev->nio < ARRAY_SIZE(dev->io));
+ dev->io[dev->nio++] = io;
+ isa_init_ioport_range(dev, start, memory_region_size(io));
+ }
+}
+
static int isa_qdev_init(DeviceState *qdev, DeviceInfo *base)
{
ISADevice *dev = DO_UPCAST(ISADevice, qdev, qdev);
diff --git a/hw/isa.h b/hw/isa.h
index f344699722..432d17ab26 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -13,10 +13,12 @@ typedef struct ISADeviceInfo ISADeviceInfo;
struct ISADevice {
DeviceState qdev;
+ MemoryRegion *io[32];
uint32_t isairq[2];
- int nirqs;
uint16_t ioports[32];
+ int nirqs;
int nioports;
+ int nio;
};
typedef int (*isa_qdev_initfn)(ISADevice *dev);
@@ -25,10 +27,11 @@ struct ISADeviceInfo {
isa_qdev_initfn init;
};
-ISABus *isa_bus_new(DeviceState *dev);
+ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io);
void isa_bus_irqs(qemu_irq *irqs);
qemu_irq isa_get_irq(int isairq);
void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
+void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start);
void isa_init_ioport(ISADevice *dev, uint16_t ioport);
void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
void isa_qdev_register(ISADeviceInfo *info);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 7cac5da920..ea07d32ead 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -102,10 +102,11 @@ static void cpu_request_exit(void *opaque, int irq, int level)
}
}
-static
-void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
- const char *cpu_model,
- enum jazz_model_e jazz_model)
+static void mips_jazz_init(MemoryRegion *address_space,
+ MemoryRegion *address_space_io,
+ ram_addr_t ram_size,
+ const char *cpu_model,
+ enum jazz_model_e jazz_model)
{
char *filename;
int bios_size, n;
@@ -114,6 +115,7 @@ void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
rc4030_dma *dmas;
void* rc4030_opaque;
MemoryRegion *rtc = g_new(MemoryRegion, 1);
+ MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev;
@@ -180,8 +182,8 @@ void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA devices */
+ isa_bus_new(NULL, address_space_io);
i8259 = i8259_init(env->irq[4]);
- isa_bus_new(NULL);
isa_bus_irqs(i8259);
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
DMA_init(0, cpu_exit_irq);
@@ -257,7 +259,8 @@ void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
- i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
+ i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
+ memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
@@ -299,7 +302,8 @@ void mips_magnum_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_MAGNUM);
+ mips_jazz_init(get_system_memory(), get_system_io(),
+ ram_size, cpu_model, JAZZ_MAGNUM);
}
static
@@ -308,7 +312,8 @@ void mips_pica61_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_PICA61);
+ mips_jazz_init(get_system_memory(), get_system_io(),
+ ram_size, cpu_model, JAZZ_PICA61);
}
static QEMUMachine mips_magnum_machine = {
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 0110daa1a3..1ec1228b87 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -778,7 +778,7 @@ void mips_malta_init (ram_addr_t ram_size,
int64_t kernel_entry;
PCIBus *pci_bus;
CPUState *env;
- qemu_irq *i8259;
+ qemu_irq *i8259 = NULL, *isa_irq;
qemu_irq *cpu_exit_irq;
int piix4_devfn;
i2c_bus *smbus;
@@ -928,17 +928,27 @@ void mips_malta_init (ram_addr_t ram_size,
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
- /* Interrupt controller */
- /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
- i8259 = i8259_init(env->irq[2]);
+ /*
+ * We have a circular dependency problem: pci_bus depends on isa_irq,
+ * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
+ * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
+ * qemu_irq_proxy() adds an extra bit of indirection, allowing us
+ * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
+ */
+ isa_irq = qemu_irq_proxy(&i8259, 16);
/* Northbridge */
- pci_bus = gt64120_register(i8259);
+ pci_bus = gt64120_register(isa_irq);
/* Southbridge */
ide_drive_get(hd, MAX_IDE_BUS);
piix4_devfn = piix4_init(pci_bus, 80);
+
+ /* Interrupt controller */
+ /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
+ i8259 = i8259_init(env->irq[2]);
+
isa_bus_irqs(i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 805d02a4eb..d0564d4449 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -256,8 +256,8 @@ void mips_r4k_init (ram_addr_t ram_size,
cpu_mips_clock_init(env);
/* The PIC is attached to the MIPS CPU INT0 pin */
+ isa_bus_new(NULL, get_system_io());
i8259 = i8259_init(env->irq[2]);
- isa_bus_new(NULL);
isa_bus_irqs(i8259);
rtc_init(2000, NULL);
diff --git a/hw/nseries.c b/hw/nseries.c
index af287dd6dc..eb991431a4 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -199,7 +199,9 @@ static void n8x0_i2c_setup(struct n800_s *s)
/* Attach a menelaus PM chip */
dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
- qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
+ qdev_connect_gpio_out(dev, 3,
+ qdev_get_gpio_in(s->cpu->ih[0],
+ OMAP_INT_24XX_SYS_NIRQ));
/* Attach a TMP105 PM chip (A0 wired to ground) */
dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
diff --git a/hw/omap.h b/hw/omap.h
index 0260cc0d4a..cc09a3c0ee 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -99,18 +99,6 @@ target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write, void *opaque);
-/* OMAP interrupt controller */
-struct omap_intr_handler_s;
-struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
- unsigned long size, unsigned char nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
-struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
- int size, int nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq,
- omap_clk fclk, omap_clk iclk);
-void omap_inth_reset(struct omap_intr_handler_s *s);
-qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n);
-
/* OMAP2 SDRAM controller */
struct omap_sdrc_s;
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
@@ -692,9 +680,6 @@ struct uWireSlave {
void *opaque;
};
struct omap_uwire_s;
-struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq dma, omap_clk clk);
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect);
@@ -732,9 +717,6 @@ struct I2SCodec {
} in, out;
};
struct omap_mcbsp_s;
-struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq *dma, omap_clk clk);
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
void omap_tap_init(struct omap_target_agent_s *ta,
@@ -823,7 +805,6 @@ struct omap_mpu_state_s {
CPUState *env;
- qemu_irq *irq[2];
qemu_irq *drq;
qemu_irq wakeup;
@@ -896,7 +877,7 @@ struct omap_mpu_state_s {
struct omap_lpg_s *led[2];
/* MPU private TIPB peripherals */
- struct omap_intr_handler_s *ih[2];
+ DeviceState *ih[2];
struct soc_dma_s *dma;
diff --git a/hw/omap1.c b/hw/omap1.c
index f747321e97..619812c176 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -524,7 +524,7 @@ static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
s->ulpd_pm_regs[addr >> 2] = 0;
- qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
+ qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
return ret;
case 0x18: /* Reserved */
@@ -625,7 +625,7 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
- qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
+ qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
}
}
s->ulpd_pm_regs[addr >> 2] = value;
@@ -2257,15 +2257,17 @@ static void omap_uwire_reset(struct omap_uwire_s *s)
s->setup[4] = 0;
}
-struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq dma, omap_clk clk)
+static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
+ qemu_irq txirq, qemu_irq rxirq,
+ qemu_irq dma,
+ omap_clk clk)
{
struct omap_uwire_s *s = (struct omap_uwire_s *)
g_malloc0(sizeof(struct omap_uwire_s));
- s->txirq = irq[0];
- s->rxirq = irq[1];
+ s->txirq = txirq;
+ s->rxirq = rxirq;
s->txdrq = dma;
omap_uwire_reset(s);
@@ -2873,14 +2875,15 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
}
static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, omap_clk clk)
+ target_phys_addr_t base,
+ qemu_irq timerirq, qemu_irq alarmirq,
+ omap_clk clk)
{
struct omap_rtc_s *s = (struct omap_rtc_s *)
g_malloc0(sizeof(struct omap_rtc_s));
- s->irq = irq[0];
- s->alarm = irq[1];
+ s->irq = timerirq;
+ s->alarm = alarmirq;
s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
omap_rtc_reset(s);
@@ -3402,15 +3405,16 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
qemu_del_timer(s->sink_timer);
}
-struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq *dma, omap_clk clk)
+static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
+ qemu_irq txirq, qemu_irq rxirq,
+ qemu_irq *dma, omap_clk clk)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
g_malloc0(sizeof(struct omap_mcbsp_s));
- s->txirq = irq[0];
- s->rxirq = irq[1];
+ s->txirq = txirq;
+ s->rxirq = rxirq;
s->txdrq = dma[0];
s->rxdrq = dma[1];
s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
@@ -3642,8 +3646,6 @@ static void omap1_mpu_reset(void *opaque)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
- omap_inth_reset(mpu->ih[0]);
- omap_inth_reset(mpu->ih[1]);
omap_dma_reset(mpu->dma);
omap_mpu_timer_reset(mpu->timer[0]);
omap_mpu_timer_reset(mpu->timer[1]);
@@ -3796,6 +3798,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
qemu_irq *cpu_irq;
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
+ SysBusDevice *busdev;
if (!core)
core = "ti925t";
@@ -3824,17 +3827,30 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
cpu_irq = arm_pic_init_cpu(s->env);
- s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
- cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
- omap_findclk(s, "arminth_ck"));
- s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
- omap_inth_get_pin(s->ih[0], OMAP_INT_15XX_IH2_IRQ),
- NULL, omap_findclk(s, "arminth_ck"));
-
- for (i = 0; i < 6; i ++)
- dma_irqs[i] =
- s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
- s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
+ s->ih[0] = qdev_create(NULL, "omap-intc");
+ qdev_prop_set_uint32(s->ih[0], "size", 0x100);
+ qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
+ qdev_init_nofail(s->ih[0]);
+ busdev = sysbus_from_qdev(s->ih[0]);
+ sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
+ sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
+ sysbus_mmio_map(busdev, 0, 0xfffecb00);
+ s->ih[1] = qdev_create(NULL, "omap-intc");
+ qdev_prop_set_uint32(s->ih[1], "size", 0x800);
+ qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck"));
+ qdev_init_nofail(s->ih[1]);
+ busdev = sysbus_from_qdev(s->ih[1]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
+ /* The second interrupt controller's FIQ output is not wired up */
+ sysbus_mmio_map(busdev, 0, 0xfffe0000);
+
+ for (i = 0; i < 6; i++) {
+ dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
+ omap1_dma_irq_map[i].intr);
+ }
+ s->dma = omap_dma_init(0xfffed800, dma_irqs,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
s->port[emiff ].addr_valid = omap_validate_emiff_addr;
@@ -3851,25 +3867,27 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
OMAP_IMIF_BASE, s->sram_size);
s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
- s->irq[0][OMAP_INT_TIMER1],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
omap_findclk(s, "mputim_ck"));
s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
- s->irq[0][OMAP_INT_TIMER2],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
omap_findclk(s, "mputim_ck"));
s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
- s->irq[0][OMAP_INT_TIMER3],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
omap_findclk(s, "mputim_ck"));
s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
- s->irq[0][OMAP_INT_WD_TIMER],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
omap_findclk(s, "armwdt_ck"));
s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
- s->irq[1][OMAP_INT_OS_TIMER],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
omap_findclk(s, "clk32-kHz"));
- s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
- omap_dma_get_lcdch(s->dma), omap_findclk(s, "lcd_ck"));
+ s->lcd = omap_lcdc_init(0xfffec000,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
+ omap_dma_get_lcdch(s->dma),
+ omap_findclk(s, "lcd_ck"));
omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
omap_pin_cfg_init(system_memory, 0xfffe1000, s);
@@ -3878,27 +3896,30 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_mpui_init(system_memory, 0xfffec900, s);
s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
- s->irq[0][OMAP_INT_BRIDGE_PRIV],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
omap_findclk(s, "tipb_ck"));
s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
- s->irq[0][OMAP_INT_BRIDGE_PUB],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
omap_findclk(s, "tipb_ck"));
omap_tcmi_init(system_memory, 0xfffecc00, s);
- s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
+ s->uart[0] = omap_uart_init(0xfffb0000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
omap_findclk(s, "uart1_ck"),
omap_findclk(s, "uart1_ck"),
s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
"uart1",
serial_hds[0]);
- s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
+ s->uart[1] = omap_uart_init(0xfffb0800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
omap_findclk(s, "uart2_ck"),
omap_findclk(s, "uart2_ck"),
s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
"uart2",
serial_hds[0] ? serial_hds[1] : NULL);
- s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],
+ s->uart[2] = omap_uart_init(0xfffb9800,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
omap_findclk(s, "uart3_ck"),
omap_findclk(s, "uart3_ck"),
s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
@@ -3918,42 +3939,53 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
exit(1);
}
s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
- s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
+ &s->drq[OMAP_DMA_MMC_TX],
omap_findclk(s, "mmc_ck"));
s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
- s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
- s->wakeup, omap_findclk(s, "clk32-kHz"));
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
+ s->wakeup, omap_findclk(s, "clk32-kHz"));
s->gpio = qdev_create(NULL, "omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
+ qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck"));
qdev_init_nofail(s->gpio);
sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
- s->irq[0][OMAP_INT_GPIO_BANK1]);
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000);
- s->microwire = omap_uwire_init(system_memory,
- 0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
+ s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck"));
omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck"));
- s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
+ s->i2c[0] = omap_i2c_init(0xfffb3800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
- &s->irq[1][OMAP_INT_RTC_TIMER],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
omap_findclk(s, "clk32-kHz"));
- s->mcbsp1 = omap_mcbsp_init(system_memory,
- 0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
+ s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
&s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
- s->mcbsp2 = omap_mcbsp_init(system_memory,
- 0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
+ s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_310_McBSP2_TX),
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_310_McBSP2_RX),
&s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
- s->mcbsp3 = omap_mcbsp_init(system_memory,
- 0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
+ s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
&s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
s->led[0] = omap_lpg_init(system_memory,
diff --git a/hw/omap2.c b/hw/omap2.c
index 3d529cefd6..838c32f371 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -2180,7 +2180,6 @@ static void omap2_mpu_reset(void *opaque)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
- omap_inth_reset(mpu->ih[0]);
omap_dma_reset(mpu->dma);
omap_prcm_reset(mpu->prcm);
omap_sysctl_reset(mpu->sysc);
@@ -2264,20 +2263,27 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
cpu_irq = arm_pic_init_cpu(s->env);
- s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
- cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
- omap_findclk(s, "mpu_intc_fclk"),
- omap_findclk(s, "mpu_intc_iclk"));
-
+ s->ih[0] = qdev_create(NULL, "omap2-intc");
+ qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
+ qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
+ qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
+ qdev_init_nofail(s->ih[0]);
+ busdev = sysbus_from_qdev(s->ih[0]);
+ sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
+ sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
+ sysbus_mmio_map(busdev, 0, 0x480fe000);
s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
- s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_PRCM_MPU_IRQ),
+ NULL, NULL, s);
s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
omap_findclk(s, "omapctrl_iclk"), s);
- for (i = 0; i < 4; i ++)
- dma_irqs[i] =
- s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
+ for (i = 0; i < 4; i++) {
+ dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
+ omap2_dma_irq_map[i].intr);
+ }
s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
omap_findclk(s, "sdma_iclk"),
omap_findclk(s, "sdma_fclk"));
@@ -2290,7 +2296,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
- s->irq[0][OMAP_INT_24XX_UART1_IRQ],
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART1_IRQ),
omap_findclk(s, "uart1_fclk"),
omap_findclk(s, "uart1_iclk"),
s->drq[OMAP24XX_DMA_UART1_TX],
@@ -2298,7 +2305,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
"uart1",
serial_hds[0]);
s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
- s->irq[0][OMAP_INT_24XX_UART2_IRQ],
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART2_IRQ),
omap_findclk(s, "uart2_fclk"),
omap_findclk(s, "uart2_iclk"),
s->drq[OMAP24XX_DMA_UART2_TX],
@@ -2306,7 +2314,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
"uart2",
serial_hds[0] ? serial_hds[1] : NULL);
s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
- s->irq[0][OMAP_INT_24XX_UART3_IRQ],
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART3_IRQ),
omap_findclk(s, "uart3_fclk"),
omap_findclk(s, "uart3_iclk"),
s->drq[OMAP24XX_DMA_UART3_TX],
@@ -2315,51 +2324,51 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
- s->irq[0][OMAP_INT_24XX_GPTIMER1],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
omap_findclk(s, "wu_gpt1_clk"),
omap_findclk(s, "wu_l4_iclk"));
s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
- s->irq[0][OMAP_INT_24XX_GPTIMER2],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
omap_findclk(s, "core_gpt2_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
- s->irq[0][OMAP_INT_24XX_GPTIMER3],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
omap_findclk(s, "core_gpt3_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
- s->irq[0][OMAP_INT_24XX_GPTIMER4],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
omap_findclk(s, "core_gpt4_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
- s->irq[0][OMAP_INT_24XX_GPTIMER5],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
omap_findclk(s, "core_gpt5_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
- s->irq[0][OMAP_INT_24XX_GPTIMER6],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
omap_findclk(s, "core_gpt6_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
- s->irq[0][OMAP_INT_24XX_GPTIMER7],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
omap_findclk(s, "core_gpt7_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
- s->irq[0][OMAP_INT_24XX_GPTIMER8],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
omap_findclk(s, "core_gpt8_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
- s->irq[0][OMAP_INT_24XX_GPTIMER9],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
omap_findclk(s, "core_gpt9_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
- s->irq[0][OMAP_INT_24XX_GPTIMER10],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
omap_findclk(s, "core_gpt10_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
- s->irq[0][OMAP_INT_24XX_GPTIMER11],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
omap_findclk(s, "core_gpt11_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
- s->irq[0][OMAP_INT_24XX_GPTIMER12],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
omap_findclk(s, "core_gpt12_clk"),
omap_findclk(s, "core_l4_iclk"));
@@ -2370,12 +2379,12 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_findclk(s, "core_l4_iclk"));
s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
- s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ),
&s->drq[OMAP24XX_DMA_I2C1_TX],
omap_findclk(s, "i2c1.fclk"),
omap_findclk(s, "i2c1.iclk"));
s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
- s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ),
&s->drq[OMAP24XX_DMA_I2C2_TX],
omap_findclk(s, "i2c2.fclk"),
omap_findclk(s, "i2c2.iclk"));
@@ -2392,10 +2401,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
}
qdev_init_nofail(s->gpio);
busdev = sysbus_from_qdev(s->gpio);
- sysbus_connect_irq(busdev, 0, s->irq[0][OMAP_INT_24XX_GPIO_BANK1]);
- sysbus_connect_irq(busdev, 3, s->irq[0][OMAP_INT_24XX_GPIO_BANK2]);
- sysbus_connect_irq(busdev, 6, s->irq[0][OMAP_INT_24XX_GPIO_BANK3]);
- sysbus_connect_irq(busdev, 9, s->irq[0][OMAP_INT_24XX_GPIO_BANK4]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
+ sysbus_connect_irq(busdev, 3,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
+ sysbus_connect_irq(busdev, 6,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
+ sysbus_connect_irq(busdev, 9,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
ta = omap_l4ta(s->l4, 3);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
@@ -2404,7 +2417,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
s->sdrc = omap_sdrc_init(0x68009000);
- s->gpmc = omap_gpmc_init(s, 0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ],
+ s->gpmc = omap_gpmc_init(s, 0x6800a000,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
s->drq[OMAP24XX_DMA_GPMC]);
dinfo = drive_get(IF_SD, 0, 0);
@@ -2413,36 +2427,38 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
exit(1);
}
s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
- s->irq[0][OMAP_INT_24XX_MMC_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
&s->drq[OMAP24XX_DMA_MMC1_TX],
omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
- s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
&s->drq[OMAP24XX_DMA_SPI1_TX0],
omap_findclk(s, "spi1_fclk"),
omap_findclk(s, "spi1_iclk"));
s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
- s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
&s->drq[OMAP24XX_DMA_SPI2_TX0],
omap_findclk(s, "spi2_fclk"),
omap_findclk(s, "spi2_iclk"));
s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
/* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
- s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
+ s->drq[OMAP24XX_DMA_DSS],
omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
omap_findclk(s, "dss_54m_clk"),
omap_findclk(s, "dss_l3_iclk"),
omap_findclk(s, "dss_l4_iclk"));
omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
- s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
+ omap_findclk(s, "emul_ck"),
serial_hds[0] && serial_hds[1] && serial_hds[2] ?
serial_hds[3] : NULL);
s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
- s->irq[0][OMAP_INT_24XX_EAC_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
/* Ten consecutive lines */
&s->drq[OMAP24XX_DMA_EAC_AC_RD],
omap_findclk(s, "func_96m_clk"),
diff --git a/hw/omap_intc.c b/hw/omap_intc.c
index f1f570e4a6..0f7fd9dd4c 100644
--- a/hw/omap_intc.c
+++ b/hw/omap_intc.c
@@ -19,6 +19,7 @@
*/
#include "hw.h"
#include "omap.h"
+#include "sysbus.h"
/* Interrupt Handlers */
struct omap_intr_handler_bank_s {
@@ -32,24 +33,26 @@ struct omap_intr_handler_bank_s {
};
struct omap_intr_handler_s {
+ SysBusDevice busdev;
qemu_irq *pins;
qemu_irq parent_intr[2];
+ MemoryRegion mmio;
+ void *iclk;
+ void *fclk;
unsigned char nbanks;
int level_only;
+ uint32_t size;
+
+ uint8_t revision;
/* state */
uint32_t new_agr[2];
int sir_intr[2];
int autoidle;
uint32_t mask;
- struct omap_intr_handler_bank_s bank[];
+ struct omap_intr_handler_bank_s bank[3];
};
-inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n)
-{
- return s->pins[n];
-}
-
static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
{
int i, j, sir_intr, p_intr, p, f;
@@ -142,7 +145,8 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
-static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
@@ -220,7 +224,7 @@ static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
}
static void omap_inth_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
@@ -312,20 +316,20 @@ static void omap_inth_write(void *opaque, target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap_inth_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_inth_read,
+static const MemoryRegionOps omap_inth_mem_ops = {
+ .read = omap_inth_read,
+ .write = omap_inth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static CPUWriteMemoryFunc * const omap_inth_writefn[] = {
- omap_inth_write,
- omap_inth_write,
- omap_inth_write,
-};
-
-void omap_inth_reset(struct omap_intr_handler_s *s)
+static void omap_inth_reset(DeviceState *dev)
{
+ struct omap_intr_handler_s *s = FROM_SYSBUS(struct omap_intr_handler_s,
+ sysbus_from_qdev(dev));
int i;
for (i = 0; i < s->nbanks; ++i){
@@ -352,32 +356,37 @@ void omap_inth_reset(struct omap_intr_handler_s *s)
qemu_set_irq(s->parent_intr[1], 0);
}
-struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
- unsigned long size, unsigned char nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
+static int omap_intc_init(SysBusDevice *dev)
{
- int iomemtype;
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
- g_malloc0(sizeof(struct omap_intr_handler_s) +
- sizeof(struct omap_intr_handler_bank_s) * nbanks);
-
- s->parent_intr[0] = parent_irq;
- s->parent_intr[1] = parent_fiq;
- s->nbanks = nbanks;
- s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
- if (pins)
- *pins = s->pins;
-
- omap_inth_reset(s);
-
- iomemtype = cpu_register_io_memory(omap_inth_readfn,
- omap_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, iomemtype);
-
- return s;
+ struct omap_intr_handler_s *s;
+ s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
+ if (!s->iclk) {
+ hw_error("omap-intc: clk not connected\n");
+ }
+ s->nbanks = 1;
+ sysbus_init_irq(dev, &s->parent_intr[0]);
+ sysbus_init_irq(dev, &s->parent_intr[1]);
+ qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s,
+ "omap-intc", s->size);
+ sysbus_init_mmio_region(dev, &s->mmio);
+ return 0;
}
-static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
+static SysBusDeviceInfo omap_intc_info = {
+ .init = omap_intc_init,
+ .qdev.name = "omap-intc",
+ .qdev.size = sizeof(struct omap_intr_handler_s),
+ .qdev.reset = omap_inth_reset,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
+ DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
+ DEFINE_PROP_END_OF_LIST()
+ }
+};
+
+static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
@@ -394,7 +403,7 @@ static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
switch (offset) {
case 0x00: /* INTC_REVISION */
- return 0x21;
+ return s->revision;
case 0x10: /* INTC_SYSCONFIG */
return (s->autoidle >> 2) & 1;
@@ -455,7 +464,7 @@ static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
}
static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
@@ -475,7 +484,7 @@ static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
s->autoidle &= 4;
s->autoidle |= (value & 1) << 2;
if (value & 2) /* SOFTRESET */
- omap_inth_reset(s);
+ omap_inth_reset(&s->busdev.qdev);
return;
case 0x48: /* INTC_CONTROL */
@@ -558,41 +567,55 @@ static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap2_inth_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap2_inth_read,
-};
-
-static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
- omap2_inth_write,
- omap2_inth_write,
- omap2_inth_write,
+static const MemoryRegionOps omap2_inth_mem_ops = {
+ .read = omap2_inth_read,
+ .write = omap2_inth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
- int size, int nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq,
- omap_clk fclk, omap_clk iclk)
+static int omap2_intc_init(SysBusDevice *dev)
{
- int iomemtype;
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
- g_malloc0(sizeof(struct omap_intr_handler_s) +
- sizeof(struct omap_intr_handler_bank_s) * nbanks);
-
- s->parent_intr[0] = parent_irq;
- s->parent_intr[1] = parent_fiq;
- s->nbanks = nbanks;
+ struct omap_intr_handler_s *s;
+ s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
+ if (!s->iclk) {
+ hw_error("omap2-intc: iclk not connected\n");
+ }
+ if (!s->fclk) {
+ hw_error("omap2-intc: fclk not connected\n");
+ }
s->level_only = 1;
- s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
- if (pins)
- *pins = s->pins;
-
- omap_inth_reset(s);
+ s->nbanks = 3;
+ sysbus_init_irq(dev, &s->parent_intr[0]);
+ sysbus_init_irq(dev, &s->parent_intr[1]);
+ qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s,
+ "omap2-intc", 0x1000);
+ sysbus_init_mmio_region(dev, &s->mmio);
+ return 0;
+}
- iomemtype = cpu_register_io_memory(omap2_inth_readfn,
- omap2_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, iomemtype);
+static SysBusDeviceInfo omap2_intc_info = {
+ .init = omap2_intc_init,
+ .qdev.name = "omap2-intc",
+ .qdev.size = sizeof(struct omap_intr_handler_s),
+ .qdev.reset = omap_inth_reset,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
+ revision, 0x21),
+ DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
+ DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
+ DEFINE_PROP_END_OF_LIST()
+ }
+};
- return s;
+static void omap_intc_register_device(void)
+{
+ sysbus_register_withprop(&omap_intc_info);
+ sysbus_register_withprop(&omap2_intc_info);
}
+
+device_init(omap_intc_register_device)
diff --git a/hw/pc.h b/hw/pc.h
index 8e75c71cf7..7e6ddbab82 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -118,7 +118,7 @@ void vmmouse_set_data(const uint32_t *data);
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
+ MemoryRegion *region, ram_addr_t size,
target_phys_addr_t mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 0144534e82..ce1c87fba9 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -130,17 +130,7 @@ static void pc_init1(MemoryRegion *system_memory,
pci_enabled ? rom_memory : system_memory, &ram_memory);
}
- if (!xen_enabled()) {
- cpu_irq = pc_allocate_cpu_irq();
- i8259 = i8259_init(cpu_irq[0]);
- } else {
- i8259 = xen_interrupt_controller_init();
- }
isa_irq_state = g_malloc0(sizeof(*isa_irq_state));
- isa_irq_state->i8259 = i8259;
- if (pci_enabled) {
- ioapic_init(isa_irq_state);
- }
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
if (pci_enabled) {
@@ -156,11 +146,23 @@ static void pc_init1(MemoryRegion *system_memory,
} else {
pci_bus = NULL;
i440fx_state = NULL;
- isa_bus_new(NULL);
+ isa_bus_new(NULL, system_io);
no_hpet = 1;
}
isa_bus_irqs(isa_irq);
+ if (!xen_enabled()) {
+ cpu_irq = pc_allocate_cpu_irq();
+ i8259 = i8259_init(cpu_irq[0]);
+ } else {
+ i8259 = xen_interrupt_controller_init();
+ }
+
+ isa_irq_state->i8259 = i8259;
+ if (pci_enabled) {
+ ioapic_init(isa_irq_state);
+ }
+
pc_register_ferr_irq(isa_get_irq(13));
pc_vga_init(pci_enabled? pci_bus: NULL);
diff --git a/hw/pci.c b/hw/pci.c
index 5c4f071d28..749e8d86ca 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -2124,3 +2124,8 @@ MemoryRegion *pci_address_space(PCIDevice *dev)
{
return dev->bus->address_space_mem;
}
+
+MemoryRegion *pci_address_space_io(PCIDevice *dev)
+{
+ return dev->bus->address_space_io;
+}
diff --git a/hw/pci.h b/hw/pci.h
index 7b62df16fb..86a81c8273 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -218,6 +218,7 @@ void pci_default_write_config(PCIDevice *d,
void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f);
MemoryRegion *pci_address_space(PCIDevice *dev);
+MemoryRegion *pci_address_space_io(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
diff --git a/hw/pckbd.c b/hw/pckbd.c
index a272ccdb78..06b40c540c 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -400,33 +400,27 @@ static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value
kbd_write_data(s, 0, value & 0xff);
}
-static CPUReadMemoryFunc * const kbd_mm_read[] = {
- &kbd_mm_readb,
- &kbd_mm_readb,
- &kbd_mm_readb,
-};
-
-static CPUWriteMemoryFunc * const kbd_mm_write[] = {
- &kbd_mm_writeb,
- &kbd_mm_writeb,
- &kbd_mm_writeb,
+static const MemoryRegionOps i8042_mmio_ops = {
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .old_mmio = {
+ .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb },
+ .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb },
+ },
};
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
+ MemoryRegion *region, ram_addr_t size,
target_phys_addr_t mask)
{
KBDState *s = g_malloc0(sizeof(KBDState));
- int s_io_memory;
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
s->mask = mask;
vmstate_register(NULL, 0, &vmstate_kbd, s);
- s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s,
- DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, s_io_memory);
+
+ memory_region_init_io(region, &i8042_mmio_ops, s, "i8042", size);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
@@ -435,7 +429,8 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
typedef struct ISAKBDState {
ISADevice dev;
- KBDState kbd;
+ KBDState kbd;
+ MemoryRegion io[2];
} ISAKBDState;
void i8042_isa_mouse_fake_event(void *opaque)
@@ -464,19 +459,37 @@ static const VMStateDescription vmstate_kbd_isa = {
}
};
+static const MemoryRegionPortio i8042_data_portio[] = {
+ { 0, 1, 1, .read = kbd_read_data, .write = kbd_write_data },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionPortio i8042_cmd_portio[] = {
+ { 0, 1, 1, .read = kbd_read_status, .write = kbd_write_command },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps i8042_data_ops = {
+ .old_portio = i8042_data_portio
+};
+
+static const MemoryRegionOps i8042_cmd_ops = {
+ .old_portio = i8042_cmd_portio
+};
+
static int i8042_initfn(ISADevice *dev)
{
- KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
+ ISAKBDState *isa_s = DO_UPCAST(ISAKBDState, dev, dev);
+ KBDState *s = &isa_s->kbd;
isa_init_irq(dev, &s->irq_kbd, 1);
isa_init_irq(dev, &s->irq_mouse, 12);
- register_ioport_read(0x60, 1, 1, kbd_read_data, s);
- register_ioport_write(0x60, 1, 1, kbd_write_data, s);
- isa_init_ioport(dev, 0x60);
- register_ioport_read(0x64, 1, 1, kbd_read_status, s);
- register_ioport_write(0x64, 1, 1, kbd_write_command, s);
- isa_init_ioport(dev, 0x64);
+ memory_region_init_io(isa_s->io + 0, &i8042_data_ops, s, "i8042-data", 1);
+ isa_register_ioport(dev, isa_s->io + 0, 0x60);
+
+ memory_region_init_io(isa_s->io + 1, &i8042_cmd_ops, s, "i8042-cmd", 1);
+ isa_register_ioport(dev, isa_s->io + 1, 0x64);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
diff --git a/hw/piix4.c b/hw/piix4.c
index 9590e7b140..2fd1171328 100644
--- a/hw/piix4.c
+++ b/hw/piix4.c
@@ -87,7 +87,7 @@ static int piix4_initfn(PCIDevice *dev)
{
PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
- isa_bus_new(&d->dev.qdev);
+ isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
piix4_dev = &d->dev;
qemu_register_reset(piix4_reset, d);
return 0;
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 8f6ea42e2c..d183443b2f 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -504,7 +504,7 @@ static int piix3_initfn(PCIDevice *dev)
{
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
- isa_bus_new(&d->dev.qdev);
+ isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
qemu_register_reset(piix3_reset, d);
return 0;
}
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 515de42da4..d26049b1d1 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -648,10 +648,10 @@ static void ppc_prep_init (ram_addr_t ram_size,
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
hw_error("Only 6xx bus is supported on PREP machine\n");
}
+ /* Hmm, prep has no pci-isa bridge ??? */
+ isa_bus_new(NULL, get_system_io());
i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io());
- /* Hmm, prep has no pci-isa bridge ??? */
- isa_bus_new(NULL);
isa_bus_irqs(i8259);
// pci_bus = i440fx_init();
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
diff --git a/hw/serial.c b/hw/serial.c
index ed7fd0aae0..2e6d2122d0 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -157,6 +157,7 @@ struct SerialState {
typedef struct ISASerialState {
ISADevice dev;
+ MemoryRegion io;
uint32_t index;
uint32_t iobase;
uint32_t isairq;
@@ -755,6 +756,15 @@ void serial_set_frequency(SerialState *s, uint32_t frequency)
static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
+static const MemoryRegionPortio serial_portio[] = {
+ { 0, 8, 1, .read = serial_ioport_read, .write = serial_ioport_write },
+ PORTIO_END_OF_LIST()
+};
+
+static const MemoryRegionOps serial_io_ops = {
+ .old_portio = serial_portio
+};
+
static int serial_isa_initfn(ISADevice *dev)
{
static int index;
@@ -776,9 +786,8 @@ static int serial_isa_initfn(ISADevice *dev)
serial_init_core(s);
qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
- register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
- register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
- isa_init_ioport_range(dev, isa->iobase, 8);
+ memory_region_init_io(&isa->io, &serial_io_ops, s, "serial", 8);
+ isa_register_ioport(dev, &isa->io, isa->iobase);
return 0;
}
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 6afb0e7158..fbef350a44 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -548,7 +548,7 @@ pci_ebus_init1(PCIDevice *pci_dev)
{
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
- isa_bus_new(&pci_dev->qdev);
+ isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
pci_dev->config[0x05] = 0x00;
diff --git a/hw/vt82c686.c b/hw/vt82c686.c
index b9fcc0e4ac..284595905d 100644
--- a/hw/vt82c686.c
+++ b/hw/vt82c686.c
@@ -490,7 +490,7 @@ static int vt82c686b_initfn(PCIDevice *d)
uint8_t *wmask;
int i;
- isa_bus_new(&d->qdev);
+ isa_bus_new(&d->qdev, pci_address_space_io(d));
pci_conf = d->config;
pci_config_set_prog_interface(pci_conf, 0x0);
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 04e8e6e065..8677bba0d8 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -332,6 +332,49 @@ enum
ARM_HWCAP_ARM_VFPv3D16 = 1 << 13,
};
+#define TARGET_HAS_GUEST_VALIDATE_BASE
+/* We want the opportunity to check the suggested base */
+bool guest_validate_base(unsigned long guest_base)
+{
+ unsigned long real_start, test_page_addr;
+
+ /* We need to check that we can force a fault on access to the
+ * commpage at 0xffff0fxx
+ */
+ test_page_addr = guest_base + (0xffff0f00 & qemu_host_page_mask);
+ /* Note it needs to be writeable to let us initialise it */
+ real_start = (unsigned long)
+ mmap((void *)test_page_addr, qemu_host_page_size,
+ PROT_READ | PROT_WRITE,
+ MAP_ANONYMOUS | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+
+ /* If we can't map it then try another address */
+ if (real_start == -1ul) {
+ return 0;
+ }
+
+ if (real_start != test_page_addr) {
+ /* OS didn't put the page where we asked - unmap and reject */
+ munmap((void *)real_start, qemu_host_page_size);
+ return 0;
+ }
+
+ /* Leave the page mapped
+ * Populate it (mmap should have left it all 0'd)
+ */
+
+ /* Kernel helper versions */
+ __put_user(5, (uint32_t *)g2h(0xffff0ffcul));
+
+ /* Now it's populated make it RO */
+ if (mprotect((void *)test_page_addr, qemu_host_page_size, PROT_READ)) {
+ perror("Protecting guest commpage");
+ exit(-1);
+ }
+
+ return 1; /* All good */
+}
+
#define ELF_HWCAP (ARM_HWCAP_ARM_SWP | ARM_HWCAP_ARM_HALF \
| ARM_HWCAP_ARM_THUMB | ARM_HWCAP_ARM_FAST_MULT \
| ARM_HWCAP_ARM_FPA | ARM_HWCAP_ARM_VFP \
@@ -1309,6 +1352,14 @@ static abi_ulong create_elf_tables(abi_ulong p, int argc, int envc,
return sp;
}
+#ifndef TARGET_HAS_GUEST_VALIDATE_BASE
+/* If the guest doesn't have a validation function just agree */
+bool guest_validate_base(unsigned long guest_base)
+{
+ return 1;
+}
+#endif
+
static void probe_guest_base(const char *image_name,
abi_ulong loaddr, abi_ulong hiaddr)
{
@@ -1345,7 +1396,9 @@ static void probe_guest_base(const char *image_name,
if (real_start == (unsigned long)-1) {
goto exit_perror;
}
- if (real_start == host_start) {
+ guest_base = real_start - loaddr;
+ if ((real_start == host_start) &&
+ guest_validate_base(guest_base)) {
break;
}
/* That address didn't work. Unmap and try a different one.
@@ -1368,7 +1421,6 @@ static void probe_guest_base(const char *image_name,
qemu_log("Relocating guest address space from 0x"
TARGET_ABI_FMT_lx " to 0x%lx\n",
loaddr, real_start);
- guest_base = real_start - loaddr;
}
return;
diff --git a/linux-user/main.c b/linux-user/main.c
index 89a51d76cd..186358bd63 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -39,6 +39,11 @@
char *exec_path;
int singlestep;
+const char *filename;
+const char *argv0;
+int gdbstub_port;
+envlist_t *envlist;
+const char *cpu_model;
unsigned long mmap_min_addr;
#if defined(CONFIG_USE_GUEST_BASE)
unsigned long guest_base;
@@ -46,6 +51,8 @@ int have_guest_base;
unsigned long reserved_va;
#endif
+static void usage(void);
+
static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
@@ -456,6 +463,83 @@ void cpu_loop(CPUX86State *env)
#ifdef TARGET_ARM
+/*
+ * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
+ * Input:
+ * r0 = pointer to oldval
+ * r1 = pointer to newval
+ * r2 = pointer to target value
+ *
+ * Output:
+ * r0 = 0 if *ptr was changed, non-0 if no exchange happened
+ * C set if *ptr was changed, clear if no exchange happened
+ *
+ * Note segv's in kernel helpers are a bit tricky, we can set the
+ * data address sensibly but the PC address is just the entry point.
+ */
+static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
+{
+ uint64_t oldval, newval, val;
+ uint32_t addr, cpsr;
+ target_siginfo_t info;
+
+ /* Based on the 32 bit code in do_kernel_trap */
+
+ /* XXX: This only works between threads, not between processes.
+ It's probably possible to implement this with native host
+ operations. However things like ldrex/strex are much harder so
+ there's not much point trying. */
+ start_exclusive();
+ cpsr = cpsr_read(env);
+ addr = env->regs[2];
+
+ if (get_user_u64(oldval, env->regs[0])) {
+ env->cp15.c6_data = env->regs[0];
+ goto segv;
+ };
+
+ if (get_user_u64(newval, env->regs[1])) {
+ env->cp15.c6_data = env->regs[1];
+ goto segv;
+ };
+
+ if (get_user_u64(val, addr)) {
+ env->cp15.c6_data = addr;
+ goto segv;
+ }
+
+ if (val == oldval) {
+ val = newval;
+
+ if (put_user_u64(val, addr)) {
+ env->cp15.c6_data = addr;
+ goto segv;
+ };
+
+ env->regs[0] = 0;
+ cpsr |= CPSR_C;
+ } else {
+ env->regs[0] = -1;
+ cpsr &= ~CPSR_C;
+ }
+ cpsr_write(env, cpsr, CPSR_C);
+ end_exclusive();
+ return;
+
+segv:
+ end_exclusive();
+ /* We get the PC of the entry address - which is as good as anything,
+ on a real kernel what you get depends on which mode it uses. */
+ info.si_signo = SIGSEGV;
+ info.si_errno = 0;
+ /* XXX: check env->error_code */
+ info.si_code = TARGET_SEGV_MAPERR;
+ info._sifields._sigfault._addr = env->cp15.c6_data;
+ queue_signal(env, info.si_signo, &info);
+
+ end_exclusive();
+}
+
/* Handle a jump to the kernel code page. */
static int
do_kernel_trap(CPUARMState *env)
@@ -495,6 +579,10 @@ do_kernel_trap(CPUARMState *env)
case 0xffff0fe0: /* __kernel_get_tls */
env->regs[0] = env->cp15.c13_tls2;
break;
+ case 0xffff0f60: /* __kernel_cmpxchg64 */
+ arm_kernel_cmpxchg64_helper(env);
+ break;
+
default:
return 1;
}
@@ -752,7 +840,6 @@ void cpu_loop(CPUARMState *env)
goto do_segv;
case EXCP_DATA_ABORT:
addr = env->cp15.c6_data;
- goto do_segv;
do_segv:
{
info.si_signo = SIGSEGV;
@@ -1669,7 +1756,7 @@ void cpu_loop(CPUPPCState *env)
#define MIPS_SYS(name, args) args,
static const uint8_t mips_syscall_args[] = {
- MIPS_SYS(sys_syscall , 0) /* 4000 */
+ MIPS_SYS(sys_syscall , 8) /* 4000 */
MIPS_SYS(sys_exit , 1)
MIPS_SYS(sys_fork , 0)
MIPS_SYS(sys_read , 3)
@@ -2090,11 +2177,22 @@ void cpu_loop(CPUMIPSState *env)
sp_reg = env->active_tc.gpr[29];
switch (nb_args) {
/* these arguments are taken from the stack */
- /* FIXME - what to do if get_user() fails? */
- case 8: get_user_ual(arg8, sp_reg + 28);
- case 7: get_user_ual(arg7, sp_reg + 24);
- case 6: get_user_ual(arg6, sp_reg + 20);
- case 5: get_user_ual(arg5, sp_reg + 16);
+ case 8:
+ if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
+ goto done_syscall;
+ }
+ case 7:
+ if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
+ goto done_syscall;
+ }
+ case 6:
+ if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
+ goto done_syscall;
+ }
+ case 5:
+ if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
+ goto done_syscall;
+ }
default:
break;
}
@@ -2105,6 +2203,7 @@ void cpu_loop(CPUMIPSState *env)
env->active_tc.gpr[7],
arg5, arg6, arg7, arg8);
}
+done_syscall:
if (ret == -TARGET_QEMU_ESIGRETURN) {
/* Returning from a successful sigreturn syscall.
Avoid clobbering register state. */
@@ -2787,57 +2886,6 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
-static void version(void)
-{
- printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION
- ", Copyright (c) 2003-2008 Fabrice Bellard\n");
-}
-
-static void usage(void)
-{
- version();
- printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
- "Linux CPU emulator (compiled for %s emulation)\n"
- "\n"
- "Standard options:\n"
- "-h print this help\n"
- "-version display version information and exit\n"
- "-g port wait gdb connection to port\n"
- "-L path set the elf interpreter prefix (default=%s)\n"
- "-s size set the stack size in bytes (default=%ld)\n"
- "-cpu model select CPU (-cpu ? for list)\n"
- "-drop-ld-preload drop LD_PRELOAD for target process\n"
- "-E var=value sets/modifies targets environment variable(s)\n"
- "-U var unsets targets environment variable(s)\n"
- "-0 argv0 forces target process argv[0] to be argv0\n"
-#if defined(CONFIG_USE_GUEST_BASE)
- "-B address set guest_base address to address\n"
- "-R size reserve size bytes for guest virtual address space\n"
-#endif
- "\n"
- "Debug options:\n"
- "-d options activate log (logfile=%s)\n"
- "-p pagesize set the host page size to 'pagesize'\n"
- "-singlestep always run in singlestep mode\n"
- "-strace log system calls\n"
- "\n"
- "Environment variables:\n"
- "QEMU_STRACE Print system calls and arguments similar to the\n"
- " 'strace' program. Enable by setting to any value.\n"
- "You can use -E and -U options to set/unset environment variables\n"
- "for target process. It is possible to provide several variables\n"
- "by repeating the option. For example:\n"
- " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
- "Note that if you provide several changes to single variable\n"
- "last change will stay in effect.\n"
- ,
- TARGET_ARCH,
- interp_prefix,
- guest_stack_size,
- DEBUG_LOGFILE);
- exit(1);
-}
-
THREAD CPUState *thread_env;
void task_settid(TaskState *ts)
@@ -2873,26 +2921,358 @@ void init_task_state(TaskState *ts)
}
ts->sigqueue_table[i].next = NULL;
}
-
+
+static void handle_arg_help(const char *arg)
+{
+ usage();
+}
+
+static void handle_arg_log(const char *arg)
+{
+ int mask;
+ const CPULogItem *item;
+
+ mask = cpu_str_to_log_mask(arg);
+ if (!mask) {
+ printf("Log items (comma separated):\n");
+ for (item = cpu_log_items; item->mask != 0; item++) {
+ printf("%-10s %s\n", item->name, item->help);
+ }
+ exit(1);
+ }
+ cpu_set_log(mask);
+}
+
+static void handle_arg_set_env(const char *arg)
+{
+ char *r, *p, *token;
+ r = p = strdup(arg);
+ while ((token = strsep(&p, ",")) != NULL) {
+ if (envlist_setenv(envlist, token) != 0) {
+ usage();
+ }
+ }
+ free(r);
+}
+
+static void handle_arg_unset_env(const char *arg)
+{
+ char *r, *p, *token;
+ r = p = strdup(arg);
+ while ((token = strsep(&p, ",")) != NULL) {
+ if (envlist_unsetenv(envlist, token) != 0) {
+ usage();
+ }
+ }
+ free(r);
+}
+
+static void handle_arg_argv0(const char *arg)
+{
+ argv0 = strdup(arg);
+}
+
+static void handle_arg_stack_size(const char *arg)
+{
+ char *p;
+ guest_stack_size = strtoul(arg, &p, 0);
+ if (guest_stack_size == 0) {
+ usage();
+ }
+
+ if (*p == 'M') {
+ guest_stack_size *= 1024 * 1024;
+ } else if (*p == 'k' || *p == 'K') {
+ guest_stack_size *= 1024;
+ }
+}
+
+static void handle_arg_ld_prefix(const char *arg)
+{
+ interp_prefix = strdup(arg);
+}
+
+static void handle_arg_pagesize(const char *arg)
+{
+ qemu_host_page_size = atoi(arg);
+ if (qemu_host_page_size == 0 ||
+ (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
+ fprintf(stderr, "page size must be a power of two\n");
+ exit(1);
+ }
+}
+
+static void handle_arg_gdb(const char *arg)
+{
+ gdbstub_port = atoi(arg);
+}
+
+static void handle_arg_uname(const char *arg)
+{
+ qemu_uname_release = strdup(arg);
+}
+
+static void handle_arg_cpu(const char *arg)
+{
+ cpu_model = strdup(arg);
+ if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
+ /* XXX: implement xxx_cpu_list for targets that still miss it */
+#if defined(cpu_list_id)
+ cpu_list_id(stdout, &fprintf, "");
+#elif defined(cpu_list)
+ cpu_list(stdout, &fprintf); /* deprecated */
+#endif
+ exit(1);
+ }
+}
+
+#if defined(CONFIG_USE_GUEST_BASE)
+static void handle_arg_guest_base(const char *arg)
+{
+ guest_base = strtol(arg, NULL, 0);
+ have_guest_base = 1;
+}
+
+static void handle_arg_reserved_va(const char *arg)
+{
+ char *p;
+ int shift = 0;
+ reserved_va = strtoul(arg, &p, 0);
+ switch (*p) {
+ case 'k':
+ case 'K':
+ shift = 10;
+ break;
+ case 'M':
+ shift = 20;
+ break;
+ case 'G':
+ shift = 30;
+ break;
+ }
+ if (shift) {
+ unsigned long unshifted = reserved_va;
+ p++;
+ reserved_va <<= shift;
+ if (((reserved_va >> shift) != unshifted)
+#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
+ || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
+#endif
+ ) {
+ fprintf(stderr, "Reserved virtual address too big\n");
+ exit(1);
+ }
+ }
+ if (*p) {
+ fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
+ exit(1);
+ }
+}
+#endif
+
+static void handle_arg_singlestep(const char *arg)
+{
+ singlestep = 1;
+}
+
+static void handle_arg_strace(const char *arg)
+{
+ do_strace = 1;
+}
+
+static void handle_arg_version(const char *arg)
+{
+ printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION
+ ", Copyright (c) 2003-2008 Fabrice Bellard\n");
+}
+
+struct qemu_argument {
+ const char *argv;
+ const char *env;
+ bool has_arg;
+ void (*handle_opt)(const char *arg);
+ const char *example;
+ const char *help;
+};
+
+struct qemu_argument arg_table[] = {
+ {"h", "", false, handle_arg_help,
+ "", "print this help"},
+ {"g", "QEMU_GDB", true, handle_arg_gdb,
+ "port", "wait gdb connection to 'port'"},
+ {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
+ "path", "set the elf interpreter prefix to 'path'"},
+ {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
+ "size", "set the stack size to 'size' bytes"},
+ {"cpu", "QEMU_CPU", true, handle_arg_cpu,
+ "model", "select CPU (-cpu ? for list)"},
+ {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
+ "var=value", "sets targets environment variable (see below)"},
+ {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
+ "var", "unsets targets environment variable (see below)"},
+ {"0", "QEMU_ARGV0", true, handle_arg_argv0,
+ "argv0", "forces target process argv[0] to be 'argv0'"},
+ {"r", "QEMU_UNAME", true, handle_arg_uname,
+ "uname", "set qemu uname release string to 'uname'"},
+#if defined(CONFIG_USE_GUEST_BASE)
+ {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
+ "address", "set guest_base address to 'address'"},
+ {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
+ "size", "reserve 'size' bytes for guest virtual address space"},
+#endif
+ {"d", "QEMU_LOG", true, handle_arg_log,
+ "options", "activate log"},
+ {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
+ "pagesize", "set the host page size to 'pagesize'"},
+ {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
+ "", "run in singlestep mode"},
+ {"strace", "QEMU_STRACE", false, handle_arg_strace,
+ "", "log system calls"},
+ {"version", "QEMU_VERSION", false, handle_arg_version,
+ "", "log system calls"},
+ {NULL, NULL, false, NULL, NULL, NULL}
+};
+
+static void usage(void)
+{
+ struct qemu_argument *arginfo;
+ int maxarglen;
+ int maxenvlen;
+
+ printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
+ "Linux CPU emulator (compiled for " TARGET_ARCH " emulation)\n"
+ "\n"
+ "Options and associated environment variables:\n"
+ "\n");
+
+ maxarglen = maxenvlen = 0;
+
+ for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
+ if (strlen(arginfo->env) > maxenvlen) {
+ maxenvlen = strlen(arginfo->env);
+ }
+ if (strlen(arginfo->argv) > maxarglen) {
+ maxarglen = strlen(arginfo->argv);
+ }
+ }
+
+ printf("%-*s%-*sDescription\n", maxarglen+3, "Argument",
+ maxenvlen+1, "Env-variable");
+
+ for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
+ if (arginfo->has_arg) {
+ printf("-%s %-*s %-*s %s\n", arginfo->argv,
+ (int)(maxarglen-strlen(arginfo->argv)), arginfo->example,
+ maxenvlen, arginfo->env, arginfo->help);
+ } else {
+ printf("-%-*s %-*s %s\n", maxarglen+1, arginfo->argv,
+ maxenvlen, arginfo->env,
+ arginfo->help);
+ }
+ }
+
+ printf("\n"
+ "Defaults:\n"
+ "QEMU_LD_PREFIX = %s\n"
+ "QEMU_STACK_SIZE = %ld byte\n"
+ "QEMU_LOG = %s\n",
+ interp_prefix,
+ guest_stack_size,
+ DEBUG_LOGFILE);
+
+ printf("\n"
+ "You can use -E and -U options or the QEMU_SET_ENV and\n"
+ "QEMU_UNSET_ENV environment variables to set and unset\n"
+ "environment variables for the target process.\n"
+ "It is possible to provide several variables by separating them\n"
+ "by commas in getsubopt(3) style. Additionally it is possible to\n"
+ "provide the -E and -U options multiple times.\n"
+ "The following lines are equivalent:\n"
+ " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
+ " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
+ " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
+ "Note that if you provide several changes to a single variable\n"
+ "the last change will stay in effect.\n");
+
+ exit(1);
+}
+
+static int parse_args(int argc, char **argv)
+{
+ const char *r;
+ int optind;
+ struct qemu_argument *arginfo;
+
+ for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
+ if (arginfo->env == NULL) {
+ continue;
+ }
+
+ r = getenv(arginfo->env);
+ if (r != NULL) {
+ arginfo->handle_opt(r);
+ }
+ }
+
+ optind = 1;
+ for (;;) {
+ if (optind >= argc) {
+ break;
+ }
+ r = argv[optind];
+ if (r[0] != '-') {
+ break;
+ }
+ optind++;
+ r++;
+ if (!strcmp(r, "-")) {
+ break;
+ }
+
+ for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
+ if (!strcmp(r, arginfo->argv)) {
+ if (optind >= argc) {
+ usage();
+ }
+
+ arginfo->handle_opt(argv[optind]);
+
+ if (arginfo->has_arg) {
+ optind++;
+ }
+
+ break;
+ }
+ }
+
+ /* no option matched the current argv */
+ if (arginfo->handle_opt == NULL) {
+ usage();
+ }
+ }
+
+ if (optind >= argc) {
+ usage();
+ }
+
+ filename = argv[optind];
+ exec_path = argv[optind];
+
+ return optind;
+}
+
int main(int argc, char **argv, char **envp)
{
- const char *filename;
- const char *cpu_model;
const char *log_file = DEBUG_LOGFILE;
- const char *log_mask = NULL;
struct target_pt_regs regs1, *regs = &regs1;
struct image_info info1, *info = &info1;
struct linux_binprm bprm;
TaskState *ts;
CPUState *env;
int optind;
- const char *r;
- int gdbstub_port = 0;
char **target_environ, **wrk;
char **target_argv;
int target_argc;
- envlist_t *envlist = NULL;
- const char *argv0 = NULL;
int i;
int ret;
@@ -2927,156 +3307,9 @@ int main(int argc, char **argv, char **envp)
cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
#endif
- optind = 1;
- for(;;) {
- if (optind >= argc)
- break;
- r = argv[optind];
- if (r[0] != '-')
- break;
- optind++;
- r++;
- if (!strcmp(r, "-")) {
- break;
- } else if (!strcmp(r, "d")) {
- if (optind >= argc) {
- break;
- }
- log_mask = argv[optind++];
- } else if (!strcmp(r, "D")) {
- if (optind >= argc) {
- break;
- }
- log_file = argv[optind++];
- } else if (!strcmp(r, "E")) {
- r = argv[optind++];
- if (envlist_setenv(envlist, r) != 0)
- usage();
- } else if (!strcmp(r, "ignore-environment")) {
- envlist_free(envlist);
- if ((envlist = envlist_create()) == NULL) {
- (void) fprintf(stderr, "Unable to allocate envlist\n");
- exit(1);
- }
- } else if (!strcmp(r, "U")) {
- r = argv[optind++];
- if (envlist_unsetenv(envlist, r) != 0)
- usage();
- } else if (!strcmp(r, "0")) {
- r = argv[optind++];
- argv0 = r;
- } else if (!strcmp(r, "s")) {
- if (optind >= argc)
- break;
- r = argv[optind++];
- guest_stack_size = strtoul(r, (char **)&r, 0);
- if (guest_stack_size == 0)
- usage();
- if (*r == 'M')
- guest_stack_size *= 1024 * 1024;
- else if (*r == 'k' || *r == 'K')
- guest_stack_size *= 1024;
- } else if (!strcmp(r, "L")) {
- interp_prefix = argv[optind++];
- } else if (!strcmp(r, "p")) {
- if (optind >= argc)
- break;
- qemu_host_page_size = atoi(argv[optind++]);
- if (qemu_host_page_size == 0 ||
- (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
- fprintf(stderr, "page size must be a power of two\n");
- exit(1);
- }
- } else if (!strcmp(r, "g")) {
- if (optind >= argc)
- break;
- gdbstub_port = atoi(argv[optind++]);
- } else if (!strcmp(r, "r")) {
- qemu_uname_release = argv[optind++];
- } else if (!strcmp(r, "cpu")) {
- cpu_model = argv[optind++];
- if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
-/* XXX: implement xxx_cpu_list for targets that still miss it */
-#if defined(cpu_list_id)
- cpu_list_id(stdout, &fprintf, "");
-#elif defined(cpu_list)
- cpu_list(stdout, &fprintf); /* deprecated */
-#endif
- exit(1);
- }
-#if defined(CONFIG_USE_GUEST_BASE)
- } else if (!strcmp(r, "B")) {
- guest_base = strtol(argv[optind++], NULL, 0);
- have_guest_base = 1;
- } else if (!strcmp(r, "R")) {
- char *p;
- int shift = 0;
- reserved_va = strtoul(argv[optind++], &p, 0);
- switch (*p) {
- case 'k':
- case 'K':
- shift = 10;
- break;
- case 'M':
- shift = 20;
- break;
- case 'G':
- shift = 30;
- break;
- }
- if (shift) {
- unsigned long unshifted = reserved_va;
- p++;
- reserved_va <<= shift;
- if (((reserved_va >> shift) != unshifted)
-#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
- || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
-#endif
- ) {
- fprintf(stderr, "Reserved virtual address too big\n");
- exit(1);
- }
- }
- if (*p) {
- fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
- exit(1);
- }
-#endif
- } else if (!strcmp(r, "drop-ld-preload")) {
- (void) envlist_unsetenv(envlist, "LD_PRELOAD");
- } else if (!strcmp(r, "singlestep")) {
- singlestep = 1;
- } else if (!strcmp(r, "strace")) {
- do_strace = 1;
- } else if (!strcmp(r, "version")) {
- version();
- exit(0);
- } else {
- usage();
- }
- }
/* init debug */
cpu_set_log_filename(log_file);
- if (log_mask) {
- int mask;
- const CPULogItem *item;
-
- mask = cpu_str_to_log_mask(log_mask);
- if (!mask) {
- printf("Log items (comma separated):\n");
- for (item = cpu_log_items; item->mask != 0; item++) {
- printf("%-10s %s\n", item->name, item->help);
- }
- exit(1);
- }
- cpu_set_log(mask);
- }
-
- if (optind >= argc) {
- usage();
- }
- filename = argv[optind];
- exec_path = argv[optind];
+ optind = parse_args(argc, argv);
/* Zero out regs */
memset(regs, 0, sizeof(struct target_pt_regs));
@@ -3180,6 +3413,13 @@ int main(int argc, char **argv, char **envp)
}
qemu_log("Reserved 0x%lx bytes of guest address space\n", reserved_va);
}
+
+ if (reserved_va || have_guest_base) {
+ if (!guest_validate_base(guest_base)) {
+ fprintf(stderr, "Guest base/Reserved VA rejected by guest code\n");
+ exit(1);
+ }
+ }
#endif /* CONFIG_USE_GUEST_BASE */
/*
@@ -3568,7 +3808,11 @@ int main(int argc, char **argv, char **envp)
#endif
if (gdbstub_port) {
- gdbserver_start (gdbstub_port);
+ if (gdbserver_start(gdbstub_port) < 0) {
+ fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
+ gdbstub_port);
+ exit(1);
+ }
gdb_handlesig(env, 0);
}
cpu_loop(env);
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 627c8b3423..55ad9d8586 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -202,6 +202,12 @@ int get_osversion(void);
void fork_start(void);
void fork_end(int child);
+/* Return true if the proposed guest_base is suitable for the guest.
+ * The guest code may leave a page mapped and populate it if the
+ * address is suitable.
+ */
+bool guest_validate_base(unsigned long guest_base);
+
#include "qemu-log.h"
/* strace.c */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 6b73769c34..7735008d6a 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -70,6 +70,9 @@ int __clone2(int (*fn)(void *), void *child_stack_base,
#ifdef CONFIG_EPOLL
#include <sys/epoll.h>
#endif
+#ifdef CONFIG_ATTR
+#include <attr/xattr.h>
+#endif
#define termios host_termios
#define winsize host_winsize
@@ -796,6 +799,15 @@ abi_long do_brk(abi_ulong new_brk)
MAP_ANON|MAP_PRIVATE, 0, 0));
if (mapped_addr == brk_page) {
+ /* Heap contents are initialized to zero, as for anonymous
+ * mapped pages. Technically the new pages are already
+ * initialized to zero since they *are* anonymous mapped
+ * pages, however we have to take care with the contents that
+ * come from the remaining part of the previous page: it may
+ * contains garbage data due to a previous heap usage (grown
+ * then shrunken). */
+ memset(g2h(target_brk), 0, brk_page - target_brk);
+
target_brk = new_brk;
brk_page = HOST_PAGE_ALIGN(target_brk);
DEBUGF_BRK("%#010x (mapped_addr == brk_page)\n", target_brk);
@@ -7632,22 +7644,67 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
#endif
break;
#endif
+#ifdef CONFIG_ATTR
#ifdef TARGET_NR_setxattr
- case TARGET_NR_setxattr:
case TARGET_NR_lsetxattr:
case TARGET_NR_fsetxattr:
- case TARGET_NR_getxattr:
case TARGET_NR_lgetxattr:
case TARGET_NR_fgetxattr:
case TARGET_NR_listxattr:
case TARGET_NR_llistxattr:
case TARGET_NR_flistxattr:
- case TARGET_NR_removexattr:
case TARGET_NR_lremovexattr:
case TARGET_NR_fremovexattr:
ret = -TARGET_EOPNOTSUPP;
break;
+ case TARGET_NR_setxattr:
+ {
+ void *p, *n, *v;
+ p = lock_user_string(arg1);
+ n = lock_user_string(arg2);
+ v = lock_user(VERIFY_READ, arg3, arg4, 1);
+ if (p && n && v) {
+ ret = get_errno(setxattr(p, n, v, arg4, arg5));
+ } else {
+ ret = -TARGET_EFAULT;
+ }
+ unlock_user(p, arg1, 0);
+ unlock_user(n, arg2, 0);
+ unlock_user(v, arg3, 0);
+ }
+ break;
+ case TARGET_NR_getxattr:
+ {
+ void *p, *n, *v;
+ p = lock_user_string(arg1);
+ n = lock_user_string(arg2);
+ v = lock_user(VERIFY_WRITE, arg3, arg4, 0);
+ if (p && n && v) {
+ ret = get_errno(getxattr(p, n, v, arg4));
+ } else {
+ ret = -TARGET_EFAULT;
+ }
+ unlock_user(p, arg1, 0);
+ unlock_user(n, arg2, 0);
+ unlock_user(v, arg3, arg4);
+ }
+ break;
+ case TARGET_NR_removexattr:
+ {
+ void *p, *n;
+ p = lock_user_string(arg1);
+ n = lock_user_string(arg2);
+ if (p && n) {
+ ret = get_errno(removexattr(p, n));
+ } else {
+ ret = -TARGET_EFAULT;
+ }
+ unlock_user(p, arg1, 0);
+ unlock_user(n, arg2, 0);
+ }
+ break;
#endif
+#endif /* CONFIG_ATTR */
#ifdef TARGET_NR_set_thread_area
case TARGET_NR_set_thread_area:
#if defined(TARGET_MIPS)
diff --git a/memory.c b/memory.c
index ba74435a9b..71e769e8b8 100644
--- a/memory.c
+++ b/memory.c
@@ -126,6 +126,7 @@ struct FlatRange {
AddrRange addr;
uint8_t dirty_log_mask;
bool readable;
+ bool readonly;
};
/* Flattened global view of current active memory hierarchy. Kept in sorted
@@ -166,7 +167,8 @@ static bool flatrange_equal(FlatRange *a, FlatRange *b)
return a->mr == b->mr
&& addrrange_equal(a->addr, b->addr)
&& a->offset_in_region == b->offset_in_region
- && a->readable == b->readable;
+ && a->readable == b->readable
+ && a->readonly == b->readonly;
}
static void flatview_init(FlatView *view)
@@ -203,7 +205,8 @@ static bool can_merge(FlatRange *r1, FlatRange *r2)
&& r1->mr == r2->mr
&& r1->offset_in_region + r1->addr.size == r2->offset_in_region
&& r1->dirty_log_mask == r2->dirty_log_mask
- && r1->readable == r2->readable;
+ && r1->readable == r2->readable
+ && r1->readonly == r2->readonly;
}
/* Attempt to simplify a view by merging ajacent ranges */
@@ -307,6 +310,10 @@ static void as_memory_range_add(AddressSpace *as, FlatRange *fr)
phys_offset &= ~TARGET_PAGE_MASK & ~IO_MEM_ROMD;
}
+ if (fr->readonly) {
+ phys_offset |= IO_MEM_ROM;
+ }
+
cpu_register_physical_memory_log(fr->addr.start,
fr->addr.size,
phys_offset,
@@ -484,7 +491,8 @@ static AddressSpace address_space_io = {
static void render_memory_region(FlatView *view,
MemoryRegion *mr,
target_phys_addr_t base,
- AddrRange clip)
+ AddrRange clip,
+ bool readonly)
{
MemoryRegion *subregion;
unsigned i;
@@ -495,6 +503,7 @@ static void render_memory_region(FlatView *view,
AddrRange tmp;
base += mr->addr;
+ readonly |= mr->readonly;
tmp = addrrange_make(base, mr->size);
@@ -507,13 +516,13 @@ static void render_memory_region(FlatView *view,
if (mr->alias) {
base -= mr->alias->addr;
base -= mr->alias_offset;
- render_memory_region(view, mr->alias, base, clip);
+ render_memory_region(view, mr->alias, base, clip, readonly);
return;
}
/* Render subregions in priority order. */
QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
- render_memory_region(view, subregion, base, clip);
+ render_memory_region(view, subregion, base, clip, readonly);
}
if (!mr->terminates) {
@@ -536,6 +545,7 @@ static void render_memory_region(FlatView *view,
fr.addr = addrrange_make(base, now);
fr.dirty_log_mask = mr->dirty_log_mask;
fr.readable = mr->readable;
+ fr.readonly = readonly;
flatview_insert(view, i, &fr);
++i;
base += now;
@@ -555,6 +565,7 @@ static void render_memory_region(FlatView *view,
fr.addr = addrrange_make(base, remain);
fr.dirty_log_mask = mr->dirty_log_mask;
fr.readable = mr->readable;
+ fr.readonly = readonly;
flatview_insert(view, i, &fr);
}
}
@@ -566,7 +577,7 @@ static FlatView generate_memory_topology(MemoryRegion *mr)
flatview_init(&view);
- render_memory_region(&view, mr, 0, addrrange_make(0, INT64_MAX));
+ render_memory_region(&view, mr, 0, addrrange_make(0, INT64_MAX), false);
flatview_simplify(&view);
return view;
@@ -772,6 +783,7 @@ void memory_region_init(MemoryRegion *mr,
mr->offset = 0;
mr->terminates = false;
mr->readable = true;
+ mr->readonly = false;
mr->destructor = memory_region_destructor_none;
mr->priority = 0;
mr->may_overlap = false;
@@ -1035,7 +1047,10 @@ void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
{
- /* FIXME */
+ if (mr->readonly != readonly) {
+ mr->readonly = readonly;
+ memory_region_update_topology();
+ }
}
void memory_region_rom_device_set_readable(MemoryRegion *mr, bool readable)
diff --git a/memory.h b/memory.h
index 06b83ae76b..e93e65a4f2 100644
--- a/memory.h
+++ b/memory.h
@@ -114,6 +114,7 @@ struct MemoryRegion {
IORange iorange;
bool terminates;
bool readable;
+ bool readonly; /* For RAM regions */
MemoryRegion *alias;
target_phys_addr_t alias_offset;
unsigned priority;
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-25 15:14:21 +0200