diff options
63 files changed, 1078 insertions, 479 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 01cfb05b76..7fc3cdb1d6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -98,8 +98,12 @@ LM32 M: Michael Walle <michael@walle.cc> S: Maintained F: target-lm32/ +F: disas/lm32.c F: hw/lm32/ -F: hw/char/lm32_* +F: hw/*/lm32_* +F: hw/*/milkymist-* +F: include/hw/char/lm32_juart.h +F: include/hw/lm32/ F: tests/tcg/lm32/ M68K diff --git a/arch_init.c b/arch_init.c index 7680d28be4..cfedbf08af 100644 --- a/arch_init.c +++ b/arch_init.c @@ -522,7 +522,7 @@ static void migration_bitmap_sync(void) address_space_sync_dirty_bitmap(&address_space_memory); QTAILQ_FOREACH(block, &ram_list.blocks, next) { - migration_bitmap_sync_range(block->mr->ram_addr, block->length); + migration_bitmap_sync_range(block->mr->ram_addr, block->used_length); } trace_migration_bitmap_sync_end(migration_dirty_pages - num_dirty_pages_init); @@ -668,7 +668,7 @@ static int ram_find_and_save_block(QEMUFile *f, bool last_stage) offset >= last_offset) { break; } - if (offset >= block->length) { + if (offset >= block->used_length) { offset = 0; block = QTAILQ_NEXT(block, next); if (!block) { @@ -727,7 +727,7 @@ uint64_t ram_bytes_total(void) uint64_t total = 0; QTAILQ_FOREACH(block, &ram_list.blocks, next) - total += block->length; + total += block->used_length; return total; } @@ -831,7 +831,7 @@ static int ram_save_setup(QEMUFile *f, void *opaque) QTAILQ_FOREACH(block, &ram_list.blocks, next) { uint64_t block_pages; - block_pages = block->length >> TARGET_PAGE_BITS; + block_pages = block->used_length >> TARGET_PAGE_BITS; migration_dirty_pages += block_pages; } @@ -844,7 +844,7 @@ static int ram_save_setup(QEMUFile *f, void *opaque) QTAILQ_FOREACH(block, &ram_list.blocks, next) { qemu_put_byte(f, strlen(block->idstr)); qemu_put_buffer(f, (uint8_t *)block->idstr, strlen(block->idstr)); - qemu_put_be64(f, block->length); + qemu_put_be64(f, block->used_length); } qemu_mutex_unlock_ramlist(); @@ -1015,7 +1015,7 @@ static inline void *host_from_stream_offset(QEMUFile *f, uint8_t len; if (flags & RAM_SAVE_FLAG_CONTINUE) { - if (!block || block->length <= offset) { + if (!block || block->max_length <= offset) { error_report("Ack, bad migration stream!"); return NULL; } @@ -1028,7 +1028,8 @@ static inline void *host_from_stream_offset(QEMUFile *f, id[len] = 0; QTAILQ_FOREACH(block, &ram_list.blocks, next) { - if (!strncmp(id, block->idstr, sizeof(id)) && block->length > offset) { + if (!strncmp(id, block->idstr, sizeof(id)) && + block->max_length > offset) { return memory_region_get_ram_ptr(block->mr) + offset; } } @@ -1085,11 +1086,14 @@ static int ram_load(QEMUFile *f, void *opaque, int version_id) QTAILQ_FOREACH(block, &ram_list.blocks, next) { if (!strncmp(id, block->idstr, sizeof(id))) { - if (block->length != length) { - error_report("Length mismatch: %s: 0x" RAM_ADDR_FMT - " in != 0x" RAM_ADDR_FMT, id, length, - block->length); - ret = -EINVAL; + if (length != block->used_length) { + Error *local_err = NULL; + + ret = qemu_ram_resize(block->offset, length, &local_err); + if (local_err) { + error_report("%s", error_get_pretty(local_err)); + error_free(local_err); + } } break; } diff --git a/block/iscsi.c b/block/iscsi.c index ed375fc30e..12ddbfb095 100644 --- a/block/iscsi.c +++ b/block/iscsi.c @@ -1286,7 +1286,7 @@ static int iscsi_open(BlockDriverState *bs, QDict *options, int flags, QemuOpts *opts; Error *local_err = NULL; const char *filename; - int i, ret; + int i, ret = 0; if ((BDRV_SECTOR_SIZE % 512) != 0) { error_setg(errp, "iSCSI: Invalid BDRV_SECTOR_SIZE. " @@ -1830,7 +1830,7 @@ if test "$seccomp" != "no" ; then seccomp="yes" else if test "$seccomp" = "yes"; then - feature_not_found "libseccomp" "Install libseccomp devel >= 2.1.0" + feature_not_found "libseccomp" "Install libseccomp devel >= 2.1.1" fi seccomp="no" fi diff --git a/device_tree.c b/device_tree.c index df9eed9cbc..4cb1cd50aa 100644 --- a/device_tree.c +++ b/device_tree.c @@ -324,6 +324,7 @@ int qemu_fdt_setprop_sized_cells_from_array(void *fdt, uint64_t value; int cellnum, vnum, ncells; uint32_t hival; + int ret; propcells = g_new0(uint32_t, numvalues * 2); @@ -331,18 +332,23 @@ int qemu_fdt_setprop_sized_cells_from_array(void *fdt, for (vnum = 0; vnum < numvalues; vnum++) { ncells = values[vnum * 2]; if (ncells != 1 && ncells != 2) { - return -1; + ret = -1; + goto out; } value = values[vnum * 2 + 1]; hival = cpu_to_be32(value >> 32); if (ncells > 1) { propcells[cellnum++] = hival; } else if (hival != 0) { - return -1; + ret = -1; + goto out; } propcells[cellnum++] = cpu_to_be32(value); } - return qemu_fdt_setprop(fdt, node_path, property, propcells, - cellnum * sizeof(uint32_t)); + ret = qemu_fdt_setprop(fdt, node_path, property, propcells, + cellnum * sizeof(uint32_t)); +out: + g_free(propcells); + return ret; } diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt index 9b57d5e8fe..c6732fe003 100644 --- a/docs/specs/pci-ids.txt +++ b/docs/specs/pci-ids.txt @@ -45,7 +45,7 @@ PCI devices (other than virtio): 1b36:0003 PCI Dual-port 16550A adapter (docs/specs/pci-serial.txt) 1b36:0004 PCI Quad-port 16550A adapter (docs/specs/pci-serial.txt) 1b36:0005 PCI test device (docs/specs/pci-testdev.txt) -1b36:0006 PCI SD Card Host Controller Interface (SDHCI) +1b36:0007 PCI SD Card Host Controller Interface (SDHCI) All these devices are documented in docs/specs. @@ -75,6 +75,11 @@ static MemoryRegion io_mem_unassigned; /* RAM is mmap-ed with MAP_SHARED */ #define RAM_SHARED (1 << 1) +/* Only a portion of RAM (used_length) is actually used, and migrated. + * This used_length size can change across reboots. + */ +#define RAM_RESIZEABLE (1 << 2) + #endif struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); @@ -812,11 +817,11 @@ static RAMBlock *qemu_get_ram_block(ram_addr_t addr) /* The list is protected by the iothread lock here. */ block = ram_list.mru_block; - if (block && addr - block->offset < block->length) { + if (block && addr - block->offset < block->max_length) { goto found; } QTAILQ_FOREACH(block, &ram_list.blocks, next) { - if (addr - block->offset < block->length) { + if (addr - block->offset < block->max_length) { goto found; } } @@ -850,7 +855,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t length, { if (length == 0) return; - cpu_physical_memory_clear_dirty_range(start, length, client); + cpu_physical_memory_clear_dirty_range_type(start, length, client); if (tcg_enabled()) { tlb_reset_dirty_range_all(start, length); @@ -1186,7 +1191,7 @@ static ram_addr_t find_ram_offset(ram_addr_t size) QTAILQ_FOREACH(block, &ram_list.blocks, next) { ram_addr_t end, next = RAM_ADDR_MAX; - end = block->offset + block->length; + end = block->offset + block->max_length; QTAILQ_FOREACH(next_block, &ram_list.blocks, next) { if (next_block->offset >= end) { @@ -1214,7 +1219,7 @@ ram_addr_t last_ram_offset(void) ram_addr_t last = 0; QTAILQ_FOREACH(block, &ram_list.blocks, next) - last = MAX(last, block->offset + block->length); + last = MAX(last, block->offset + block->max_length); return last; } @@ -1296,6 +1301,49 @@ static int memory_try_enable_merging(void *addr, size_t len) return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); } +/* Only legal before guest might have detected the memory size: e.g. on + * incoming migration, or right after reset. + * + * As memory core doesn't know how is memory accessed, it is up to + * resize callback to update device state and/or add assertions to detect + * misuse, if necessary. + */ +int qemu_ram_resize(ram_addr_t base, ram_addr_t newsize, Error **errp) +{ + RAMBlock *block = find_ram_block(base); + + assert(block); + + if (block->used_length == newsize) { + return 0; + } + + if (!(block->flags & RAM_RESIZEABLE)) { + error_setg_errno(errp, EINVAL, + "Length mismatch: %s: 0x" RAM_ADDR_FMT + " in != 0x" RAM_ADDR_FMT, block->idstr, + newsize, block->used_length); + return -EINVAL; + } + + if (block->max_length < newsize) { + error_setg_errno(errp, EINVAL, + "Length too large: %s: 0x" RAM_ADDR_FMT + " > 0x" RAM_ADDR_FMT, block->idstr, + newsize, block->max_length); + return -EINVAL; + } + + cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); + block->used_length = newsize; + cpu_physical_memory_set_dirty_range(block->offset, block->used_length); + memory_region_set_size(block->mr, newsize); + if (block->resized) { + block->resized(block->idstr, newsize, block->host); + } + return 0; +} + static ram_addr_t ram_block_add(RAMBlock *new_block, Error **errp) { RAMBlock *block; @@ -1305,13 +1353,14 @@ static ram_addr_t ram_block_add(RAMBlock *new_block, Error **errp) /* This assumes the iothread lock is taken here too. */ qemu_mutex_lock_ramlist(); - new_block->offset = find_ram_offset(new_block->length); + new_block->offset = find_ram_offset(new_block->max_length); if (!new_block->host) { if (xen_enabled()) { - xen_ram_alloc(new_block->offset, new_block->length, new_block->mr); + xen_ram_alloc(new_block->offset, new_block->max_length, + new_block->mr); } else { - new_block->host = phys_mem_alloc(new_block->length, + new_block->host = phys_mem_alloc(new_block->max_length, &new_block->mr->align); if (!new_block->host) { error_setg_errno(errp, errno, @@ -1320,13 +1369,13 @@ static ram_addr_t ram_block_add(RAMBlock *new_block, Error **errp) qemu_mutex_unlock_ramlist(); return -1; } - memory_try_enable_merging(new_block->host, new_block->length); + memory_try_enable_merging(new_block->host, new_block->max_length); } } /* Keep the list sorted from biggest to smallest block. */ QTAILQ_FOREACH(block, &ram_list.blocks, next) { - if (block->length < new_block->length) { + if (block->max_length < new_block->max_length) { break; } } @@ -1350,14 +1399,15 @@ static ram_addr_t ram_block_add(RAMBlock *new_block, Error **errp) old_ram_size, new_ram_size); } } - cpu_physical_memory_set_dirty_range(new_block->offset, new_block->length); + cpu_physical_memory_set_dirty_range(new_block->offset, + new_block->used_length); - qemu_ram_setup_dump(new_block->host, new_block->length); - qemu_madvise(new_block->host, new_block->length, QEMU_MADV_HUGEPAGE); - qemu_madvise(new_block->host, new_block->length, QEMU_MADV_DONTFORK); + qemu_ram_setup_dump(new_block->host, new_block->max_length); + qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); + qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); if (kvm_enabled()) { - kvm_setup_guest_memory(new_block->host, new_block->length); + kvm_setup_guest_memory(new_block->host, new_block->max_length); } return new_block->offset; @@ -1391,7 +1441,8 @@ ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, size = TARGET_PAGE_ALIGN(size); new_block = g_malloc0(sizeof(*new_block)); new_block->mr = mr; - new_block->length = size; + new_block->used_length = size; + new_block->max_length = size; new_block->flags = share ? RAM_SHARED : 0; new_block->host = file_ram_alloc(new_block, size, mem_path, errp); @@ -1410,7 +1461,12 @@ ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, } #endif -ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, +static +ram_addr_t qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, + void (*resized)(const char*, + uint64_t length, + void *host), + void *host, bool resizeable, MemoryRegion *mr, Error **errp) { RAMBlock *new_block; @@ -1418,14 +1474,21 @@ ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, Error *local_err = NULL; size = TARGET_PAGE_ALIGN(size); + max_size = TARGET_PAGE_ALIGN(max_size); new_block = g_malloc0(sizeof(*new_block)); new_block->mr = mr; - new_block->length = size; + new_block->resized = resized; + new_block->used_length = size; + new_block->max_length = max_size; + assert(max_size >= size); new_block->fd = -1; new_block->host = host; if (host) { new_block->flags |= RAM_PREALLOC; } + if (resizeable) { + new_block->flags |= RAM_RESIZEABLE; + } addr = ram_block_add(new_block, &local_err); if (local_err) { g_free(new_block); @@ -1435,9 +1498,24 @@ ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, return addr; } +ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, + MemoryRegion *mr, Error **errp) +{ + return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp); +} + ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp) { - return qemu_ram_alloc_from_ptr(size, NULL, mr, errp); + return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp); +} + +ram_addr_t qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, + void (*resized)(const char*, + uint64_t length, + void *host), + MemoryRegion *mr, Error **errp) +{ + return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp); } void qemu_ram_free_from_ptr(ram_addr_t addr) @@ -1475,11 +1553,11 @@ void qemu_ram_free(ram_addr_t addr) xen_invalidate_map_cache_entry(block->host); #ifndef _WIN32 } else if (block->fd >= 0) { - munmap(block->host, block->length); + munmap(block->host, block->max_length); close(block->fd); #endif } else { - qemu_anon_ram_free(block->host, block->length); + qemu_anon_ram_free(block->host, block->max_length); } g_free(block); break; @@ -1499,7 +1577,7 @@ void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) QTAILQ_FOREACH(block, &ram_list.blocks, next) { offset = addr - block->offset; - if (offset < block->length) { + if (offset < block->max_length) { vaddr = ramblock_ptr(block, offset); if (block->flags & RAM_PREALLOC) { ; @@ -1575,7 +1653,7 @@ void *qemu_get_ram_ptr(ram_addr_t addr) return xen_map_cache(addr, 0, 0); } else if (block->host == NULL) { block->host = - xen_map_cache(block->offset, block->length, 1); + xen_map_cache(block->offset, block->max_length, 1); } } return ramblock_ptr(block, addr - block->offset); @@ -1594,9 +1672,9 @@ static void *qemu_ram_ptr_length(ram_addr_t addr, hwaddr *size) RAMBlock *block; QTAILQ_FOREACH(block, &ram_list.blocks, next) { - if (addr - block->offset < block->length) { - if (addr - block->offset + *size > block->length) - *size = block->length - addr + block->offset; + if (addr - block->offset < block->max_length) { + if (addr - block->offset + *size > block->max_length) + *size = block->max_length - addr + block->offset; return ramblock_ptr(block, addr - block->offset); } } @@ -1619,7 +1697,7 @@ MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) } block = ram_list.mru_block; - if (block && block->host && host - block->host < block->length) { + if (block && block->host && host - block->host < block->max_length) { goto found; } @@ -1628,7 +1706,7 @@ MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) if (block->host == NULL) { continue; } - if (host - block->host < block->length) { + if (host - block->host < block->max_length) { goto found; } } @@ -2882,7 +2960,7 @@ void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) RAMBlock *block; QTAILQ_FOREACH(block, &ram_list.blocks, next) { - func(block->host, block->offset, block->length, opaque); + func(block->host, block->offset, block->used_length, opaque); } } #endif diff --git a/hw/char/serial.c b/hw/char/serial.c index 6d522ff4f3..3aca87416d 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -645,8 +645,17 @@ static int serial_post_load(void *opaque, int version_id) static bool serial_thr_ipending_needed(void *opaque) { SerialState *s = opaque; - bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); - return s->thr_ipending != expected_value; + + if (s->ier & UART_IER_THRI) { + bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); + return s->thr_ipending != expected_value; + } else { + /* LSR.THRE will be sampled again when the interrupt is + * enabled. thr_ipending is not used in this case, do + * not migrate it. + */ + return false; + } } const VMStateDescription vmstate_serial_thr_ipending = { diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index a7b1b68984..37a6f442fa 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -482,10 +482,14 @@ static uint32_t get_features(VirtIODevice *vdev, uint32_t features) /* Guest requested config info */ static void get_config(VirtIODevice *vdev, uint8_t *config_data) { - VirtIOSerial *vser; - - vser = VIRTIO_SERIAL(vdev); - memcpy(config_data, &vser->config, sizeof(struct virtio_console_config)); + VirtIOSerial *vser = VIRTIO_SERIAL(vdev); + struct virtio_console_config *config = + (struct virtio_console_config *)config_data; + + config->cols = 0; + config->rows = 0; + config->max_nr_ports = virtio_tswap32(vdev, + vser->serial.max_virtserial_ports); } static void guest_reset(VirtIOSerial *vser) @@ -533,10 +537,6 @@ static void vser_reset(VirtIODevice *vdev) vser = VIRTIO_SERIAL(vdev); guest_reset(vser); - - /* In case we have switched endianness */ - vser->config.max_nr_ports = - virtio_tswap32(vdev, vser->serial.max_virtserial_ports); } static void virtio_serial_save(QEMUFile *f, void *opaque) @@ -551,15 +551,16 @@ static void virtio_serial_save_device(VirtIODevice *vdev, QEMUFile *f) VirtIOSerialPort *port; uint32_t nr_active_ports; unsigned int i, max_nr_ports; + struct virtio_console_config config; - /* The config space */ - qemu_put_be16s(f, &s->config.cols); - qemu_put_be16s(f, &s->config.rows); - - qemu_put_be32s(f, &s->config.max_nr_ports); + /* The config space (ignored on the far end in current versions) */ + get_config(vdev, (uint8_t *)&config); + qemu_put_be16s(f, &config.cols); + qemu_put_be16s(f, &config.rows); + qemu_put_be32s(f, &config.max_nr_ports); /* The ports map */ - max_nr_ports = virtio_tswap32(vdev, s->config.max_nr_ports); + max_nr_ports = s->serial.max_virtserial_ports; for (i = 0; i < (max_nr_ports + 31) / 32; i++) { qemu_put_be32s(f, &s->ports_map[i]); } @@ -715,13 +716,7 @@ static int virtio_serial_load_device(VirtIODevice *vdev, QEMUFile *f, qemu_get_be16s(f, (uint16_t *) &tmp); qemu_get_be32s(f, &tmp); - /* Note: this is the only location where we use tswap32() instead of - * virtio_tswap32() because: - * - virtio_tswap32() only makes sense when the device is fully restored - * - the target endianness that was used to populate s->config is - * necessarly the default one - */ - max_nr_ports = tswap32(s->config.max_nr_ports); + max_nr_ports = s->serial.max_virtserial_ports; for (i = 0; i < (max_nr_ports + 31) / 32; i++) { qemu_get_be32s(f, &ports_map); @@ -784,10 +779,9 @@ static void virtser_bus_dev_print(Monitor *mon, DeviceState *qdev, int indent) /* This function is only used if a port id is not provided by the user */ static uint32_t find_free_port_id(VirtIOSerial *vser) { - VirtIODevice *vdev = VIRTIO_DEVICE(vser); unsigned int i, max_nr_ports; - max_nr_ports = virtio_tswap32(vdev, vser->config.max_nr_ports); + max_nr_ports = vser->serial.max_virtserial_ports; for (i = 0; i < (max_nr_ports + 31) / 32; i++) { uint32_t map, bit; @@ -848,7 +842,6 @@ static void virtser_port_device_realize(DeviceState *dev, Error **errp) VirtIOSerialPort *port = VIRTIO_SERIAL_PORT(dev); VirtIOSerialPortClass *vsc = VIRTIO_SERIAL_PORT_GET_CLASS(port); VirtIOSerialBus *bus = VIRTIO_SERIAL_BUS(qdev_get_parent_bus(dev)); - VirtIODevice *vdev = VIRTIO_DEVICE(bus->vser); int max_nr_ports; bool plugging_port0; Error *err = NULL; @@ -890,7 +883,7 @@ static void virtser_port_device_realize(DeviceState *dev, Error **errp) } } - max_nr_ports = virtio_tswap32(vdev, port->vser->config.max_nr_ports); + max_nr_ports = port->vser->serial.max_virtserial_ports; if (port->id >= max_nr_ports) { error_setg(errp, "virtio-serial-bus: Out-of-range port id specified, " "max. allowed: %u", max_nr_ports - 1); @@ -995,8 +988,6 @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp) vser->ovqs[i] = virtio_add_queue(vdev, 128, handle_output); } - vser->config.max_nr_ports = - virtio_tswap32(vdev, vser->serial.max_virtserial_ports); vser->ports_map = g_malloc0(((vser->serial.max_virtserial_ports + 31) / 32) * sizeof(vser->ports_map[0])); /* diff --git a/hw/core/loader.c b/hw/core/loader.c index f2b34da240..fcd4705d78 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -724,12 +724,22 @@ static void rom_insert(Rom *rom) QTAILQ_INSERT_TAIL(&roms, rom, next); } +static void fw_cfg_resized(const char *id, uint64_t length, void *host) +{ + if (fw_cfg) { + fw_cfg_modify_file(fw_cfg, id + strlen("/rom@"), host, length); + } +} + static void *rom_set_mr(Rom *rom, Object *owner, const char *name) { void *data; rom->mr = g_malloc(sizeof(*rom->mr)); - memory_region_init_ram(rom->mr, owner, name, rom->datasize, &error_abort); + memory_region_init_resizeable_ram(rom->mr, owner, name, + rom->datasize, rom->romsize, + fw_cfg_resized, + &error_abort); memory_region_set_readonly(rom->mr, true); vmstate_register_ram_global(rom->mr); @@ -824,7 +834,7 @@ err: } ram_addr_t rom_add_blob(const char *name, const void *blob, size_t len, - hwaddr addr, const char *fw_file_name, + size_t max_len, hwaddr addr, const char *fw_file_name, FWCfgReadCallback fw_callback, void *callback_opaque) { Rom *rom; @@ -833,7 +843,7 @@ ram_addr_t rom_add_blob(const char *name, const void *blob, size_t len, rom = g_malloc0(sizeof(*rom)); rom->name = g_strdup(name); rom->addr = addr; - rom->romsize = len; + rom->romsize = max_len ? max_len : len; rom->datasize = len; rom->data = g_malloc0(rom->datasize); memcpy(rom->data, blob, len); @@ -853,7 +863,7 @@ ram_addr_t rom_add_blob(const char *name, const void *blob, size_t len, fw_cfg_add_file_callback(fw_cfg, fw_file_name, fw_callback, callback_opaque, - data, rom->romsize); + data, rom->datasize); } return ret; } diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index a4d0c0c8bf..6a2e9c52bc 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -68,6 +68,9 @@ #define ACPI_BUILD_TABLE_SIZE 0x20000 +/* Reserve RAM space for tables: add another order of magnitude. */ +#define ACPI_BUILD_TABLE_MAX_SIZE 0x200000 + /* #define DEBUG_ACPI_BUILD */ #ifdef DEBUG_ACPI_BUILD #define ACPI_BUILD_DPRINTF(fmt, ...) \ @@ -1718,6 +1721,11 @@ static void acpi_build_update(void *build_opaque, uint32_t offset) acpi_build(build_state->guest_info, &tables); assert(acpi_data_len(tables.table_data) == build_state->table_size); + + /* Make sure RAM size is correct - in case it got changed by migration */ + qemu_ram_resize(build_state->table_ram, build_state->table_size, + &error_abort); + memcpy(qemu_get_ram_ptr(build_state->table_ram), tables.table_data->data, build_state->table_size); @@ -1734,10 +1742,10 @@ static void acpi_build_reset(void *build_opaque) } static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob, - const char *name) + const char *name, uint64_t max_size) { - return rom_add_blob(name, blob->data, acpi_data_len(blob), -1, name, - acpi_build_update, build_state); + return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, + name, acpi_build_update, build_state); } static const VMStateDescription vmstate_acpi_build = { @@ -1781,11 +1789,12 @@ void acpi_setup(PcGuestInfo *guest_info) /* Now expose it all to Guest */ build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data, - ACPI_BUILD_TABLE_FILE); + ACPI_BUILD_TABLE_FILE, + ACPI_BUILD_TABLE_MAX_SIZE); assert(build_state->table_ram != RAM_ADDR_MAX); build_state->table_size = acpi_data_len(tables.table_data); - acpi_add_rom_blob(NULL, tables.linker, "etc/table-loader"); + acpi_add_rom_blob(NULL, tables.linker, "etc/table-loader", 0); fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); diff --git a/hw/input/milkymist-softusb.c b/hw/input/milkymist-softusb.c index 5a427f0b33..7b0f4db88d 100644 --- a/hw/input/milkymist-softusb.c +++ b/hw/input/milkymist-softusb.c @@ -194,10 +194,13 @@ static void softusb_kbd_hid_datain(HIDState *hs) return; } - len = hid_keyboard_poll(hs, s->kbd_hid_buffer, sizeof(s->kbd_hid_buffer)); + while (hid_has_events(hs)) { + len = hid_keyboard_poll(hs, s->kbd_hid_buffer, + sizeof(s->kbd_hid_buffer)); - if (len == 8) { - softusb_kbd_changed(s); + if (len == 8) { + softusb_kbd_changed(s); + } } } @@ -212,11 +215,13 @@ static void softusb_mouse_hid_datain(HIDState *hs) return; } - len = hid_pointer_poll(hs, s->mouse_hid_buffer, - sizeof(s->mouse_hid_buffer)); + while (hid_has_events(hs)) { + len = hid_pointer_poll(hs, s->mouse_hid_buffer, + sizeof(s->mouse_hid_buffer)); - if (len == 4) { - softusb_mouse_changed(s); + if (len == 4) { + softusb_mouse_changed(s); + } } } diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 2b0cd3dbb8..9b9a7d7a8a 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -101,6 +101,12 @@ #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */ #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */ +/* OSes typically write 0xdd/0xdf to turn the A20 line off and on. + * We make the default value of the outport include these four bits, + * so that the subsection is rarely necessary. + */ +#define KBD_OUT_ONES 0xcc + /* Mouse Commands */ #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ @@ -367,13 +373,13 @@ static void kbd_reset(void *opaque) s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; - s->outport = KBD_OUT_RESET | KBD_OUT_A20; + s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES; s->outport_present = false; } static uint8_t kbd_outport_default(KBDState *s) { - return KBD_OUT_RESET | KBD_OUT_A20 + return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0) | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0); } diff --git a/hw/lm32/lm32_hwsetup.h b/hw/lm32/lm32_hwsetup.h index 9fd5e697a7..838754d5d8 100644 --- a/hw/lm32/lm32_hwsetup.h +++ b/hw/lm32/lm32_hwsetup.h @@ -73,7 +73,8 @@ static inline void hwsetup_free(HWSetup *hw) static inline void hwsetup_create_rom(HWSetup *hw, hwaddr base) { - rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base, NULL, NULL, NULL); + rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, + TARGET_PAGE_SIZE, base, NULL, NULL, NULL); } static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 1b4c0f0023..574f8b2efb 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -62,11 +62,19 @@ #define PPCE500_PCI_NR_POBS 5 #define PPCE500_PCI_NR_PIBS 3 +#define PIWAR_EN 0x80000000 /* Enable */ +#define PIWAR_PF 0x20000000 /* prefetch */ +#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_SZ_MASK 0x0000003f + struct pci_outbound { uint32_t potar; uint32_t potear; uint32_t powbar; uint32_t powar; + MemoryRegion mem; }; struct pci_inbound { @@ -74,6 +82,7 @@ struct pci_inbound { uint32_t piwbar; uint32_t piwbear; uint32_t piwar; + MemoryRegion mem; }; #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" @@ -91,10 +100,13 @@ struct PPCE500PCIState { uint32_t irq_num[PCI_NUM_PINS]; uint32_t first_slot; uint32_t first_pin_irq; + AddressSpace bm_as; + MemoryRegion bm; /* mmio maps */ MemoryRegion container; MemoryRegion iomem; MemoryRegion pio; + MemoryRegion busmem; }; #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" @@ -181,6 +193,71 @@ static uint64_t pci_reg_read4(void *opaque, hwaddr addr, return value; } +/* DMA mapping */ +static void e500_update_piw(PPCE500PCIState *pci, int idx) +{ + uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; + uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; + uint64_t war = pci->pib[idx].piwar; + uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); + MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *mem = &pci->pib[idx].mem; + MemoryRegion *bm = &pci->bm; + char *name; + + if (memory_region_is_mapped(mem)) { + /* Before we modify anything, unmap and destroy the region */ + memory_region_del_subregion(bm, mem); + object_unparent(OBJECT(mem)); + } + + if (!(war & PIWAR_EN)) { + /* Not enabled, nothing to do */ + return; + } + + name = g_strdup_printf("PCI Inbound Window %d", idx); + memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, + size); + memory_region_add_subregion_overlap(bm, wbar, mem, -1); + g_free(name); + + pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n", + __func__, size, wbar, tar); +} + +/* BAR mapping */ +static void e500_update_pow(PPCE500PCIState *pci, int idx) +{ + uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; + uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; + uint64_t war = pci->pob[idx].powar; + uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); + MemoryRegion *mem = &pci->pob[idx].mem; + MemoryRegion *address_space_mem = get_system_memory(); + char *name; + + if (memory_region_is_mapped(mem)) { + /* Before we modify anything, unmap and destroy the region */ + memory_region_del_subregion(address_space_mem, mem); + object_unparent(OBJECT(mem)); + } + + if (!(war & PIWAR_EN)) { + /* Not enabled, nothing to do */ + return; + } + + name = g_strdup_printf("PCI Outbound Window %d", idx); + memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, + size); + memory_region_add_subregion(address_space_mem, wbar, mem); + g_free(name); + + pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n", + __func__, size, wbar, tar); +} + static void pci_reg_write4(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -199,18 +276,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr, case PPCE500_PCI_OW3: case PPCE500_PCI_OW4: idx = (addr >> 5) & 0x7; - switch (addr & 0xC) { + switch (addr & 0x1F) { case PCI_POTAR: pci->pob[idx].potar = value; + e500_update_pow(pci, idx); break; case PCI_POTEAR: pci->pob[idx].potear = value; + e500_update_pow(pci, idx); break; case PCI_POWBAR: pci->pob[idx].powbar = value; + e500_update_pow(pci, idx); break; case PCI_POWAR: pci->pob[idx].powar = value; + e500_update_pow(pci, idx); break; default: break; @@ -221,18 +302,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr, case PPCE500_PCI_IW2: case PPCE500_PCI_IW1: idx = ((addr >> 5) & 0x3) - 1; - switch (addr & 0xC) { + switch (addr & 0x1F) { case PCI_PITAR: pci->pib[idx].pitar = value; + e500_update_piw(pci, idx); break; case PCI_PIWBAR: pci->pib[idx].piwbar = value; + e500_update_piw(pci, idx); break; case PCI_PIWBEAR: pci->pib[idx].piwbear = value; + e500_update_piw(pci, idx); break; case PCI_PIWAR: pci->pib[idx].piwar = value; + e500_update_piw(pci, idx); break; default: break; @@ -349,13 +434,20 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d) return 0; } +static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque, + int devfn) +{ + PPCE500PCIState *s = opaque; + + return &s->bm_as; +} + static int e500_pcihost_initfn(SysBusDevice *dev) { PCIHostState *h; PPCE500PCIState *s; PCIBus *b; int i; - MemoryRegion *address_space_mem = get_system_memory(); h = PCI_HOST_BRIDGE(dev); s = PPC_E500_PCI_HOST_BRIDGE(dev); @@ -369,12 +461,22 @@ static int e500_pcihost_initfn(SysBusDevice *dev) } memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); + memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); + + /* PIO lives at the bottom of our bus space */ + memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2); b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq, - mpc85xx_pci_map_irq, s, address_space_mem, - &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); + mpc85xx_pci_map_irq, s, &s->busmem, &s->pio, + PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); h->bus = b; + /* Set up PCI view of memory */ + memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX); + memory_region_add_subregion(&s->bm, 0x0, &s->busmem); + address_space_init(&s->bm_as, &s->bm, "pci-bm"); + pci_setup_iommu(b, e500_pcihost_set_iommu, s); + pci_create_simple(b, 0, "e500-host-bridge"); memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); @@ -388,7 +490,6 @@ static int e500_pcihost_initfn(SysBusDevice *dev) memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); sysbus_init_mmio(dev, &s->container); - sysbus_init_mmio(dev, &s->pio); pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); return 0; diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 2832fc0da4..7e17d180c6 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -51,21 +51,16 @@ #define RAM_SIZES_ALIGN (64UL << 20) /* TODO: parameterize */ -#define MPC8544_CCSRBAR_BASE 0xE0000000ULL #define MPC8544_CCSRBAR_SIZE 0x00100000ULL #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL #define MPC8544_MSI_REGS_OFFSET 0x41600ULL #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL #define MPC8544_PCI_REGS_OFFSET 0x8000ULL -#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ - MPC8544_PCI_REGS_OFFSET) #define MPC8544_PCI_REGS_SIZE 0x1000ULL -#define MPC8544_PCI_IO 0xE1000000ULL #define MPC8544_UTIL_OFFSET 0xe0000ULL -#define MPC8544_SPIN_BASE 0xEF000000ULL #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL -#define MPC8XXX_GPIO_IRQ 43 +#define MPC8XXX_GPIO_IRQ 47 struct boot_info { @@ -293,12 +288,12 @@ static int ppce500_load_device_tree(MachineState *machine, int len; uint32_t pci_ranges[14] = { - 0x2000000, 0x0, 0xc0000000, - 0x0, 0xc0000000, + 0x2000000, 0x0, params->pci_mmio_bus_base, + params->pci_mmio_base >> 32, params->pci_mmio_base, 0x0, 0x20000000, 0x1000000, 0x0, 0x0, - 0x0, 0xe1000000, + params->pci_pio_base >> 32, params->pci_pio_base, 0x0, 0x10000, }; QemuOpts *machine_opts = qemu_get_machine_opts(); @@ -389,7 +384,7 @@ static int ppce500_load_device_tree(MachineState *machine, CPUState *cpu; PowerPCCPU *pcpu; char cpu_name[128]; - uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); + uint64_t cpu_release_addr = params->spin_base + (i * 0x20); cpu = qemu_get_cpu(i); if (cpu == NULL) { @@ -426,7 +421,7 @@ static int ppce500_load_device_tree(MachineState *machine, qemu_fdt_add_subnode(fdt, "/aliases"); /* XXX These should go into their respective devices' code */ - snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); + snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base); qemu_fdt_add_subnode(fdt, soc); qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, @@ -434,7 +429,7 @@ static int ppce500_load_device_tree(MachineState *machine, qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, - MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, + params->ccsrbar_base >> 32, params->ccsrbar_base, MPC8544_CCSRBAR_SIZE); /* XXX should contain a reasonable value */ qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); @@ -493,7 +488,8 @@ static int ppce500_load_device_tree(MachineState *machine, qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); - snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); + snprintf(pci, sizeof(pci), "/pci@%llx", + params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); qemu_fdt_add_subnode(fdt, pci); qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); @@ -512,8 +508,10 @@ static int ppce500_load_device_tree(MachineState *machine, } qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); - qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, - MPC8544_PCI_REGS_BASE, 0, 0x1000); + qemu_fdt_setprop_cells(fdt, pci, "reg", + (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, + (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), + 0, 0x1000); qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); @@ -841,7 +839,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; - env->mpic_iack = MPC8544_CCSRBAR_BASE + + env->mpic_iack = params->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); @@ -875,7 +873,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) qdev_init_nofail(dev); ccsr = CCSR(dev); ccsr_addr_space = &ccsr->ccsr_space; - memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, + memory_region_add_subregion(address_space_mem, params->ccsrbar_base, ccsr_addr_space); mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); @@ -917,8 +915,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) if (!pci_bus) printf("couldn't create PCI controller!\n"); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO); - if (pci_bus) { /* Register network interfaces. */ for (i = 0; i < nb_nics; i++) { @@ -927,7 +923,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) } /* Register spinning region */ - sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); + sysbus_create_simple("e500-spin", params->spin_base, NULL); if (cur_base < (32 * 1024 * 1024)) { /* u-boot occupies memory up to 32MB, so load blobs above */ diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 9f61ab2b1c..ef224ea5e6 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -17,6 +17,11 @@ typedef struct PPCE500Params { hwaddr platform_bus_size; int platform_bus_first_irq; int platform_bus_num_irqs; + hwaddr ccsrbar_base; + hwaddr pci_pio_base; + hwaddr pci_mmio_base; + hwaddr pci_mmio_bus_base; + hwaddr spin_base; } PPCE500Params; void ppce500_init(MachineState *machine, PPCE500Params *params); diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index d50ae000ee..14b14eaa7d 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -41,6 +41,11 @@ static void e500plat_init(MachineState *machine) .platform_bus_size = (128ULL * 1024 * 1024), .platform_bus_first_irq = 5, .platform_bus_num_irqs = 10, + .ccsrbar_base = 0xFE0000000ULL, + .pci_pio_base = 0xFE1000000ULL, + .pci_mmio_base = 0xC00000000ULL, + .pci_mmio_bus_base = 0xE0000000ULL, + .spin_base = 0xFEF000000ULL, }; /* Older KVM versions don't support EPR which breaks guests when we announce diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index b99f74af75..3a3b141e43 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -15,6 +15,7 @@ #include "hw/boards.h" #include "sysemu/device_tree.h" #include "hw/ppc/openpic.h" +#include "qemu/error-report.h" static void mpc8544ds_fixup_devtree(PPCE500Params *params, void *fdt) { @@ -33,8 +34,18 @@ static void mpc8544ds_init(MachineState *machine) .pci_nr_slots = 2, .fixup_devtree = mpc8544ds_fixup_devtree, .mpic_version = OPENPIC_MODEL_FSL_MPIC_20, + .ccsrbar_base = 0xE0000000ULL, + .pci_mmio_base = 0xC0000000ULL, + .pci_mmio_bus_base = 0xC0000000ULL, + .pci_pio_base = 0xE1000000ULL, + .spin_base = 0xEF000000ULL, }; + if (machine->ram_size > 0xc0000000) { + error_report("The MPC8544DS board only supports up to 3GB of RAM"); + exit(1); + } + ppce500_init(machine, ¶ms); } diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index bec82cd7a9..5ce565d5ec 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -844,7 +844,7 @@ static void timebase_pre_save(void *opaque) return; } - tb->time_of_the_day_ns = get_clock_realtime(); + tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); /* * tb_offset is only expected to be changed by migration so * there is no need to update it from KVM here @@ -873,7 +873,7 @@ static int timebase_post_load(void *opaque, int version_id) * We try to adjust timebase by downtime if host clocks are not * too much out of sync (1 second for now). */ - host_ns = get_clock_realtime(); + host_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); ns_diff = MAX(0, host_ns - tb_remote->time_of_the_day_ns); migration_duration_ns = MIN(NSEC_PER_SEC, ns_diff); migration_duration_tb = muldiv64(migration_duration_ns, freq, NSEC_PER_SEC); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 53c4116ed3..b560459e83 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -819,9 +819,16 @@ static void emulate_spapr_hypercall(PowerPCCPU *cpu) } } +#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) +#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) +#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) +#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) +#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) + static void spapr_reset_htab(sPAPREnvironment *spapr) { long shift; + int index; /* allocate hash page table. For now we always make this 16mb, * later we should probably make it scale to the size of guest @@ -833,6 +840,11 @@ static void spapr_reset_htab(sPAPREnvironment *spapr) /* Kernel handles htab, we don't need to allocate one */ spapr->htab_shift = shift; kvmppc_kern_htab = true; + + /* Tell readers to update their file descriptor */ + if (spapr->htab_fd >= 0) { + spapr->htab_fd_stale = true; + } } else { if (!spapr->htab) { /* Allocate an htab if we don't yet have one */ @@ -841,6 +853,10 @@ static void spapr_reset_htab(sPAPREnvironment *spapr) /* And clear it */ memset(spapr->htab, 0, HTAB_SIZE(spapr)); + + for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { + DIRTY_HPTE(HPTE(spapr->htab, index)); + } } /* Update the RMA size if necessary */ @@ -867,6 +883,28 @@ static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) return 0; } +/* + * A guest reset will cause spapr->htab_fd to become stale if being used. + * Reopen the file descriptor to make sure the whole HTAB is properly read. + */ +static int spapr_check_htab_fd(sPAPREnvironment *spapr) +{ + int rc = 0; + + if (spapr->htab_fd_stale) { + close(spapr->htab_fd); + spapr->htab_fd = kvmppc_get_htab_fd(false); + if (spapr->htab_fd < 0) { + error_report("Unable to open fd for reading hash table from KVM: " + "%s", strerror(errno)); + rc = -1; + } + spapr->htab_fd_stale = false; + } + + return rc; +} + static void ppc_spapr_reset(void) { PowerPCCPU *first_ppc_cpu; @@ -986,11 +1024,6 @@ static const VMStateDescription vmstate_spapr = { }, }; -#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) -#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) -#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) -#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) - static int htab_save_setup(QEMUFile *f, void *opaque) { sPAPREnvironment *spapr = opaque; @@ -1005,6 +1038,7 @@ static int htab_save_setup(QEMUFile *f, void *opaque) assert(kvm_enabled()); spapr->htab_fd = kvmppc_get_htab_fd(false); + spapr->htab_fd_stale = false; if (spapr->htab_fd < 0) { fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", strerror(errno)); @@ -1037,7 +1071,7 @@ static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, /* Consume valid HPTEs */ chunkstart = index; - while ((index < htabslots) + while ((index < htabslots) && (index - chunkstart < USHRT_MAX) && HPTE_VALID(HPTE(spapr->htab, index))) { index++; CLEAN_HPTE(HPTE(spapr->htab, index)); @@ -1089,7 +1123,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, chunkstart = index; /* Consume valid dirty HPTEs */ - while ((index < htabslots) + while ((index < htabslots) && (index - chunkstart < USHRT_MAX) && HPTE_DIRTY(HPTE(spapr->htab, index)) && HPTE_VALID(HPTE(spapr->htab, index))) { CLEAN_HPTE(HPTE(spapr->htab, index)); @@ -1099,7 +1133,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, invalidstart = index; /* Consume invalid dirty HPTEs */ - while ((index < htabslots) + while ((index < htabslots) && (index - invalidstart < USHRT_MAX) && HPTE_DIRTY(HPTE(spapr->htab, index)) && !HPTE_VALID(HPTE(spapr->htab, index))) { CLEAN_HPTE(HPTE(spapr->htab, index)); @@ -1157,6 +1191,11 @@ static int htab_save_iterate(QEMUFile *f, void *opaque) if (!spapr->htab) { assert(kvm_enabled()); + rc = spapr_check_htab_fd(spapr); + if (rc < 0) { + return rc; + } + rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); if (rc < 0) { @@ -1188,6 +1227,11 @@ static int htab_save_complete(QEMUFile *f, void *opaque) assert(kvm_enabled()); + rc = spapr_check_htab_fd(spapr); + if (rc < 0) { + return rc; + } + rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); if (rc < 0) { return rc; @@ -1438,7 +1482,7 @@ static void ppc_spapr_init(MachineState *machine) } if (spapr->rtas_size > RTAS_MAX_SIZE) { hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", - spapr->rtas_size, RTAS_MAX_SIZE); + (size_t)spapr->rtas_size, RTAS_MAX_SIZE); exit(1); } g_free(filename); diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 6c91d8edd8..da474740c0 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -173,9 +173,9 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, return tcet; } -static void spapr_tce_table_finalize(Object *obj) +static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) { - sPAPRTCETable *tcet = SPAPR_TCE_TABLE(obj); + sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); QLIST_REMOVE(tcet, list); @@ -420,6 +420,7 @@ static void spapr_tce_table_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->init = spapr_tce_table_realize; dc->reset = spapr_tce_reset; + dc->unrealize = spapr_tce_table_unrealize; QLIST_INIT(&spapr_tce_tables); @@ -435,7 +436,6 @@ static TypeInfo spapr_tce_table_info = { .parent = TYPE_DEVICE, .instance_size = sizeof(sPAPRTCETable), .class_init = spapr_tce_table_class_init, - .instance_finalize = spapr_tce_table_finalize, }; static void register_types(void) diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c index 473c04410e..06e71782b2 100644 --- a/hw/virtio/virtio-rng.c +++ b/hw/virtio/virtio-rng.c @@ -149,7 +149,7 @@ static void virtio_rng_device_realize(DeviceState *dev, Error **errp) VirtIORNG *vrng = VIRTIO_RNG(dev); Error *local_err = NULL; - if (!vrng->conf.period_ms > 0) { + if (vrng->conf.period_ms <= 0) { error_setg(errp, "'period' parameter expects a positive integer"); return; } diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index f0ce18725c..5fdd2fee80 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -299,11 +299,15 @@ CPUArchState *cpu_copy(CPUArchState *env); /* memory API */ -typedef struct RAMBlock { +typedef struct RAMBlock RAMBlock; + +struct RAMBlock { struct MemoryRegion *mr; uint8_t *host; ram_addr_t offset; - ram_addr_t length; + ram_addr_t used_length; + ram_addr_t max_length; + void (*resized)(const char*, uint64_t length, void *host); uint32_t flags; char idstr[256]; /* Reads can take either the iothread or the ramlist lock. @@ -311,11 +315,11 @@ typedef struct RAMBlock { */ QTAILQ_ENTRY(RAMBlock) next; int fd; -} RAMBlock; +}; static inline void *ramblock_ptr(RAMBlock *block, ram_addr_t offset) { - assert(offset < block->length); + assert(offset < block->used_length); assert(block->host); return (char *)block->host + offset; } diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 38a8a09b42..6a154485ba 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -142,10 +142,12 @@ struct TranslationBlock { uint64_t flags; /* flags defining in which context the code was generated */ uint16_t size; /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ - uint16_t cflags; /* compile flags */ + uint16_t icount; + uint32_t cflags; /* compile flags */ #define CF_COUNT_MASK 0x7fff #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ #define CF_NOCACHE 0x10000 /* To be freed after execution */ +#define CF_USE_ICOUNT 0x20000 void *tc_ptr; /* pointer to the translated code */ /* next matching tb for physical address. */ @@ -169,7 +171,6 @@ struct TranslationBlock { jmp_first */ struct TranslationBlock *jmp_next[2]; struct TranslationBlock *jmp_first; - uint32_t icount; }; #include "exec/spinlock.h" diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index da53395de6..221aad0bfd 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -9,7 +9,7 @@ static TCGArg *icount_arg; static int icount_label; static int exitreq_label; -static inline void gen_tb_start(void) +static inline void gen_tb_start(TranslationBlock *tb) { TCGv_i32 count; TCGv_i32 flag; @@ -21,7 +21,7 @@ static inline void gen_tb_start(void) tcg_gen_brcondi_i32(TCG_COND_NE, flag, 0, exitreq_label); tcg_temp_free_i32(flag); - if (!use_icount) + if (!(tb->cflags & CF_USE_ICOUNT)) return; icount_label = gen_new_label(); @@ -43,7 +43,7 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns) gen_set_label(exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); - if (use_icount) { + if (tb->cflags & CF_USE_ICOUNT) { *icount_arg = num_insns; gen_set_label(icount_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_ICOUNT_EXPIRED); diff --git a/include/exec/memory.h b/include/exec/memory.h index f64ab5e3e5..0cd96b152e 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -321,6 +321,30 @@ void memory_region_init_ram(MemoryRegion *mr, uint64_t size, Error **errp); +/** + * memory_region_init_resizeable_ram: Initialize memory region with resizeable + * RAM. Accesses into the region will + * modify memory directly. Only an initial + * portion of this RAM is actually used. + * The used size can change across reboots. + * + * @mr: the #MemoryRegion to be initialized. + * @owner: the object that tracks the region's reference count + * @name: the name of the region. + * @size: used size of the region. + * @max_size: max size of the region. + * @resized: callback to notify owner about used size change. + * @errp: pointer to Error*, to store an error if it happens. + */ +void memory_region_init_resizeable_ram(MemoryRegion *mr, + struct Object *owner, + const char *name, + uint64_t size, + uint64_t max_size, + void (*resized)(const char*, + uint64_t length, + void *host), + Error **errp); #ifdef __linux__ /** * memory_region_init_ram_from_file: Initialize RAM memory region with a @@ -878,6 +902,16 @@ void memory_region_set_enabled(MemoryRegion *mr, bool enabled); void memory_region_set_address(MemoryRegion *mr, hwaddr addr); /* + * memory_region_set_size: dynamically update the size of a region. + * + * Dynamically updates the size of a region. + * + * @mr: the region to be updated + * @size: used size of the region. + */ +void memory_region_set_size(MemoryRegion *mr, uint64_t size); + +/* * memory_region_set_alias_offset: dynamically update a memory alias's offset * * Dynamically updates the offset into the target region that an alias points diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 8fc75cdd2b..ff558a4734 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -28,12 +28,19 @@ ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, MemoryRegion *mr, Error **errp); ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp); +ram_addr_t qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t max_size, + void (*resized)(const char*, + uint64_t length, + void *host), + MemoryRegion *mr, Error **errp); int qemu_get_ram_fd(ram_addr_t addr); void *qemu_get_ram_block_host_ptr(ram_addr_t addr); void *qemu_get_ram_ptr(ram_addr_t addr); void qemu_ram_free(ram_addr_t addr); void qemu_ram_free_from_ptr(ram_addr_t addr); +int qemu_ram_resize(ram_addr_t base, ram_addr_t newsize, Error **errp); + static inline bool cpu_physical_memory_get_dirty(ram_addr_t start, ram_addr_t length, unsigned client) @@ -172,9 +179,9 @@ static inline void cpu_physical_memory_set_dirty_lebitmap(unsigned long *bitmap, } #endif /* not _WIN32 */ -static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, - ram_addr_t length, - unsigned client) +static inline void cpu_physical_memory_clear_dirty_range_type(ram_addr_t start, + ram_addr_t length, + unsigned client) { unsigned long end, page; @@ -184,6 +191,15 @@ static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, bitmap_clear(ram_list.dirty_memory[client], page, end - page); } +static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, + ram_addr_t length) +{ + cpu_physical_memory_clear_dirty_range_type(start, length, DIRTY_MEMORY_MIGRATION); + cpu_physical_memory_clear_dirty_range_type(start, length, DIRTY_MEMORY_VGA); + cpu_physical_memory_clear_dirty_range_type(start, length, DIRTY_MEMORY_CODE); +} + + void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t length, unsigned client); diff --git a/include/hw/loader.h b/include/hw/loader.h index 899762019f..8593045d04 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -69,7 +69,7 @@ int rom_add_file(const char *file, const char *fw_dir, hwaddr addr, int32_t bootindex, bool option_rom); ram_addr_t rom_add_blob(const char *name, const void *blob, size_t len, - hwaddr addr, const char *fw_file_name, + size_t max_len, hwaddr addr, const char *fw_file_name, FWCfgReadCallback fw_callback, void *callback_opaque); int rom_add_elf_program(const char *name, void *data, size_t datasize, size_t romsize, hwaddr addr); @@ -83,7 +83,7 @@ void do_info_roms(Monitor *mon, const QDict *qdict); #define rom_add_file_fixed(_f, _a, _i) \ rom_add_file(_f, NULL, _a, _i, false) #define rom_add_blob_fixed(_f, _b, _l, _a) \ - rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL) + rom_add_blob(_f, _b, _l, _l, _a, NULL, NULL, NULL) #define PC_ROM_MIN_VGA 0xc0000 #define PC_ROM_MIN_OPTION 0xc8000 diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 97e4257ac0..97a83d362f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -88,7 +88,7 @@ #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 -#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0006 +#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 #define FMT_PCIBUS PRIx64 diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 749daf4dd7..716bff43bf 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -37,6 +37,7 @@ typedef struct sPAPREnvironment { int htab_save_index; bool htab_first_pass; int htab_fd; + bool htab_fd_stale; } sPAPREnvironment; #define H_SUCCESS 0 diff --git a/include/hw/virtio/virtio-serial.h b/include/hw/virtio/virtio-serial.h index a679e54aab..11af978a96 100644 --- a/include/hw/virtio/virtio-serial.h +++ b/include/hw/virtio/virtio-serial.h @@ -207,8 +207,6 @@ struct VirtIOSerial { /* bitmap for identifying active ports */ uint32_t *ports_map; - struct virtio_console_config config; - struct VirtIOSerialPostLoad *post_load; virtio_serial_conf serial; diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 492bce1c1b..93c2ae2f37 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -122,11 +122,11 @@ #endif #ifndef atomic_read -#define atomic_read(ptr) (*(__typeof__(*ptr) *volatile) (ptr)) +#define atomic_read(ptr) (*(__typeof__(*ptr) volatile*) (ptr)) #endif #ifndef atomic_set -#define atomic_set(ptr, i) ((*(__typeof__(*ptr) *volatile) (ptr)) = (i)) +#define atomic_set(ptr, i) ((*(__typeof__(*ptr) volatile*) (ptr)) = (i)) #endif /* These have the same semantics as Java volatile variables. @@ -1152,6 +1152,23 @@ void memory_region_init_ram(MemoryRegion *mr, mr->ram_addr = qemu_ram_alloc(size, mr, errp); } +void memory_region_init_resizeable_ram(MemoryRegion *mr, + Object *owner, + const char *name, + uint64_t size, + uint64_t max_size, + void (*resized)(const char*, + uint64_t length, + void *host), + Error **errp) +{ + memory_region_init(mr, owner, name, size); + mr->ram = true; + mr->terminates = true; + mr->destructor = memory_region_destructor_ram; + mr->ram_addr = qemu_ram_alloc_resizeable(size, max_size, resized, mr, errp); +} + #ifdef __linux__ void memory_region_init_ram_from_file(MemoryRegion *mr, struct Object *owner, @@ -1707,6 +1724,22 @@ void memory_region_set_enabled(MemoryRegion *mr, bool enabled) memory_region_transaction_commit(); } +void memory_region_set_size(MemoryRegion *mr, uint64_t size) +{ + Int128 s = int128_make64(size); + + if (size == UINT64_MAX) { + s = int128_2_64(); + } + if (int128_eq(s, mr->size)) { + return; + } + memory_region_transaction_begin(); + mr->size = s; + memory_region_update_pending = true; + memory_region_transaction_commit(); +} + static void memory_region_readd_subregion(MemoryRegion *mr) { MemoryRegion *container = mr->container; diff --git a/pc-bios/README b/pc-bios/README index edfadd7d38..8a85e69d3b 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -17,7 +17,7 @@ - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware implementation for certain IBM POWER hardware. The sources are at https://github.com/aik/SLOF, and the image currently in qemu is - built from git tag qemu-slof-20140630. + built from git tag qemu-slof-20141202. - sgabios (the Serial Graphics Adapter option ROM) provides a means for legacy x86 software to communicate with an attached serial console as diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin Binary files differindex 69b0a5dbc3..031e3063a2 100644 --- a/pc-bios/slof.bin +++ b/pc-bios/slof.bin diff --git a/qemu-seccomp.c b/qemu-seccomp.c index af6a375127..b0c626984f 100644 --- a/qemu-seccomp.c +++ b/qemu-seccomp.c @@ -235,7 +235,8 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = { { SCMP_SYS(fallocate), 240 }, { SCMP_SYS(fadvise64), 240 }, { SCMP_SYS(inotify_init1), 240 }, - { SCMP_SYS(inotify_add_watch), 240 } + { SCMP_SYS(inotify_add_watch), 240 }, + { SCMP_SYS(mbind), 240 } }; int seccomp_start(void) diff --git a/roms/SLOF b/roms/SLOF -Subproject f284ab3f03ae69a20e1ae966f6ddf76da33cbf7 +Subproject a70dbda2e21f6e438b3617c44ff180c3418dc30 diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 76658a074a..f8883672a8 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1285,7 +1285,7 @@ static int cpu_pr_data(int pr) return 0; } -static ExitStatus gen_mfpr(TCGv va, int regno) +static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) { int data = cpu_pr_data(regno); @@ -1295,7 +1295,7 @@ static ExitStatus gen_mfpr(TCGv va, int regno) if (regno == 249) { helper = gen_helper_get_vmtime; } - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); helper(va); gen_io_end(); @@ -2283,7 +2283,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) case 0xC000: /* RPCC */ va = dest_gpr(ctx, ra); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); @@ -2317,7 +2317,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) #ifndef CONFIG_USER_ONLY REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE); va = dest_gpr(ctx, ra); - ret = gen_mfpr(va, insn & 0xffff); + ret = gen_mfpr(ctx, va, insn & 0xffff); break; #else goto invalid_opc; @@ -2828,7 +2828,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, pc_mask = ~TARGET_PAGE_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 80d2c07e82..80d23597c7 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1372,7 +1372,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, break; } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -1403,7 +1403,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, } } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->is_jmp = DISAS_UPDATE; @@ -10962,7 +10962,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); tcg_clear_temp_count(); diff --git a/target-arm/translate.c b/target-arm/translate.c index b52c758698..bdfcdf169c 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7170,7 +7170,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) break; } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -7261,7 +7261,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if (use_icount && (ri->type & ARM_CP_IO)) { + if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); gen_lookup_tb(s); @@ -11080,7 +11080,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); tcg_clear_temp_count(); diff --git a/target-cris/translate.c b/target-cris/translate.c index 76406af980..b675ed0b18 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3202,7 +3202,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { check_breakpoint(env, dc); diff --git a/target-i386/translate.c b/target-i386/translate.c index fc75da7fc0..ebdc3500e5 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -1168,8 +1168,9 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot) static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_string_movl_A0_EDI(s); /* Note: we must do this dummy write first to be restartable in case of page fault. */ @@ -1181,14 +1182,16 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot) gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); + } } static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); @@ -1199,8 +1202,9 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); + } } /* same method as Valgrind : we generate jumps to current or next @@ -6278,7 +6282,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6293,7 +6297,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_outs(s, ot); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6309,12 +6313,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_movi_tl(cpu_T[0], val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6328,12 +6333,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T[1], R_EAX); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6344,12 +6350,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6362,12 +6369,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T[1], R_EAX); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7065,10 +7073,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_rdtsc(cpu_env); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7451,10 +7460,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op; gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (use_icount) + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_rdtscp(cpu_env); - if (use_icount) { + if (s->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7962,7 +7972,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, record/replay modes and there will always be an additional step for ecx=0 when icount is enabled. */ - dc->repz_opt = !dc->jmp_opt && !use_icount; + dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -7992,7 +8002,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); for(;;) { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { @@ -8040,7 +8050,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - if (use_icount + if ((tb->cflags & CF_USE_ICOUNT) && ((pc_ptr & TARGET_PAGE_MASK) != ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) || (pc_ptr & ~TARGET_PAGE_MASK) == 0)) { diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 8454e8b517..a7579dc8be 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -865,24 +865,24 @@ static void dec_wcsr(DisasContext *dc) break; case CSR_IM: /* mark as an io operation because it could cause an interrupt */ - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp = DISAS_UPDATE; break; case CSR_IP: /* mark as an io operation because it could cause an interrupt */ - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (use_icount) { + if (dc->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp = DISAS_UPDATE; @@ -1095,7 +1095,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { check_breakpoint(env, dc); diff --git a/target-m68k/translate.c b/target-m68k/translate.c index efd4cfc3c7..47edc7ae51 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3010,7 +3010,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); do { pc_offset = dc->pc - pc_start; gen_throws_exception = NULL; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index fd2b771645..69ce4df4a3 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1720,7 +1720,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); do { #if SIM_COMPAT diff --git a/target-mips/translate.c b/target-mips/translate.c index 1205909f78..e9d86b2364 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5123,10 +5123,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_mfc0_count(arg, cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -5499,8 +5500,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS32); - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } switch (reg) { case 0: @@ -6118,7 +6120,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) (void)rn; /* avoid a compiler warning */ LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); ctx->bstate = BS_STOP; } @@ -6369,10 +6371,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } gen_helper_mfc0_count(arg, cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -6738,8 +6741,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS64); - if (use_icount) + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); + } switch (reg) { case 0: @@ -7045,11 +7049,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) save_cpu_state(ctx, 1); /* Mark as an IO operation because we may trigger a software interrupt. */ - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mtc0_cause(cpu_env, arg); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } /* Stop translation as we may have triggered an intetrupt */ @@ -7358,7 +7362,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) (void)rn; /* avoid a compiler warning */ LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); ctx->bstate = BS_STOP; } @@ -19126,7 +19130,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, if (max_insns == 0) max_insns = CF_COUNT_MASK; LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); - gen_tb_start(); + gen_tb_start(tb); while (ctx.bstate == BS_NONE) { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-moxie/translate.c b/target-moxie/translate.c index 4541b9bff4..564f3eedaf 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -843,7 +843,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, ctx.bstate = BS_NONE; num_insns = 0; - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 407bd9762f..7dea405c69 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1675,7 +1675,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { check_breakpoint(cpu, dc); diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 068fcb24a2..c62097bb8a 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -320,6 +320,7 @@ typedef struct opc_handler_t opc_handler_t; /*****************************************************************************/ /* Types used to describe some PowerPC registers */ typedef struct CPUPPCState CPUPPCState; +typedef struct DisasContext DisasContext; typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_spr_t ppc_spr_t; typedef struct ppc_dcr_t ppc_dcr_t; @@ -328,13 +329,13 @@ typedef union ppc_tlb_t ppc_tlb_t; /* SPR access micro-ops generations callbacks */ struct ppc_spr_t { - void (*uea_read)(void *opaque, int gpr_num, int spr_num); - void (*uea_write)(void *opaque, int spr_num, int gpr_num); + void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num); + void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num); #if !defined(CONFIG_USER_ONLY) - void (*oea_read)(void *opaque, int gpr_num, int spr_num); - void (*oea_write)(void *opaque, int spr_num, int gpr_num); - void (*hea_read)(void *opaque, int gpr_num, int spr_num); - void (*hea_write)(void *opaque, int spr_num, int gpr_num); + void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num); + void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); + void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); + void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); #endif const char *name; target_ulong default_value; @@ -558,6 +559,26 @@ struct ppc_slb_t { #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */ #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */ +/* Transaction EXception And Summary Register bits */ +#define TEXASR_FAILURE_PERSISTENT (63 - 7) +#define TEXASR_DISALLOWED (63 - 8) +#define TEXASR_NESTING_OVERFLOW (63 - 9) +#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) +#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) +#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) +#define TEXASR_TRANSACTION_CONFLICT (63 - 13) +#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) +#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) +#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) +#define TEXASR_ABORT (63 - 31) +#define TEXASR_SUSPENDED (63 - 32) +#define TEXASR_PRIVILEGE_HV (63 - 34) +#define TEXASR_PRIVILEGE_PR (63 - 35) +#define TEXASR_FAILURE_SUMMARY (63 - 36) +#define TEXASR_TFIAR_EXACT (63 - 37) +#define TEXASR_ROT (63 - 38) +#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ + enum { POWERPC_FLAG_NONE = 0x00000000, /* Flag for MSR bit 25 signification (VRE/SPE) */ @@ -584,6 +605,8 @@ enum { POWERPC_FLAG_CFAR = 0x00040000, /* Has VSX */ POWERPC_FLAG_VSX = 0x00080000, + /* Has Transaction Memory (ISA 2.07) */ + POWERPC_FLAG_TM = 0x00100000, }; /*****************************************************************************/ @@ -2010,6 +2033,8 @@ enum { PPC2_ISA207S = 0x0000000000008000ULL, /* Double precision floating point conversion for signed integer 64 */ PPC2_FP_CVT_S64 = 0x0000000000010000ULL, + /* Transactional Memory (ISA 2.07, Book II) */ + PPC2_TM = 0x0000000000020000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2017,7 +2042,7 @@ enum { PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ - PPC2_FP_CVT_S64) + PPC2_FP_CVT_S64 | PPC2_TM) }; /*****************************************************************************/ diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 7f74466f32..6cceffc556 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -19,6 +19,9 @@ #include "cpu.h" #include "exec/helper-proto.h" +#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL) +#define float32_snan_to_qnan(x) ((x) | 0x00400000) + /*****************************************************************************/ /* Floating point operations helpers */ uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) @@ -60,59 +63,55 @@ static inline int ppc_float64_get_unbiased_exp(float64 f) return ((f >> 52) & 0x7FF) - 1023; } -uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf) +void helper_compute_fprf(CPUPPCState *env, uint64_t arg) { CPU_DoubleU farg; int isneg; - int ret; + int fprf; farg.ll = arg; isneg = float64_is_neg(farg.d); if (unlikely(float64_is_any_nan(farg.d))) { if (float64_is_signaling_nan(farg.d)) { /* Signaling NaN: flags are undefined */ - ret = 0x00; + fprf = 0x00; } else { /* Quiet NaN */ - ret = 0x11; + fprf = 0x11; } } else if (unlikely(float64_is_infinity(farg.d))) { /* +/- infinity */ if (isneg) { - ret = 0x09; + fprf = 0x09; } else { - ret = 0x05; + fprf = 0x05; } } else { if (float64_is_zero(farg.d)) { /* +/- zero */ if (isneg) { - ret = 0x12; + fprf = 0x12; } else { - ret = 0x02; + fprf = 0x02; } } else { if (isden(farg.d)) { /* Denormalized numbers */ - ret = 0x10; + fprf = 0x10; } else { /* Normalized numbers */ - ret = 0x00; + fprf = 0x00; } if (isneg) { - ret |= 0x08; + fprf |= 0x08; } else { - ret |= 0x04; + fprf |= 0x04; } } } - if (set_fprf) { - /* We update FPSCR_FPRF */ - env->fpscr &= ~(0x1F << FPSCR_FPRF); - env->fpscr |= ret << FPSCR_FPRF; - } - /* We just need fpcc to update Rc1 */ - return ret & 0xF; + /* We update FPSCR_FPRF */ + env->fpscr &= ~(0x1F << FPSCR_FPRF); + env->fpscr |= fprf << FPSCR_FPRF; } /* Floating-point invalid operations exception */ @@ -920,14 +919,16 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg) farg.ll = arg; - if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { - /* Square root of a negative nonzero number */ - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - } else { + if (unlikely(float64_is_any_nan(farg.d))) { if (unlikely(float64_is_signaling_nan(farg.d))) { - /* sNaN square root */ + /* sNaN reciprocal square root */ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + farg.ll = float64_snan_to_qnan(farg.ll); } + } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { + /* Square root of a negative nonzero number */ + farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + } else { farg.d = float64_sqrt(farg.d, &env->fp_status); } return farg.ll; @@ -974,17 +975,20 @@ uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg) farg.ll = arg; - if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { - /* Reciprocal square root of a negative nonzero number */ - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - } else { + if (unlikely(float64_is_any_nan(farg.d))) { if (unlikely(float64_is_signaling_nan(farg.d))) { /* sNaN reciprocal square root */ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + farg.ll = float64_snan_to_qnan(farg.ll); } + } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { + /* Reciprocal square root of a negative nonzero number */ + farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + } else { farg.d = float64_sqrt(farg.d, &env->fp_status); farg.d = float64_div(float64_one, farg.d, &env->fp_status); } + return farg.ll; } @@ -1845,7 +1849,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ } \ \ if (sfprf) { \ - helper_compute_fprf(env, xt.fld, sfprf); \ + helper_compute_fprf(env, xt.fld); \ } \ } \ putVSR(xT(opcode), &xt, env); \ @@ -1900,7 +1904,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ if (sfprf) { \ - helper_compute_fprf(env, xt.fld, sfprf); \ + helper_compute_fprf(env, xt.fld); \ } \ } \ \ @@ -1954,7 +1958,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ if (sfprf) { \ - helper_compute_fprf(env, xt.fld, sfprf); \ + helper_compute_fprf(env, xt.fld); \ } \ } \ \ @@ -1995,7 +1999,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ if (sfprf) { \ - helper_compute_fprf(env, xt.fld, sfprf); \ + helper_compute_fprf(env, xt.fld); \ } \ } \ \ @@ -2044,7 +2048,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ if (sfprf) { \ - helper_compute_fprf(env, xt.fld, sfprf); \ + helper_compute_fprf(env, xt.fld); \ } \ } \ \ @@ -2094,7 +2098,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ if (sfprf) { \ - helper_compute_fprf(env, xt.fld, sfprf); \ + helper_compute_fprf(env, xt.fld); \ } \ } \ \ @@ -2294,7 +2298,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ \ if (sfprf) { \ - helper_compute_fprf(env, xt_out.fld, sfprf); \ + helper_compute_fprf(env, xt_out.fld); \ } \ } \ putVSR(xT(opcode), &xt_out, env); \ @@ -2382,9 +2386,6 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ VSX_SCALAR_CMP(xscmpodp, 1) VSX_SCALAR_CMP(xscmpudp, 0) -#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL) -#define float32_snan_to_qnan(x) ((x) | 0x00400000) - /* VSX_MAX_MIN - VSX floating point maximum/minimum * name - instruction mnemonic * op - operation (max or min) @@ -2504,7 +2505,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ if (sfprf) { \ helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \ - &env->fp_status), sfprf); \ + &env->fp_status)); \ } \ } \ \ @@ -2614,7 +2615,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ xt.tfld = helper_frsp(env, xt.tfld); \ } \ if (sfprf) { \ - helper_compute_fprf(env, xt.tfld, sfprf); \ + helper_compute_fprf(env, xt.tfld); \ } \ } \ \ @@ -2669,7 +2670,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \ } \ if (sfprf) { \ - helper_compute_fprf(env, xt.fld, sfprf); \ + helper_compute_fprf(env, xt.fld); \ } \ } \ \ @@ -2709,7 +2710,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) uint64_t xt = helper_frsp(env, xb); - helper_compute_fprf(env, xt, 1); + helper_compute_fprf(env, xt); helper_float_check_status(env); return xt; } diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 210fd97f6a..869be1509d 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -52,7 +52,7 @@ DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_1(float_check_status, void, env) DEF_HELPER_1(reset_fpstatus, void, env) -DEF_HELPER_3(compute_fprf, i32, env, i64, i32) +DEF_HELPER_2(compute_fprf, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) DEF_HELPER_2(fpscr_clrbit, void, env, i32) DEF_HELPER_2(fpscr_setbit, void, env, i32) @@ -665,3 +665,5 @@ DEF_HELPER_4(dscri, void, env, fprp, fprp, i32) DEF_HELPER_4(dscriq, void, env, fprp, fprp, i32) DEF_HELPER_4(dscli, void, env, fprp, fprp, i32) DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32) + +DEF_HELPER_1(tbegin, void, env) diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 6843fa0b98..911f91212a 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -2246,8 +2246,23 @@ int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) strerror(errno)); return rc; } else if (rc) { - /* Kernel already retuns data in BE format for the file */ - qemu_put_buffer(f, buf, rc); + uint8_t *buffer = buf; + ssize_t n = rc; + while (n) { + struct kvm_get_htab_header *head = + (struct kvm_get_htab_header *) buffer; + size_t chunksize = sizeof(*head) + + HASH_PTE_SIZE_64 * head->n_valid; + + qemu_put_be32(f, head->index); + qemu_put_be16(f, head->n_valid); + qemu_put_be16(f, head->n_invalid); + qemu_put_buffer(f, (void *)(head + 1), + HASH_PTE_SIZE_64 * head->n_valid); + + buffer += chunksize; + n -= chunksize; + } } } while ((rc != 0) && ((max_ns < 0) @@ -2264,7 +2279,6 @@ int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, ssize_t rc; buf = alloca(chunksize); - /* This is KVM on ppc, so this is all big-endian */ buf->index = index; buf->n_valid = n_valid; buf->n_invalid = n_invalid; diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c index 50344b81cf..6d37dae7b0 100644 --- a/target-ppc/mem_helper.c +++ b/target-ppc/mem_helper.c @@ -269,3 +269,25 @@ STVE(stvewx, cpu_stl_data, bswap32, u32) #undef HI_IDX #undef LO_IDX + +void helper_tbegin(CPUPPCState *env) +{ + /* As a degenerate implementation, always fail tbegin. The reason + * given is "Nesting overflow". The "persistent" bit is set, + * providing a hint to the error handler to not retry. The TFIAR + * captures the address of the failure, which is this tbegin + * instruction. Instruction execution will continue with the + * next instruction in memory, which is precisely what we want. + */ + + env->spr[SPR_TEXASR] = + (1ULL << TEXASR_FAILURE_PERSISTENT) | + (1ULL << TEXASR_NESTING_OVERFLOW) | + (msr_hv << TEXASR_PRIVILEGE_HV) | + (msr_pr << TEXASR_PRIVILEGE_PR) | + (1ULL << TEXASR_FAILURE_SUMMARY) | + (1ULL << TEXASR_TFIAR_EXACT); + env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr; + env->spr[SPR_TFHAR] = env->nip + 4; + env->crf[0] = 0xB; /* 0b1010 = transaction failure */ +} diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d381632c86..7c801f36e3 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -183,7 +183,7 @@ void ppc_translate_init(void) } /* internal defines */ -typedef struct DisasContext { +struct DisasContext { struct TranslationBlock *tb; target_ulong nip; uint32_t opcode; @@ -203,11 +203,12 @@ typedef struct DisasContext { int altivec_enabled; int vsx_enabled; int spe_enabled; + int tm_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint64_t insns_flags; uint64_t insns_flags2; -} DisasContext; +}; /* Return true iff byteswap is needed in a scalar memop */ static inline bool need_byteswap(const DisasContext *ctx) @@ -250,26 +251,10 @@ static inline void gen_reset_fpstatus(void) gen_helper_reset_fpstatus(cpu_env); } -static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) +static inline void gen_compute_fprf(TCGv_i64 arg) { - TCGv_i32 t0 = tcg_temp_new_i32(); - - if (set_fprf != 0) { - /* This case might be optimized later */ - tcg_gen_movi_i32(t0, 1); - gen_helper_compute_fprf(t0, cpu_env, arg, t0); - if (unlikely(set_rc)) { - tcg_gen_mov_i32(cpu_crf[1], t0); - } - gen_helper_float_check_status(cpu_env); - } else if (unlikely(set_rc)) { - /* We always need to compute fpcc */ - tcg_gen_movi_i32(t0, 0); - gen_helper_compute_fprf(t0, cpu_env, arg, t0); - tcg_gen_mov_i32(cpu_crf[1], t0); - } - - tcg_temp_free_i32(t0); + gen_helper_compute_fprf(cpu_env, arg); + gen_helper_float_check_status(cpu_env); } static inline void gen_set_access_type(DisasContext *ctx, int access_type) @@ -346,11 +331,13 @@ static inline void gen_stop_exception(DisasContext *ctx) ctx->exception = POWERPC_EXCP_STOP; } +#ifndef CONFIG_USER_ONLY /* No need to update nip here, as execution flow will change */ static inline void gen_sync_exception(DisasContext *ctx) { ctx->exception = POWERPC_EXCP_SYNC; } +#endif #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) @@ -452,7 +439,10 @@ EXTRACT_HELPER(ME, 1, 5); EXTRACT_HELPER(TO, 21, 5); EXTRACT_HELPER(CRM, 12, 8); + +#ifndef CONFIG_USER_ONLY EXTRACT_HELPER(SR, 16, 4); +#endif /* mtfsf/mtfsfi */ EXTRACT_HELPER(FPBF, 23, 3); @@ -2077,6 +2067,21 @@ static void gen_srd(DisasContext *ctx) } #endif +#if defined(TARGET_PPC64) +static void gen_set_cr1_from_fpscr(DisasContext *ctx) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], tmp, 28); + tcg_temp_free_i32(tmp); +} +#else +static void gen_set_cr1_from_fpscr(DisasContext *ctx) +{ + tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); +} +#endif + /*** Floating-Point arithmetic ***/ #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ @@ -2095,8 +2100,12 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rD(ctx->opcode)]); \ } \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ - Rc(ctx->opcode) != 0); \ + if (set_fprf) { \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ } #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ @@ -2120,8 +2129,12 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rD(ctx->opcode)]); \ } \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + if (set_fprf) { \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ @@ -2144,8 +2157,12 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rD(ctx->opcode)]); \ } \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + if (set_fprf) { \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ @@ -2163,8 +2180,12 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rB(ctx->opcode)]); \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + if (set_fprf) { \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ } #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ @@ -2179,8 +2200,12 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ cpu_fpr[rB(ctx->opcode)]); \ - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ - set_fprf, Rc(ctx->opcode) != 0); \ + if (set_fprf) { \ + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \ + } \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_cr1_from_fpscr(ctx); \ + } \ } /* fadd - fadds */ @@ -2213,7 +2238,10 @@ static void gen_frsqrtes(DisasContext *ctx) cpu_fpr[rB(ctx->opcode)]); gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(ctx); + } } /* fsel */ @@ -2234,7 +2262,10 @@ static void gen_fsqrt(DisasContext *ctx) gen_reset_fpstatus(); gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, cpu_fpr[rB(ctx->opcode)]); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(ctx); + } } static void gen_fsqrts(DisasContext *ctx) @@ -2250,7 +2281,10 @@ static void gen_fsqrts(DisasContext *ctx) cpu_fpr[rB(ctx->opcode)]); gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_cr1_from_fpscr(ctx); + } } /*** Floating-Point multiply-and-add ***/ @@ -2370,7 +2404,9 @@ static void gen_fabs(DisasContext *ctx) } tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], ~(1ULL << 63)); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } /* fmr - fmr. */ @@ -2382,7 +2418,9 @@ static void gen_fmr(DisasContext *ctx) return; } tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } /* fnabs */ @@ -2395,7 +2433,9 @@ static void gen_fnabs(DisasContext *ctx) } tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], 1ULL << 63); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } /* fneg */ @@ -2408,7 +2448,9 @@ static void gen_fneg(DisasContext *ctx) } tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], 1ULL << 63); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } /* fcpsgn: PowerPC 2.05 specification */ @@ -2421,7 +2463,9 @@ static void gen_fcpsgn(DisasContext *ctx) } tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], 0, 63); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } static void gen_fmrgew(DisasContext *ctx) @@ -2479,7 +2523,9 @@ static void gen_mffs(DisasContext *ctx) } gen_reset_fpstatus(); tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } /* mtfsb0 */ @@ -4206,7 +4252,7 @@ static void gen_mfmsr(DisasContext *ctx) #endif } -static void spr_noaccess(void *opaque, int gprn, int sprn) +static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) { #if 0 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); @@ -4218,7 +4264,7 @@ static void spr_noaccess(void *opaque, int gprn, int sprn) /* mfspr */ static inline void gen_op_mfspr(DisasContext *ctx) { - void (*read_cb)(void *opaque, int gprn, int sprn); + void (*read_cb)(DisasContext *ctx, int gprn, int sprn); uint32_t sprn = SPR(ctx->opcode); #if !defined(CONFIG_USER_ONLY) @@ -4369,7 +4415,7 @@ static void gen_mtmsr(DisasContext *ctx) /* mtspr */ static void gen_mtspr(DisasContext *ctx) { - void (*write_cb)(void *opaque, int sprn, int gprn); + void (*write_cb)(DisasContext *ctx, int sprn, int gprn); uint32_t sprn = SPR(ctx->opcode); #if !defined(CONFIG_USER_ONLY) @@ -6743,7 +6789,7 @@ static void gen_st##name(DisasContext *ctx) \ tcg_temp_free(EA); \ } -#define GEN_VR_LVE(name, opc2, opc3) \ +#define GEN_VR_LVE(name, opc2, opc3, size) \ static void gen_lve##name(DisasContext *ctx) \ { \ TCGv EA; \ @@ -6755,13 +6801,16 @@ static void gen_lve##name(DisasContext *ctx) \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ + if (size > 1) { \ + tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ + } \ rs = gen_avr_ptr(rS(ctx->opcode)); \ gen_helper_lve##name(cpu_env, rs, EA); \ tcg_temp_free(EA); \ tcg_temp_free_ptr(rs); \ } -#define GEN_VR_STVE(name, opc2, opc3) \ +#define GEN_VR_STVE(name, opc2, opc3, size) \ static void gen_stve##name(DisasContext *ctx) \ { \ TCGv EA; \ @@ -6773,6 +6822,9 @@ static void gen_stve##name(DisasContext *ctx) \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ + if (size > 1) { \ + tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ + } \ rs = gen_avr_ptr(rS(ctx->opcode)); \ gen_helper_stve##name(cpu_env, rs, EA); \ tcg_temp_free(EA); \ @@ -6783,17 +6835,17 @@ GEN_VR_LDX(lvx, 0x07, 0x03); /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ GEN_VR_LDX(lvxl, 0x07, 0x0B); -GEN_VR_LVE(bx, 0x07, 0x00); -GEN_VR_LVE(hx, 0x07, 0x01); -GEN_VR_LVE(wx, 0x07, 0x02); +GEN_VR_LVE(bx, 0x07, 0x00, 1); +GEN_VR_LVE(hx, 0x07, 0x01, 2); +GEN_VR_LVE(wx, 0x07, 0x02, 4); GEN_VR_STX(svx, 0x07, 0x07); /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ GEN_VR_STX(svxl, 0x07, 0x0F); -GEN_VR_STVE(bx, 0x07, 0x04); -GEN_VR_STVE(hx, 0x07, 0x05); -GEN_VR_STVE(wx, 0x07, 0x06); +GEN_VR_STVE(bx, 0x07, 0x04, 1); +GEN_VR_STVE(hx, 0x07, 0x05, 2); +GEN_VR_STVE(wx, 0x07, 0x06, 4); static void gen_lvsl(DisasContext *ctx) { @@ -8205,21 +8257,6 @@ static inline TCGv_ptr gen_fprp_ptr(int reg) return r; } -#if defined(TARGET_PPC64) -static void gen_set_cr1_from_fpscr(DisasContext *ctx) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], tmp, 28); - tcg_temp_free_i32(tmp); -} -#else -static void gen_set_cr1_from_fpscr(DisasContext *ctx) -{ - tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); -} -#endif - #define GEN_DFP_T_A_B_Rc(name) \ static void gen_##name(DisasContext *ctx) \ { \ @@ -9642,6 +9679,88 @@ GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // +static void gen_tbegin(DisasContext *ctx) +{ + if (unlikely(!ctx->tm_enabled)) { + gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); + return; + } + gen_helper_tbegin(cpu_env); +} + +#define GEN_TM_NOOP(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + if (unlikely(!ctx->tm_enabled)) { \ + gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ + return; \ + } \ + /* Because tbegin always fails in QEMU, these user \ + * space instructions all have a simple implementation: \ + * \ + * CR[0] = 0b0 || MSR[TS] || 0b0 \ + * = 0b0 || 0b00 || 0b0 \ + */ \ + tcg_gen_movi_i32(cpu_crf[0], 0); \ +} + +GEN_TM_NOOP(tend); +GEN_TM_NOOP(tabort); +GEN_TM_NOOP(tabortwc); +GEN_TM_NOOP(tabortwci); +GEN_TM_NOOP(tabortdc); +GEN_TM_NOOP(tabortdci); +GEN_TM_NOOP(tsr); + +static void gen_tcheck(DisasContext *ctx) +{ + if (unlikely(!ctx->tm_enabled)) { + gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); + return; + } + /* Because tbegin always fails, the tcheck implementation + * is simple: + * + * CR[CRF] = TDOOMED || MSR[TS] || 0b0 + * = 0b1 || 0b00 || 0b0 + */ + tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); +} + +#if defined(CONFIG_USER_ONLY) +#define GEN_TM_PRIV_NOOP(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ +} + +#else + +#define GEN_TM_PRIV_NOOP(name) \ +static inline void gen_##name(DisasContext *ctx) \ +{ \ + if (unlikely(ctx->pr)) { \ + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ + return; \ + } \ + if (unlikely(!ctx->tm_enabled)) { \ + gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ + return; \ + } \ + /* Because tbegin always fails, the implementation is \ + * simple: \ + * \ + * CR[0] = 0b0 || MSR[TS] || 0b0 \ + * = 0b0 || 0b00 | 0b0 \ + */ \ + tcg_gen_movi_i32(cpu_crf[0], 0); \ +} + +#endif + +GEN_TM_PRIV_NOOP(treclaim); +GEN_TM_PRIV_NOOP(trechkpt); + static opcode_t opcodes[] = { GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), @@ -11054,6 +11173,29 @@ GEN_SPEOP_LDST(evstwhe, 0x18, 2), GEN_SPEOP_LDST(evstwho, 0x1A, 2), GEN_SPEOP_LDST(evstwwe, 0x1C, 2), GEN_SPEOP_LDST(evstwwo, 0x1E, 2), + +GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ + PPC_NONE, PPC2_TM), +GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ + PPC_NONE, PPC2_TM), }; #include "helper_regs.h" @@ -11311,6 +11453,13 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, } else { ctx.vsx_enabled = 0; } +#if defined(TARGET_PPC64) + if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { + ctx.tm_enabled = msr_tm; + } else { + ctx.tm_enabled = 0; + } +#endif if ((env->flags & POWERPC_FLAG_SE) && msr_se) ctx.singlestep_enabled = CPU_SINGLE_STEP; else @@ -11329,7 +11478,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); tcg_clear_temp_count(); /* Set env in case of segfault during code fetch */ while (ctx.exception == POWERPC_EXCP_NONE diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 1fece7b97c..df1a62c4c6 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -65,7 +65,7 @@ static void spr_load_dump_spr(int sprn) #endif } -static void spr_read_generic (void *opaque, int gprn, int sprn) +static void spr_read_generic (DisasContext *ctx, int gprn, int sprn) { gen_load_spr(cpu_gpr[gprn], sprn); spr_load_dump_spr(sprn); @@ -80,14 +80,14 @@ static void spr_store_dump_spr(int sprn) #endif } -static void spr_write_generic (void *opaque, int sprn, int gprn) +static void spr_write_generic (DisasContext *ctx, int sprn, int gprn) { gen_store_spr(sprn, cpu_gpr[gprn]); spr_store_dump_spr(sprn); } #if !defined(CONFIG_USER_ONLY) -static void spr_write_generic32(void *opaque, int sprn, int gprn) +static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { #ifdef TARGET_PPC64 TCGv t0 = tcg_temp_new(); @@ -96,11 +96,11 @@ static void spr_write_generic32(void *opaque, int sprn, int gprn) tcg_temp_free(t0); spr_store_dump_spr(sprn); #else - spr_write_generic(opaque, sprn, gprn); + spr_write_generic(ctx, sprn, gprn); #endif } -static void spr_write_clear (void *opaque, int sprn, int gprn) +static void spr_write_clear (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -112,7 +112,7 @@ static void spr_write_clear (void *opaque, int sprn, int gprn) tcg_temp_free(t1); } -static void spr_access_nop(void *opaque, int sprn, int gprn) +static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) { } @@ -120,47 +120,47 @@ static void spr_access_nop(void *opaque, int sprn, int gprn) /* SPR common to all PowerPC */ /* XER */ -static void spr_read_xer (void *opaque, int gprn, int sprn) +static void spr_read_xer (DisasContext *ctx, int gprn, int sprn) { gen_read_xer(cpu_gpr[gprn]); } -static void spr_write_xer (void *opaque, int sprn, int gprn) +static void spr_write_xer (DisasContext *ctx, int sprn, int gprn) { gen_write_xer(cpu_gpr[gprn]); } /* LR */ -static void spr_read_lr (void *opaque, int gprn, int sprn) +static void spr_read_lr (DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); } -static void spr_write_lr (void *opaque, int sprn, int gprn) +static void spr_write_lr (DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); } /* CFAR */ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -static void spr_read_cfar (void *opaque, int gprn, int sprn) +static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); } -static void spr_write_cfar (void *opaque, int sprn, int gprn) +static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); } #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ /* CTR */ -static void spr_read_ctr (void *opaque, int gprn, int sprn) +static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); } -static void spr_write_ctr (void *opaque, int sprn, int gprn) +static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); } @@ -171,13 +171,13 @@ static void spr_write_ctr (void *opaque, int sprn, int gprn) /* UPMCx */ /* USIA */ /* UDECR */ -static void spr_read_ureg (void *opaque, int gprn, int sprn) +static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn) { gen_load_spr(cpu_gpr[gprn], sprn + 0x10); } #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) -static void spr_write_ureg(void *opaque, int sprn, int gprn) +static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) { gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); } @@ -186,109 +186,109 @@ static void spr_write_ureg(void *opaque, int sprn, int gprn) /* SPR common to all non-embedded PowerPC */ /* DECR */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_decr (void *opaque, int gprn, int sprn) +static void spr_read_decr (DisasContext *ctx, int gprn, int sprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_decr(cpu_gpr[gprn], cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } -static void spr_write_decr (void *opaque, int sprn, int gprn) +static void spr_write_decr (DisasContext *ctx, int sprn, int gprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } #endif /* SPR common to all non-embedded PowerPC, except 601 */ /* Time base */ -static void spr_read_tbl (void *opaque, int gprn, int sprn) +static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } -static void spr_read_tbu (void *opaque, int gprn, int sprn) +static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } __attribute__ (( unused )) -static void spr_read_atbl (void *opaque, int gprn, int sprn) +static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); } __attribute__ (( unused )) -static void spr_read_atbu (void *opaque, int gprn, int sprn) +static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); } #if !defined(CONFIG_USER_ONLY) -static void spr_write_tbl (void *opaque, int sprn, int gprn) +static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } -static void spr_write_tbu (void *opaque, int sprn, int gprn) +static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn) { - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); - if (use_icount) { + if (ctx->tb->cflags & CF_USE_ICOUNT) { gen_io_end(); - gen_stop_exception(opaque); + gen_stop_exception(ctx); } } __attribute__ (( unused )) -static void spr_write_atbl (void *opaque, int sprn, int gprn) +static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); } __attribute__ (( unused )) -static void spr_write_atbu (void *opaque, int sprn, int gprn) +static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); } #if defined(TARGET_PPC64) __attribute__ (( unused )) -static void spr_read_purr (void *opaque, int gprn, int sprn) +static void spr_read_purr (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_purr(cpu_gpr[gprn], cpu_env); } @@ -298,38 +298,38 @@ static void spr_read_purr (void *opaque, int gprn, int sprn) #if !defined(CONFIG_USER_ONLY) /* IBAT0U...IBAT0U */ /* IBAT0L...IBAT7L */ -static void spr_read_ibat (void *opaque, int gprn, int sprn) +static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); } -static void spr_read_ibat_h (void *opaque, int gprn, int sprn) +static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2])); } -static void spr_write_ibatu (void *opaque, int sprn, int gprn) +static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) +static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_ibatl (void *opaque, int sprn, int gprn) +static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) +static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); @@ -338,38 +338,38 @@ static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) /* DBAT0U...DBAT7U */ /* DBAT0L...DBAT7L */ -static void spr_read_dbat (void *opaque, int gprn, int sprn) +static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); } -static void spr_read_dbat_h (void *opaque, int gprn, int sprn) +static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); } -static void spr_write_dbatu (void *opaque, int sprn, int gprn) +static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_dbatu_h (void *opaque, int sprn, int gprn) +static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_dbatl (void *opaque, int sprn, int gprn) +static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) +static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); @@ -377,19 +377,19 @@ static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) } /* SDR1 */ -static void spr_write_sdr1 (void *opaque, int sprn, int gprn) +static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); } /* 64 bits PowerPC specific SPRs */ #if defined(TARGET_PPC64) -static void spr_read_hior (void *opaque, int gprn, int sprn) +static void spr_read_hior (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); } -static void spr_write_hior (void *opaque, int sprn, int gprn) +static void spr_write_hior (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); @@ -401,31 +401,29 @@ static void spr_write_hior (void *opaque, int sprn, int gprn) /* PowerPC 601 specific registers */ /* RTC */ -static void spr_read_601_rtcl (void *opaque, int gprn, int sprn) +static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); } -static void spr_read_601_rtcu (void *opaque, int gprn, int sprn) +static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); } #if !defined(CONFIG_USER_ONLY) -static void spr_write_601_rtcu (void *opaque, int sprn, int gprn) +static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); } -static void spr_write_601_rtcl (void *opaque, int sprn, int gprn) +static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); } -static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) +static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn) { - DisasContext *ctx = opaque; - gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); /* Must stop the translation as endianness may have changed */ gen_stop_exception(ctx); @@ -434,19 +432,19 @@ static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) /* Unified bats */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_601_ubat (void *opaque, int gprn, int sprn) +static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); } -static void spr_write_601_ubatu (void *opaque, int sprn, int gprn) +static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) +static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); @@ -456,36 +454,34 @@ static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) /* PowerPC 40x specific registers */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_40x_pit (void *opaque, int gprn, int sprn) +static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn) { gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); } -static void spr_write_40x_pit (void *opaque, int sprn, int gprn) +static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); } -static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) +static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn) { - DisasContext *ctx = opaque; - gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); /* We must stop translation as we may have rebooted */ gen_stop_exception(ctx); } -static void spr_write_40x_sler (void *opaque, int sprn, int gprn) +static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); } -static void spr_write_booke_tcr (void *opaque, int sprn, int gprn) +static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); } -static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) +static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn) { gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); } @@ -494,19 +490,19 @@ static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) /* PowerPC 403 specific registers */ /* PBL1 / PBU1 / PBL2 / PBU2 */ #if !defined(CONFIG_USER_ONLY) -static void spr_read_403_pbr (void *opaque, int gprn, int sprn) +static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn) { tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); } -static void spr_write_403_pbr (void *opaque, int sprn, int gprn) +static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } -static void spr_write_pir (void *opaque, int sprn, int gprn) +static void spr_write_pir (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); @@ -516,7 +512,7 @@ static void spr_write_pir (void *opaque, int sprn, int gprn) #endif /* SPE specific registers */ -static void spr_read_spefscr (void *opaque, int gprn, int sprn) +static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn) { TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); @@ -524,7 +520,7 @@ static void spr_read_spefscr (void *opaque, int gprn, int sprn) tcg_temp_free_i32(t0); } -static void spr_write_spefscr (void *opaque, int sprn, int gprn) +static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); @@ -534,7 +530,7 @@ static void spr_write_spefscr (void *opaque, int sprn, int gprn) #if !defined(CONFIG_USER_ONLY) /* Callback used to write the exception vector base */ -static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) +static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); @@ -544,9 +540,8 @@ static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) tcg_temp_free(t0); } -static void spr_write_excp_vector (void *opaque, int sprn, int gprn) +static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn) { - DisasContext *ctx = opaque; int sprn_offs; if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { @@ -604,12 +599,12 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val) static inline void _spr_register(CPUPPCState *env, int num, const char *name, - void (*uea_read)(void *opaque, int gprn, int sprn), - void (*uea_write)(void *opaque, int sprn, int gprn), + void (*uea_read)(DisasContext *ctx, int gprn, int sprn), + void (*uea_write)(DisasContext *ctx, int sprn, int gprn), #if !defined(CONFIG_USER_ONLY) - void (*oea_read)(void *opaque, int gprn, int sprn), - void (*oea_write)(void *opaque, int sprn, int gprn), + void (*oea_read)(DisasContext *ctx, int gprn, int sprn), + void (*oea_write)(DisasContext *ctx, int sprn, int gprn), #endif #if defined(CONFIG_KVM) uint64_t one_reg_id, @@ -1040,19 +1035,19 @@ static void gen_spr_7xx (CPUPPCState *env) #ifdef TARGET_PPC64 #ifndef CONFIG_USER_ONLY -static void spr_read_uamr (void *opaque, int gprn, int sprn) +static void spr_read_uamr (DisasContext *ctx, int gprn, int sprn) { gen_load_spr(cpu_gpr[gprn], SPR_AMR); spr_load_dump_spr(SPR_AMR); } -static void spr_write_uamr (void *opaque, int sprn, int gprn) +static void spr_write_uamr (DisasContext *ctx, int sprn, int gprn) { gen_store_spr(SPR_AMR, cpu_gpr[gprn]); spr_store_dump_spr(SPR_AMR); } -static void spr_write_uamr_pr (void *opaque, int sprn, int gprn) +static void spr_write_uamr_pr (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); @@ -1454,7 +1449,7 @@ static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) } #if !defined(CONFIG_USER_ONLY) -static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) +static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); @@ -1463,7 +1458,7 @@ static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) tcg_temp_free(t0); } -static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn) +static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); @@ -1472,12 +1467,12 @@ static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn) tcg_temp_free(t0); } -static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) +static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn) { gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); } -static void spr_write_booke_pid (void *opaque, int sprn, int gprn) +static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(sprn); gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); @@ -1693,7 +1688,7 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, /* TLB assist registers */ /* XXX : not implemented */ for (i = 0; i < 8; i++) { - void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32; + void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32; if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { uea_write = &spr_write_generic; } @@ -4680,7 +4675,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) } #if !defined(CONFIG_USER_ONLY) -static void spr_write_mas73(void *opaque, int sprn, int gprn) +static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) { TCGv val = tcg_temp_new(); tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); @@ -4690,7 +4685,7 @@ static void spr_write_mas73(void *opaque, int sprn, int gprn) tcg_temp_free(val); } -static void spr_read_mas73(void *opaque, int gprn, int sprn) +static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) { TCGv mas7 = tcg_temp_new(); TCGv mas3 = tcg_temp_new(); @@ -7322,14 +7317,14 @@ enum BOOK3S_CPU_TYPE { BOOK3S_CPU_POWER8 }; -static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit, - int sprn, int cause) +static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, + int bit, int sprn, int cause) { TCGv_i32 t1 = tcg_const_i32(bit); TCGv_i32 t2 = tcg_const_i32(sprn); TCGv_i32 t3 = tcg_const_i32(cause); - gen_update_current_nip(opaque); + gen_update_current_nip(ctx); gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); tcg_temp_free_i32(t3); @@ -7337,14 +7332,14 @@ static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit, tcg_temp_free_i32(t1); } -static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit, - int sprn, int cause) +static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, + int bit, int sprn, int cause) { TCGv_i32 t1 = tcg_const_i32(bit); TCGv_i32 t2 = tcg_const_i32(sprn); TCGv_i32 t3 = tcg_const_i32(cause); - gen_update_current_nip(opaque); + gen_update_current_nip(ctx); gen_helper_msr_facility_check(cpu_env, t1, t2, t3); tcg_temp_free_i32(t3); @@ -7352,7 +7347,7 @@ static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit, tcg_temp_free_i32(t1); } -static void spr_read_prev_upper32(void *opaque, int gprn, int sprn) +static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) { TCGv spr_up = tcg_temp_new(); TCGv spr = tcg_temp_new(); @@ -7365,7 +7360,7 @@ static void spr_read_prev_upper32(void *opaque, int gprn, int sprn) tcg_temp_free(spr_up); } -static void spr_write_prev_upper32(void *opaque, int sprn, int gprn) +static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) { TCGv spr = tcg_temp_new(); @@ -7704,16 +7699,16 @@ static void gen_spr_power6_common(CPUPPCState *env) 0x00000000); } -static void spr_read_tar(void *opaque, int gprn, int sprn) +static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); - spr_read_generic(opaque, gprn, sprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_read_generic(ctx, gprn, sprn); } -static void spr_write_tar(void *opaque, int sprn, int gprn) +static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); - spr_write_generic(opaque, sprn, gprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); + spr_write_generic(ctx, sprn, gprn); } static void gen_spr_power8_tce_address_control(CPUPPCState *env) @@ -7724,28 +7719,28 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env) 0x00000000); } -static void spr_read_tm(void *opaque, int gprn, int sprn) +static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_read_generic(opaque, gprn, sprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_read_generic(ctx, gprn, sprn); } -static void spr_write_tm(void *opaque, int sprn, int gprn) +static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_write_generic(opaque, sprn, gprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_write_generic(ctx, sprn, gprn); } -static void spr_read_tm_upper32(void *opaque, int gprn, int sprn) +static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_read_prev_upper32(opaque, gprn, sprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_read_prev_upper32(ctx, gprn, sprn); } -static void spr_write_tm_upper32(void *opaque, int sprn, int gprn) +static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) { - gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); - spr_write_prev_upper32(opaque, sprn, gprn); + gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); + spr_write_prev_upper32(ctx, sprn, gprn); } static void gen_spr_power8_tm(CPUPPCState *env) @@ -7768,28 +7763,28 @@ static void gen_spr_power8_tm(CPUPPCState *env) 0x00000000); } -static void spr_read_ebb(void *opaque, int gprn, int sprn) +static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_read_generic(opaque, gprn, sprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_generic(ctx, gprn, sprn); } -static void spr_write_ebb(void *opaque, int sprn, int gprn) +static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_write_generic(opaque, sprn, gprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_generic(ctx, sprn, gprn); } -static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn) +static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_read_prev_upper32(opaque, gprn, sprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_prev_upper32(ctx, gprn, sprn); } -static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn) +static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) { - gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); - spr_write_prev_upper32(opaque, sprn, gprn); + gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_prev_upper32(ctx, sprn, gprn); } static void gen_spr_power8_ebb(CPUPPCState *env) @@ -8219,7 +8214,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64; + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_TM) | (1ull << MSR_VR) | @@ -8247,7 +8243,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX; + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; diff --git a/target-s390x/translate.c b/target-s390x/translate.c index dbf1993d46..ab01bc004e 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -4779,7 +4779,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, max_insns = CF_COUNT_MASK; } - gen_tb_start(); + gen_tb_start(tb); do { if (search_pc) { diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 3088edc6a6..7010740b21 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1890,7 +1890,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 78c4e21cff..25d1bd6988 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5271,7 +5271,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) max_insns = CF_COUNT_MASK; - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-tricore/translate.c b/target-tricore/translate.c index dbcf87e383..3b83782be2 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -5077,7 +5077,7 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb, ctx.mem_idx = cpu_mmu_index(env); tcg_clear_temp_count(); - gen_tb_start(); + gen_tb_start(tb); while (ctx.bstate == BS_NONE) { ctx.opcode = cpu_ldl_code(env, ctx.pc); decode_opc(env, &ctx, 0); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 653c225187..ab7e96f937 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1917,7 +1917,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, } #endif - gen_tb_start(); + gen_tb_start(tb); do { if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 65005546d6..9e137fe5ec 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -3054,7 +3054,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu, dc.next_icount = tcg_temp_local_new_i32(); } - gen_tb_start(); + gen_tb_start(tb); if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { tcg_gen_movi_i32(cpu_pc, dc.pc); diff --git a/translate-all.c b/translate-all.c index c24cfe865b..8fa4378055 100644 --- a/translate-all.c +++ b/translate-all.c @@ -218,7 +218,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, gen_intermediate_code_pc(env, tb); - if (use_icount) { + if (tb->cflags & CF_USE_ICOUNT) { /* Reset the cycle counter to the start of the block. */ cpu->icount_decr.u16.low += tb->icount; /* Clear the IO flag. */ @@ -1045,6 +1045,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, int code_gen_size; phys_pc = get_page_addr_code(env, pc); + if (use_icount) { + cflags |= CF_USE_ICOUNT; + } tb = tb_alloc(pc); if (!tb) { /* flush must be done */ |