diff options
| -rw-r--r-- | target/mips/cpu-defs.c.inc | 36 | ||||
| -rw-r--r-- | target/mips/cpu.c | 1 | ||||
| -rw-r--r-- | target/mips/internal.h | 2 | ||||
| -rw-r--r-- | target/mips/msa_helper.c | 36 |
4 files changed, 39 insertions, 36 deletions
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 3d44b39477..ba22ff4bcd 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -18,8 +18,6 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ -#include "fpu_helper.h" - /* CPU / CPU family specific config register values. */ /* Have config1, uncached coherency */ @@ -975,37 +973,3 @@ static void mvp_init(CPUMIPSState *env) (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | (0x1 << CP0MVPC1_PCP1); } - -static void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |= 1 << CP0C5_MSAEn; - env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* MSA CSR: - - non-signaling floating point exception mode off (NX bit is 0) - - Cause, Enables, and Flags are all 0 - - round to nearest / ties to even (RM bits are 0) */ - env->active_tc.msacsr = 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 001b1b88e2..4c4548233c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -33,6 +33,7 @@ #include "hw/qdev-clock.h" #include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" +#include "fpu_helper.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/mips/internal.h b/target/mips/internal.h index 1048781bcf..5dd17ff733 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -199,6 +199,8 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) void mips_tcg_init(void); +void msa_reset(CPUMIPSState *env); + /* cp0_timer.c */ uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index b89b4c4490..f0d728c03f 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -8201,3 +8201,39 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, msa_move_v(pwd, pwx); } + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |= 1 << CP0C5_MSAEn; + env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr = 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} |