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-rw-r--r--accel/tcg/translate-all.c34
-rw-r--r--default-configs/ppc-softmmu.mak1
-rw-r--r--default-configs/ppcemb-softmmu.mak1
-rw-r--r--default-configs/sh4-softmmu.mak2
-rw-r--r--default-configs/sh4eb-softmmu.mak2
-rw-r--r--hw/arm/smmu-common.c2
-rw-r--r--hw/core/ptimer.c22
-rw-r--r--hw/display/sm501.c230
-rw-r--r--hw/net/dp8393x.c2
-rw-r--r--hw/ppc/mac_newworld.c1
-rw-r--r--hw/ppc/mac_oldworld.c1
-rw-r--r--hw/ppc/ppc440_uc.c2
-rw-r--r--hw/ppc/prep.c2
-rw-r--r--hw/ppc/sam460ex.c49
-rw-r--r--hw/ppc/spapr_vio.c15
-rw-r--r--hw/sd/omap_mmc.c14
-rw-r--r--hw/timer/cmsdk-apb-timer.c20
-rw-r--r--include/hw/arm/smmu-common.h1
-rw-r--r--include/hw/boards.h3
-rw-r--r--include/hw/ptimer.h9
-rw-r--r--nbd/server.c5
-rwxr-xr-xpc-bios/u-boot-sam460-20100605.binbin524288 -> 524288 bytes
m---------roms/u-boot-sam460ex0
-rw-r--r--target/arm/translate-sve.c14
-rw-r--r--target/ppc/int_helper.c2
-rw-r--r--tcg/tcg-op-gvec.c7
-rw-r--r--tests/ptimer-test.c25
27 files changed, 370 insertions, 96 deletions
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 170b95793f..49d77fad44 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1446,7 +1446,8 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb_cflags(tb) & CF_HASH_MASK,
tb->trace_vcpu_dstate);
- if (!qht_remove(&tb_ctx.htable, tb, h)) {
+ if (!(tb->cflags & CF_NOCACHE) &&
+ !qht_remove(&tb_ctx.htable, tb, h)) {
return;
}
@@ -1604,8 +1605,6 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
{
PageDesc *p;
PageDesc *p2 = NULL;
- void *existing_tb = NULL;
- uint32_t h;
assert_memory_lock();
@@ -1625,20 +1624,25 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
tb->page_addr[1] = -1;
}
- /* add in the hash table */
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
- tb->trace_vcpu_dstate);
- qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
+ if (!(tb->cflags & CF_NOCACHE)) {
+ void *existing_tb = NULL;
+ uint32_t h;
- /* remove TB from the page(s) if we couldn't insert it */
- if (unlikely(existing_tb)) {
- tb_page_remove(p, tb);
- invalidate_page_bitmap(p);
- if (p2) {
- tb_page_remove(p2, tb);
- invalidate_page_bitmap(p2);
+ /* add in the hash table */
+ h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK,
+ tb->trace_vcpu_dstate);
+ qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
+
+ /* remove TB from the page(s) if we couldn't insert it */
+ if (unlikely(existing_tb)) {
+ tb_page_remove(p, tb);
+ invalidate_page_bitmap(p);
+ if (p2) {
+ tb_page_remove(p2, tb);
+ invalidate_page_bitmap(p2);
+ }
+ tb = existing_tb;
}
- tb = existing_tb;
}
if (p2 && p2 != p) {
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index 6f12bf84f0..3181bbf163 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -25,6 +25,7 @@ CONFIG_ETSEC=y
CONFIG_SAM460EX=y
CONFIG_USB_EHCI_SYSBUS=y
CONFIG_SM501=y
+CONFIG_DDC=y
CONFIG_IDE_SII3112=y
CONFIG_I2C=y
CONFIG_BITBANG_I2C=y
diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-softmmu.mak
index 37af1930b3..ac44f150c6 100644
--- a/default-configs/ppcemb-softmmu.mak
+++ b/default-configs/ppcemb-softmmu.mak
@@ -17,6 +17,7 @@ CONFIG_XILINX=y
CONFIG_XILINX_ETHLITE=y
CONFIG_USB_EHCI_SYSBUS=y
CONFIG_SM501=y
+CONFIG_DDC=y
CONFIG_IDE_SII3112=y
CONFIG_I2C=y
CONFIG_BITBANG_I2C=y
diff --git a/default-configs/sh4-softmmu.mak b/default-configs/sh4-softmmu.mak
index 546d855088..caeccd55be 100644
--- a/default-configs/sh4-softmmu.mak
+++ b/default-configs/sh4-softmmu.mak
@@ -9,6 +9,8 @@ CONFIG_PFLASH_CFI02=y
CONFIG_SH4=y
CONFIG_IDE_MMIO=y
CONFIG_SM501=y
+CONFIG_I2C=y
+CONFIG_DDC=y
CONFIG_ISA_TESTDEV=y
CONFIG_I82378=y
CONFIG_I8259=y
diff --git a/default-configs/sh4eb-softmmu.mak b/default-configs/sh4eb-softmmu.mak
index 2d3fd49663..53b9cd7b5a 100644
--- a/default-configs/sh4eb-softmmu.mak
+++ b/default-configs/sh4eb-softmmu.mak
@@ -9,6 +9,8 @@ CONFIG_PFLASH_CFI02=y
CONFIG_SH4=y
CONFIG_IDE_MMIO=y
CONFIG_SM501=y
+CONFIG_I2C=y
+CONFIG_DDC=y
CONFIG_ISA_TESTDEV=y
CONFIG_I82378=y
CONFIG_I8259=y
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 3098915d07..55c75d65d2 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -351,7 +351,7 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
bus_n = PCI_BUS_NUM(sid);
smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
if (smmu_bus) {
- devfn = sid & 0x7;
+ devfn = SMMU_PCI_DEVFN(sid);
smmu = smmu_bus->pbdev[devfn];
if (smmu) {
return &smmu->iommu;
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
index 7221c68a98..170fd34d8b 100644
--- a/hw/core/ptimer.c
+++ b/hw/core/ptimer.c
@@ -45,8 +45,20 @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
uint32_t period_frac = s->period_frac;
uint64_t period = s->period;
uint64_t delta = s->delta;
+ bool suppress_trigger = false;
- if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
+ /*
+ * Note that if delta_adjust is 0 then we must be here because of
+ * a count register write or timer start, not because of timer expiry.
+ * In that case the policy might require us to suppress the timer trigger
+ * that we would otherwise generate for a zero delta.
+ */
+ if (delta_adjust == 0 &&
+ (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) {
+ suppress_trigger = true;
+ }
+ if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)
+ && !suppress_trigger) {
ptimer_trigger(s);
}
@@ -353,6 +365,14 @@ ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask)
s->bh = bh;
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
s->policy_mask = policy_mask;
+
+ /*
+ * These two policies are incompatible -- trigger-on-decrement implies
+ * a timer trigger when the count becomes 0, but no-immediate-trigger
+ * implies a trigger when the count stops being 0.
+ */
+ assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
+ (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
return s;
}
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 9dec0d3218..3661a89f60 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
+#include "qemu/log.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
@@ -34,6 +35,8 @@
#include "hw/devices.h"
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
+#include "hw/i2c/i2c.h"
+#include "hw/i2c/i2c-ddc.h"
#include "qemu/range.h"
#include "ui/pixel_ops.h"
@@ -216,6 +219,14 @@
#define SM501_I2C_SLAVE_ADDRESS (0x03)
#define SM501_I2C_DATA (0x04)
+#define SM501_I2C_CONTROL_START (1 << 2)
+#define SM501_I2C_CONTROL_ENABLE (1 << 0)
+
+#define SM501_I2C_STATUS_COMPLETE (1 << 3)
+#define SM501_I2C_STATUS_ERROR (1 << 2)
+
+#define SM501_I2C_RESET_ERROR (1 << 2)
+
/* SSP base */
#define SM501_SSP (0x020000)
@@ -471,10 +482,13 @@ typedef struct SM501State {
MemoryRegion local_mem_region;
MemoryRegion mmio_region;
MemoryRegion system_config_region;
+ MemoryRegion i2c_region;
MemoryRegion disp_ctrl_region;
MemoryRegion twoD_engine_region;
uint32_t last_width;
uint32_t last_height;
+ bool do_full_update; /* perform a full update next time */
+ I2CBus *i2c_bus;
/* mmio registers */
uint32_t system_control;
@@ -487,6 +501,11 @@ typedef struct SM501State {
uint32_t misc_timing;
uint32_t power_mode_control;
+ uint8_t i2c_byte_count;
+ uint8_t i2c_status;
+ uint8_t i2c_addr;
+ uint8_t i2c_data[16];
+
uint32_t uart0_ier;
uint32_t uart0_lcr;
uint32_t uart0_mcr;
@@ -567,6 +586,11 @@ static uint32_t get_local_mem_size_index(uint32_t size)
return index;
}
+static ram_addr_t get_fb_addr(SM501State *s, int crt)
+{
+ return (crt ? s->dc_crt_fb_addr : s->dc_panel_fb_addr) & 0x3FFFFF0;
+}
+
static inline int get_width(SM501State *s, int crt)
{
int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total;
@@ -669,7 +693,8 @@ static inline void hwc_invalidate(SM501State *s, int crt)
start *= w * bpp;
end *= w * bpp;
- memory_region_set_dirty(&s->local_mem_region, start, end - start);
+ memory_region_set_dirty(&s->local_mem_region,
+ get_fb_addr(s, crt) + start, end - start);
}
static void sm501_2d_operation(SM501State *s)
@@ -686,18 +711,47 @@ static void sm501_2d_operation(SM501State *s)
uint32_t color = s->twoD_foreground;
int format_flags = (s->twoD_stretch >> 20) & 0x3;
int addressing = (s->twoD_stretch >> 16) & 0xF;
+ int rop_mode = (s->twoD_control >> 15) & 0x1; /* 1 for rop2, else rop3 */
+ /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */
+ int rop2_source_is_pattern = (s->twoD_control >> 14) & 0x1;
+ int rop = s->twoD_control & 0xFF;
+ uint32_t src_base = s->twoD_source_base & 0x03FFFFFF;
+ uint32_t dst_base = s->twoD_destination_base & 0x03FFFFFF;
/* get frame buffer info */
- uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
- uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
- int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
- int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
+ uint8_t *src = s->local_mem + src_base;
+ uint8_t *dst = s->local_mem + dst_base;
+ int src_width = s->twoD_pitch & 0x1FFF;
+ int dst_width = (s->twoD_pitch >> 16) & 0x1FFF;
+ int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
+ int fb_len = get_width(s, crt) * get_height(s, crt) * get_bpp(s, crt);
if (addressing != 0x0) {
printf("%s: only XY addressing is supported.\n", __func__);
abort();
}
+ if (rop_mode == 0) {
+ if (rop != 0xcc) {
+ /* Anything other than plain copies are not supported */
+ qemu_log_mask(LOG_UNIMP, "sm501: rop3 mode with rop %x is not "
+ "supported.\n", rop);
+ }
+ } else {
+ if (rop2_source_is_pattern && rop != 0x5) {
+ /* For pattern source, we support only inverse dest */
+ qemu_log_mask(LOG_UNIMP, "sm501: rop2 source being the pattern and "
+ "rop %x is not supported.\n", rop);
+ } else {
+ if (rop != 0x5 && rop != 0xc) {
+ /* Anything other than plain copies or inverse dest is not
+ * supported */
+ qemu_log_mask(LOG_UNIMP, "sm501: rop mode %x is not "
+ "supported.\n", rop);
+ }
+ }
+ }
+
if ((s->twoD_source_base & 0x08000000) ||
(s->twoD_destination_base & 0x08000000)) {
printf("%s: only local memory is supported.\n", __func__);
@@ -710,6 +764,8 @@ static void sm501_2d_operation(SM501State *s)
int y, x, index_d, index_s; \
for (y = 0; y < operation_height; y++) { \
for (x = 0; x < operation_width; x++) { \
+ _pixel_type val; \
+ \
if (rtl) { \
index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
@@ -717,7 +773,13 @@ static void sm501_2d_operation(SM501State *s)
index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
} \
- *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\
+ if (rop_mode == 1 && rop == 5) { \
+ /* Invert dest */ \
+ val = ~*(_pixel_type *)&dst[index_d]; \
+ } else { \
+ val = *(_pixel_type *)&src[index_s]; \
+ } \
+ *(_pixel_type *)&dst[index_d] = val; \
} \
} \
}
@@ -763,6 +825,15 @@ static void sm501_2d_operation(SM501State *s)
abort();
break;
}
+
+ if (dst_base >= get_fb_addr(s, crt) &&
+ dst_base <= get_fb_addr(s, crt) + fb_len) {
+ int dst_len = MIN(fb_len, ((dst_y + operation_height - 1) * dst_width +
+ dst_x + operation_width) * (1 << format_flags));
+ if (dst_len) {
+ memory_region_set_dirty(&s->local_mem_region, dst_base, dst_len);
+ }
+ }
}
static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
@@ -897,6 +968,109 @@ static const MemoryRegionOps sm501_system_config_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
+static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size)
+{
+ SM501State *s = (SM501State *)opaque;
+ uint8_t ret = 0;
+
+ switch (addr) {
+ case SM501_I2C_BYTE_COUNT:
+ ret = s->i2c_byte_count;
+ break;
+ case SM501_I2C_STATUS:
+ ret = s->i2c_status;
+ break;
+ case SM501_I2C_SLAVE_ADDRESS:
+ ret = s->i2c_addr;
+ break;
+ case SM501_I2C_DATA ... SM501_I2C_DATA + 15:
+ ret = s->i2c_data[addr - SM501_I2C_DATA];
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register read."
+ " addr=0x%" HWADDR_PRIx "\n", addr);
+ }
+
+ SM501_DPRINTF("sm501 i2c regs : read addr=%" HWADDR_PRIx " val=%x\n",
+ addr, ret);
+ return ret;
+}
+
+static void sm501_i2c_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ SM501State *s = (SM501State *)opaque;
+ SM501_DPRINTF("sm501 i2c regs : write addr=%" HWADDR_PRIx
+ " val=%" PRIx64 "\n", addr, value);
+
+ switch (addr) {
+ case SM501_I2C_BYTE_COUNT:
+ s->i2c_byte_count = value & 0xf;
+ break;
+ case SM501_I2C_CONTROL:
+ if (value & SM501_I2C_CONTROL_ENABLE) {
+ if (value & SM501_I2C_CONTROL_START) {
+ int res = i2c_start_transfer(s->i2c_bus,
+ s->i2c_addr >> 1,
+ s->i2c_addr & 1);
+ s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0);
+ if (!res) {
+ int i;
+ SM501_DPRINTF("sm501 i2c : transferring %d bytes to 0x%x\n",
+ s->i2c_byte_count + 1, s->i2c_addr >> 1);
+ for (i = 0; i <= s->i2c_byte_count; i++) {
+ res = i2c_send_recv(s->i2c_bus, &s->i2c_data[i],
+ !(s->i2c_addr & 1));
+ if (res) {
+ SM501_DPRINTF("sm501 i2c : transfer failed"
+ " i=%d, res=%d\n", i, res);
+ s->i2c_status |= (res ? SM501_I2C_STATUS_ERROR : 0);
+ return;
+ }
+ }
+ if (i) {
+ SM501_DPRINTF("sm501 i2c : transferred %d bytes\n", i);
+ s->i2c_status = SM501_I2C_STATUS_COMPLETE;
+ }
+ }
+ } else {
+ SM501_DPRINTF("sm501 i2c : end transfer\n");
+ i2c_end_transfer(s->i2c_bus);
+ s->i2c_status &= ~SM501_I2C_STATUS_ERROR;
+ }
+ }
+ break;
+ case SM501_I2C_RESET:
+ if ((value & SM501_I2C_RESET_ERROR) == 0) {
+ s->i2c_status &= ~SM501_I2C_STATUS_ERROR;
+ }
+ break;
+ case SM501_I2C_SLAVE_ADDRESS:
+ s->i2c_addr = value & 0xff;
+ break;
+ case SM501_I2C_DATA ... SM501_I2C_DATA + 15:
+ s->i2c_data[addr - SM501_I2C_DATA] = value & 0xff;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "sm501 i2c : not implemented register write. "
+ "addr=0x%" HWADDR_PRIx " val=%" PRIx64 "\n", addr, value);
+ }
+}
+
+static const MemoryRegionOps sm501_i2c_ops = {
+ .read = sm501_i2c_read,
+ .write = sm501_i2c_write,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
{
SM501State *s = (SM501State *)opaque;
@@ -921,6 +1095,7 @@ static void sm501_palette_write(void *opaque, hwaddr addr,
assert(range_covers_byte(0, 0x400 * 3, addr));
*(uint32_t *)&s->dc_palette[addr] = value;
+ s->do_full_update = true;
}
static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
@@ -1057,6 +1232,9 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
break;
case SM501_DC_PANEL_FB_ADDR:
s->dc_panel_fb_addr = value & 0x8FFFFFF0;
+ if (value & 0x8000000) {
+ qemu_log_mask(LOG_UNIMP, "Panel external memory not supported\n");
+ }
break;
case SM501_DC_PANEL_FB_OFFSET:
s->dc_panel_fb_offset = value & 0x3FF03FF0;
@@ -1117,6 +1295,9 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
break;
case SM501_DC_CRT_FB_ADDR:
s->dc_crt_fb_addr = value & 0x8FFFFFF0;
+ if (value & 0x8000000) {
+ qemu_log_mask(LOG_UNIMP, "CRT external memory not supported\n");
+ }
break;
case SM501_DC_CRT_FB_OFFSET:
s->dc_crt_fb_offset = value & 0x3FF03FF0;
@@ -1459,7 +1640,7 @@ static void sm501_update_display(void *opaque)
draw_hwc_line_func *draw_hwc_line = NULL;
int full_update = 0;
int y_start = -1;
- ram_addr_t offset = 0;
+ ram_addr_t offset;
uint32_t *palette;
uint8_t hwc_palette[3 * 3];
uint8_t *hwc_src = NULL;
@@ -1509,10 +1690,17 @@ static void sm501_update_display(void *opaque)
full_update = 1;
}
+ /* someone else requested a full update */
+ if (s->do_full_update) {
+ s->do_full_update = false;
+ full_update = 1;
+ }
+
/* draw each line according to conditions */
+ offset = get_fb_addr(s, crt);
snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region,
offset, width * height * src_bpp, DIRTY_MEMORY_VGA);
- for (y = 0, offset = 0; y < height; y++, offset += width * src_bpp) {
+ for (y = 0; y < height; y++, offset += width * src_bpp) {
int update, update_hwc;
/* check if hardware cursor is enabled and we're within its range */
@@ -1577,6 +1765,10 @@ static void sm501_reset(SM501State *s)
s->irq_mask = 0;
s->misc_timing = 0;
s->power_mode_control = 0;
+ s->i2c_byte_count = 0;
+ s->i2c_status = 0;
+ s->i2c_addr = 0;
+ memset(s->i2c_data, 0, 16);
s->dc_panel_control = 0x00010000; /* FIFO level 3 */
s->dc_video_control = 0;
s->dc_crt_control = 0x00010000;
@@ -1615,6 +1807,12 @@ static void sm501_init(SM501State *s, DeviceState *dev,
memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
+ /* i2c */
+ s->i2c_bus = i2c_init_bus(dev, "sm501.i2c");
+ /* ddc */
+ I2CDDCState *ddc = I2CDDC(qdev_create(BUS(s->i2c_bus), TYPE_I2CDDC));
+ i2c_set_slave_address(I2C_SLAVE(ddc), 0x50);
+
/* mmio */
memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
memory_region_init_io(&s->system_config_region, OBJECT(dev),
@@ -1622,6 +1820,9 @@ static void sm501_init(SM501State *s, DeviceState *dev,
"sm501-system-config", 0x6c);
memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG,
&s->system_config_region);
+ memory_region_init_io(&s->i2c_region, OBJECT(dev), &sm501_i2c_ops, s,
+ "sm501-i2c", 0x14);
+ memory_region_add_subregion(&s->mmio_region, SM501_I2C, &s->i2c_region);
memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev),
&sm501_disp_ctrl_ops, s,
"sm501-disp-ctrl", 0x1000);
@@ -1705,6 +1906,11 @@ static const VMStateDescription vmstate_sm501_state = {
VMSTATE_UINT32(twoD_destination_base, SM501State),
VMSTATE_UINT32(twoD_alpha, SM501State),
VMSTATE_UINT32(twoD_wrap, SM501State),
+ /* Added in version 2 */
+ VMSTATE_UINT8(i2c_byte_count, SM501State),
+ VMSTATE_UINT8(i2c_status, SM501State),
+ VMSTATE_UINT8(i2c_addr, SM501State),
+ VMSTATE_UINT8_ARRAY(i2c_data, SM501State, 16),
VMSTATE_END_OF_LIST()
}
};
@@ -1770,8 +1976,8 @@ static void sm501_reset_sysbus(DeviceState *dev)
static const VMStateDescription vmstate_sm501_sysbus = {
.name = TYPE_SYSBUS_SM501,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(state, SM501SysBusState, 1,
vmstate_sm501_state, SM501State),
@@ -1843,8 +2049,8 @@ static void sm501_reset_pci(DeviceState *dev)
static const VMStateDescription vmstate_sm501_pci = {
.name = TYPE_PCI_SM501,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState),
VMSTATE_STRUCT(state, SM501PCIState, 1,
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index f2d2ce344c..b53fcaa8bc 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -887,7 +887,7 @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
- memory_region_init_ram_nomigrate(&s->prom, OBJECT(dev),
+ memory_region_init_ram(&s->prom, OBJECT(dev),
"dp8393x-prom", SONIC_PROM_SIZE, &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index d11980166f..2ca294664b 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -525,6 +525,7 @@ static void core99_machine_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_IDE;
mc->max_cpus = MAX_CPUS;
mc->default_boot_order = "cd";
+ mc->default_display = "std";
mc->kvm_type = core99_kvm_type;
#ifdef TARGET_PPC64
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1");
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 06ed6f660e..064d7eb30a 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -383,6 +383,7 @@ static void heathrow_class_init(ObjectClass *oc, void *data)
mc->default_boot_order = "cd";
mc->kvm_type = heathrow_kvm_type;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
+ mc->default_display = "std";
}
static const TypeInfo ppc_heathrow_machine_info = {
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 0bbaa6844a..09ccda548f 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -935,7 +935,7 @@ static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
if (wptr) {
cpu_physical_memory_unmap(wptr, wlen, 1, didx);
}
- if (wptr) {
+ if (rptr) {
cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
}
}
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 6689407b3d..3401570d98 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -682,6 +682,7 @@ static void prep_machine_init(MachineClass *mc)
mc->max_cpus = MAX_CPUS;
mc->default_boot_order = "cad";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
+ mc->default_display = "std";
}
static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
@@ -888,6 +889,7 @@ static void ibm_40p_machine_init(MachineClass *mc)
mc->block_default_type = IF_SCSI;
mc->default_boot_order = "c";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
+ mc->default_display = "std";
}
DEFINE_MACHINE("40p", ibm_40p_machine_init)
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 7eed2ec601..e2b7028843 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -36,6 +36,7 @@
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/i2c/smbus.h"
#include "hw/usb/hcd-ehci.h"
+#include "hw/ppc/fdt.h"
#include <libfdt.h>
@@ -254,7 +255,6 @@ static int sam460ex_load_device_tree(hwaddr addr,
hwaddr initrd_size,
const char *kernel_cmdline)
{
- int ret = -1;
uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
char *filename;
int fdt_size;
@@ -265,42 +265,30 @@ static int sam460ex_load_device_tree(hwaddr addr,
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
if (!filename) {
- goto out;
+ error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE);
+ exit(1);
}
fdt = load_device_tree(filename, &fdt_size);
g_free(filename);
- if (fdt == NULL) {
- goto out;
+ if (!fdt) {
+ error_report("Couldn't load dtb file `%s'", filename);
+ exit(1);
}
/* Manipulate device tree in memory. */
- ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
- sizeof(mem_reg_property));
- if (ret < 0) {
- error_report("couldn't set /memory/reg");
- }
+ qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
+ sizeof(mem_reg_property));
/* default FDT doesn't have a /chosen node... */
qemu_fdt_add_subnode(fdt, "/chosen");
- ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
- initrd_base);
- if (ret < 0) {
- error_report("couldn't set /chosen/linux,initrd-start");
- }
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base);
- ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
- (initrd_base + initrd_size));
- if (ret < 0) {
- error_report("couldn't set /chosen/linux,initrd-end");
- }
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+ (initrd_base + initrd_size));
- ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
- kernel_cmdline);
- if (ret < 0) {
- error_report("couldn't set /chosen/bootargs");
- }
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
/* Copy data from the host device tree into the guest. Since the guest can
* directly access the timebase without host involvement, we must expose
@@ -318,13 +306,13 @@ static int sam460ex_load_device_tree(hwaddr addr,
/* Remove cpm node if it exists (it is not emulated) */
offset = fdt_path_offset(fdt, "/cpm");
if (offset >= 0) {
- fdt_nop_node(fdt, offset);
+ _FDT(fdt_nop_node(fdt, offset));
}
/* set serial port clocks */
offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
while (offset >= 0) {
- fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ);
+ _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ));
offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
}
@@ -338,11 +326,8 @@ static int sam460ex_load_device_tree(hwaddr addr,
rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
g_free(fdt);
- ret = fdt_size;
-
-out:
- return ret;
+ return fdt_size;
}
/* Create reset TLB entries for BookE, mapping only the flash memory. */
@@ -612,10 +597,6 @@ static void sam460ex_init(MachineState *machine)
dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
RAMDISK_ADDR, initrd_size,
machine->kernel_cmdline);
- if (dt_size < 0) {
- error_report("couldn't load device tree");
- exit(1);
- }
boot_info->dt_base = FDT_ADDR;
boot_info->dt_size = dt_size;
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index daf85130b5..be9af71437 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -43,7 +43,16 @@
#include <libfdt.h>
-static void spapr_vio_getset_irq(Object *obj, Visitor *v, const char *name,
+static void spapr_vio_get_irq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ Property *prop = opaque;
+ uint32_t *ptr = qdev_get_prop_ptr(DEVICE(obj), prop);
+
+ visit_type_uint32(v, name, ptr, errp);
+}
+
+static void spapr_vio_set_irq(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
Property *prop = opaque;
@@ -57,8 +66,8 @@ static void spapr_vio_getset_irq(Object *obj, Visitor *v, const char *name,
static const PropertyInfo spapr_vio_irq_propinfo = {
.name = "irq",
- .get = spapr_vio_getset_irq,
- .set = spapr_vio_getset_irq,
+ .get = spapr_vio_get_irq,
+ .set = spapr_vio_set_irq,
};
static Property spapr_vio_props[] = {
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
index 671264b650..d0c98ca021 100644
--- a/hw/sd/omap_mmc.c
+++ b/hw/sd/omap_mmc.c
@@ -1,6 +1,8 @@
/*
* OMAP on-chip MMC/SD host emulation.
*
+ * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
+ *
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
*
* This program is free software; you can redistribute it and/or
@@ -278,6 +280,12 @@ static void omap_mmc_update(void *opaque)
omap_mmc_interrupts_update(s);
}
+static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
+{
+ host->status = 0;
+ host->fifo_len = 0;
+}
+
void omap_mmc_reset(struct omap_mmc_s *host)
{
host->last_cmd = 0;
@@ -286,11 +294,9 @@ void omap_mmc_reset(struct omap_mmc_s *host)
host->dw = 0;
host->mode = 0;
host->enable = 0;
- host->status = 0;
host->mask = 0;
host->cto = 0;
host->dto = 0;
- host->fifo_len = 0;
host->blen = 0;
host->blen_counter = 0;
host->nblk = 0;
@@ -305,6 +311,8 @@ void omap_mmc_reset(struct omap_mmc_s *host)
qemu_set_irq(host->coverswitch, host->cdet_state);
host->clkdiv = 0;
+ omap_mmc_pseudo_reset(host);
+
/* Since we're still using the legacy SD API the card is not plugged
* into any bus, and we must reset it manually. When omap_mmc is
* QOMified this must move into the QOM reset function.
@@ -459,7 +467,7 @@ static void omap_mmc_write(void *opaque, hwaddr offset,
if (s->dw != 0 && s->lines < 4)
printf("4-bit SD bus enabled\n");
if (!s->enable)
- omap_mmc_reset(s);
+ omap_mmc_pseudo_reset(s);
break;
case 0x10: /* MMC_STAT */
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
index 9878746609..801d1dba74 100644
--- a/hw/timer/cmsdk-apb-timer.c
+++ b/hw/timer/cmsdk-apb-timer.c
@@ -119,17 +119,33 @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
}
s->ctrl = value & 0xf;
if (s->ctrl & R_CTRL_EN_MASK) {
- ptimer_run(s->timer, 0);
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
} else {
ptimer_stop(s->timer);
}
break;
case A_RELOAD:
/* Writing to reload also sets the current timer value */
+ if (!value) {
+ ptimer_stop(s->timer);
+ }
ptimer_set_limit(s->timer, value, 1);
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
+ /*
+ * Make sure timer is running (it might have stopped if this
+ * was an expired one-shot timer)
+ */
+ ptimer_run(s->timer, 0);
+ }
break;
case A_VALUE:
+ if (!value && !ptimer_get_limit(s->timer)) {
+ ptimer_stop(s->timer);
+ }
ptimer_set_count(s->timer, value);
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
+ }
break;
case A_INTSTATUS:
/* Just one bit, which is W1C. */
@@ -201,7 +217,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
s->timer = ptimer_init(bh,
PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
- PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
+ PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 50e2912a95..b07cadd0ef 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -24,6 +24,7 @@
#define SMMU_PCI_BUS_MAX 256
#define SMMU_PCI_DEVFN_MAX 256
+#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
#define SMMU_MAX_VA_BITS 48
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 79069ddcbe..d139a431a6 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -35,8 +35,7 @@
*
* Smaller pieces of memory (display RAM, static RAMs, etc) don't need
* to be backed via the -mem-path memory backend and can simply
- * be created via memory_region_allocate_aux_memory() or
- * memory_region_init_ram().
+ * be created via memory_region_init_ram().
*/
void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
const char *name,
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
index fc4ef5cc1d..0731d9aef1 100644
--- a/include/hw/ptimer.h
+++ b/include/hw/ptimer.h
@@ -69,6 +69,15 @@
* not the one less. */
#define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4)
+/*
+ * Starting to run with a zero counter, or setting the counter to "0" via
+ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer
+ * (though it will cause a reload). Only a counter decrement to "0"
+ * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
+ * ptimer_init() will assert() that you don't set both.
+ */
+#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
+
/* ptimer.c */
typedef struct ptimer_state ptimer_state;
typedef void (*ptimer_cb)(void *opaque);
diff --git a/nbd/server.c b/nbd/server.c
index e52b76bd1a..ea5fe0eb33 100644
--- a/nbd/server.c
+++ b/nbd/server.c
@@ -1910,7 +1910,7 @@ static int nbd_co_send_extents(NBDClient *client, uint64_t handle,
/* Get block status from the exported device and send it to the client */
static int nbd_co_send_block_status(NBDClient *client, uint64_t handle,
BlockDriverState *bs, uint64_t offset,
- uint64_t length, bool last,
+ uint32_t length, bool last,
uint32_t context_id, Error **errp)
{
int ret;
@@ -1922,7 +1922,8 @@ static int nbd_co_send_block_status(NBDClient *client, uint64_t handle,
client, handle, -ret, "can't get block status", errp);
}
- return nbd_co_send_extents(client, handle, &extent, 1, length, last,
+ return nbd_co_send_extents(client, handle, &extent, 1,
+ be32_to_cpu(extent.length), last,
context_id, errp);
}
diff --git a/pc-bios/u-boot-sam460-20100605.bin b/pc-bios/u-boot-sam460-20100605.bin
index 99408f8e95..e17de77c19 100755
--- a/pc-bios/u-boot-sam460-20100605.bin
+++ b/pc-bios/u-boot-sam460-20100605.bin
Binary files differ
diff --git a/roms/u-boot-sam460ex b/roms/u-boot-sam460ex
-Subproject 8ee007c4216fd6a0d760589e8405ce4494497aa
+Subproject 60b3916f33e617a815973c5a6df77055b2e3a58
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index c080345b9c..374051cd20 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1438,7 +1438,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
setsz = numelem << esz;
lastword = word = pred_esz_masks[esz];
if (setsz % 64) {
- lastword &= ~(-1ull << (setsz % 64));
+ lastword &= MAKE_64BIT_MASK(0, setsz % 64);
}
}
@@ -1457,19 +1457,13 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
goto done;
}
- if (oprsz * 8 == setsz + 8) {
- tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
- tcg_gen_movi_i64(t, 0);
- tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
- goto done;
- }
}
setsz /= 8;
fullsz /= 8;
tcg_gen_movi_i64(t, word);
- for (i = 0; i < setsz; i += 8) {
+ for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
tcg_gen_st_i64(t, cpu_env, ofs + i);
}
if (lastword != word) {
@@ -5164,7 +5158,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
{
/* Prefetch is a nop within QEMU. */
- sve_access_check(s);
+ (void)sve_access_check(s);
return true;
}
@@ -5174,7 +5168,7 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
return false;
}
/* Prefetch is a nop within QEMU. */
- sve_access_check(s);
+ (void)sve_access_check(s);
return true;
}
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 03d37da79f..d52338ed71 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1951,7 +1951,7 @@ VSPLT(w, u32)
#define VINSERT(suffix, element) \
void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
{ \
- memmove(&r->u8[index], &b->u8[8 - sizeof(r->element)], \
+ memmove(&r->u8[index], &b->u8[8 - sizeof(r->element[0])], \
sizeof(r->element[0])); \
}
#else
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 22db1590d5..61c25f5784 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -287,8 +287,11 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
in units of LNSZ. This limits the expansion of inline code. */
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
{
- uint32_t lnct = oprsz / lnsz;
- return lnct >= 1 && lnct <= MAX_UNROLL;
+ if (oprsz % lnsz == 0) {
+ uint32_t lnct = oprsz / lnsz;
+ return lnct >= 1 && lnct <= MAX_UNROLL;
+ }
+ return false;
}
static void expand_clr(uint32_t dofs, uint32_t maxsz);
diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c
index 41488896f7..b30aad0737 100644
--- a/tests/ptimer-test.c
+++ b/tests/ptimer-test.c
@@ -208,6 +208,7 @@ static void check_periodic(gconstpointer arg)
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
triggered = false;
@@ -311,7 +312,7 @@ static void check_periodic(gconstpointer arg)
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
no_immediate_reload ? 0 : 10);
- if (no_immediate_trigger) {
+ if (no_immediate_trigger || trig_only_on_dec) {
g_assert_false(triggered);
} else {
g_assert_true(triggered);
@@ -506,6 +507,7 @@ static void check_run_with_delta_0(gconstpointer arg)
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
triggered = false;
@@ -515,7 +517,7 @@ static void check_run_with_delta_0(gconstpointer arg)
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
no_immediate_reload ? 0 : 99);
- if (no_immediate_trigger) {
+ if (no_immediate_trigger || trig_only_on_dec) {
g_assert_false(triggered);
} else {
g_assert_true(triggered);
@@ -563,7 +565,7 @@ static void check_run_with_delta_0(gconstpointer arg)
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
no_immediate_reload ? 0 : 99);
- if (no_immediate_trigger) {
+ if (no_immediate_trigger || trig_only_on_dec) {
g_assert_false(triggered);
} else {
g_assert_true(triggered);
@@ -609,6 +611,7 @@ static void check_periodic_with_load_0(gconstpointer arg)
ptimer_state *ptimer = ptimer_init(bh, *policy);
bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER);
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
triggered = false;
@@ -617,7 +620,7 @@ static void check_periodic_with_load_0(gconstpointer arg)
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
- if (no_immediate_trigger) {
+ if (no_immediate_trigger || trig_only_on_dec) {
g_assert_false(triggered);
} else {
g_assert_true(triggered);
@@ -667,6 +670,7 @@ static void check_oneshot_with_load_0(gconstpointer arg)
QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL);
ptimer_state *ptimer = ptimer_init(bh, *policy);
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
triggered = false;
@@ -675,7 +679,7 @@ static void check_oneshot_with_load_0(gconstpointer arg)
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
- if (no_immediate_trigger) {
+ if (no_immediate_trigger || trig_only_on_dec) {
g_assert_false(triggered);
} else {
g_assert_true(triggered);
@@ -725,6 +729,10 @@ static void add_ptimer_tests(uint8_t policy)
g_strlcat(policy_name, "no_counter_rounddown,", 256);
}
+ if (policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) {
+ g_strlcat(policy_name, "trigger_only_on_decrement,", 256);
+ }
+
g_test_add_data_func_full(
tmp = g_strdup_printf("/ptimer/set_count policy=%s", policy_name),
g_memdup(&policy, 1), check_set_count, g_free);
@@ -790,10 +798,15 @@ static void add_ptimer_tests(uint8_t policy)
static void add_all_ptimer_policies_comb_tests(void)
{
- int last_policy = PTIMER_POLICY_NO_COUNTER_ROUND_DOWN;
+ int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT;
int policy = PTIMER_POLICY_DEFAULT;
for (; policy < (last_policy << 1); policy++) {
+ if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
+ (policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
+ /* Incompatible policy flag settings -- don't try to test them */
+ continue;
+ }
add_ptimer_tests(policy);
}
}
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-25 13:37:16 +0200