diff options
| -rw-r--r-- | target/mips/translate.c | 18 | ||||
| -rw-r--r-- | target/mips/translate.h | 4 |
2 files changed, 22 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 5228e04084..a303c36be3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2291,6 +2291,24 @@ void gen_store_gpr(TCGv t, int reg) } } +#if defined(TARGET_MIPS64) +void gen_load_gpr_hi(TCGv_i64 t, int reg) +{ + if (reg == 0) { + tcg_gen_movi_i64(t, 0); + } else { + tcg_gen_mov_i64(t, cpu_gpr_hi[reg]); + } +} + +void gen_store_gpr_hi(TCGv_i64 t, int reg) +{ + if (reg != 0) { + tcg_gen_mov_i64(cpu_gpr_hi[reg], t); + } +} +#endif /* TARGET_MIPS64 */ + /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr(int from, int to) { diff --git a/target/mips/translate.h b/target/mips/translate.h index 3014c20cad..468e29d757 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -131,6 +131,10 @@ void gen_move_low32(TCGv ret, TCGv_i64 arg); void gen_move_high32(TCGv ret, TCGv_i64 arg); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); +#if defined(TARGET_MIPS64) +void gen_load_gpr_hi(TCGv_i64 t, int reg); +void gen_store_gpr_hi(TCGv_i64 t, int reg); +#endif /* TARGET_MIPS64 */ void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); |