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-rw-r--r--MAINTAINERS1
-rw-r--r--VERSION2
-rw-r--r--hw/arm/virt.c16
-rw-r--r--hw/block/nvme-dif.c10
-rw-r--r--hw/block/nvme-dif.h10
-rw-r--r--hw/block/nvme-ns.c78
-rw-r--r--hw/block/nvme-ns.h12
-rw-r--r--hw/block/nvme-subsys.c28
-rw-r--r--hw/block/nvme-subsys.h11
-rw-r--r--hw/block/nvme.c142
-rw-r--r--hw/block/nvme.h41
-rw-r--r--hw/block/trace-events1
-rw-r--r--hw/core/machine.c22
-rw-r--r--hw/pci/pcie.c10
-rw-r--r--hw/ppc/e500plat.c8
-rw-r--r--hw/virtio/virtio-pci.c5
-rw-r--r--hw/virtio/virtio-pci.h5
-rw-r--r--include/block/nvme.h1
-rw-r--r--include/hw/boards.h39
-rw-r--r--include/hw/i386/x86.h4
-rw-r--r--include/hw/pci/pcie.h2
-rw-r--r--target/arm/cpu.h1
-rw-r--r--target/arm/cpu64.c3
-rw-r--r--target/arm/cpu_tcg.c5
-rw-r--r--target/arm/helper.c29
-rw-r--r--target/arm/kvm64.c2
-rw-r--r--tests/qtest/bios-tables-test.c2
27 files changed, 259 insertions, 231 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 69003cdc3c..58f342108e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -688,7 +688,6 @@ F: include/hw/misc/imx25_ccm.h
F: include/hw/watchdog/wdt_imx2.h
i.MX31 (kzm)
-M: Peter Chubb <peter.chubb@nicta.com.au>
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Odd Fixes
diff --git a/VERSION b/VERSION
index 298bd24435..af3fcb4cb7 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-5.2.91
+5.2.92
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index aa2bbd14e0..9f01d9041b 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2443,7 +2443,9 @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
if (vms->platform_bus_dev) {
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
+
+ if (device_is_dynamic_sysbus(mc, dev)) {
platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
SYS_BUS_DEVICE(dev));
}
@@ -2527,7 +2529,9 @@ static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
DeviceState *dev)
{
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) ||
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (device_is_dynamic_sysbus(mc, dev) ||
(object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
return HOTPLUG_HANDLER(machine);
}
@@ -2670,19 +2674,19 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
"Set on/off to enable/disable "
"ITS instantiation");
- object_class_property_add_str(oc, "oem-id",
+ object_class_property_add_str(oc, "x-oem-id",
virt_get_oem_id,
virt_set_oem_id);
- object_class_property_set_description(oc, "oem-id",
+ object_class_property_set_description(oc, "x-oem-id",
"Override the default value of field OEMID "
"in ACPI table header."
"The string may be up to 6 bytes in size");
- object_class_property_add_str(oc, "oem-table-id",
+ object_class_property_add_str(oc, "x-oem-table-id",
virt_get_oem_table_id,
virt_set_oem_table_id);
- object_class_property_set_description(oc, "oem-table-id",
+ object_class_property_set_description(oc, "x-oem-table-id",
"Override the default value of field OEM Table ID "
"in ACPI table header."
"The string may be up to 8 bytes in size");
diff --git a/hw/block/nvme-dif.c b/hw/block/nvme-dif.c
index e6f04faafb..81b0a4cb13 100644
--- a/hw/block/nvme-dif.c
+++ b/hw/block/nvme-dif.c
@@ -1,3 +1,13 @@
+/*
+ * QEMU NVM Express End-to-End Data Protection support
+ *
+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.
+ *
+ * Authors:
+ * Klaus Jensen <k.jensen@samsung.com>
+ * Gollu Appalanaidu <anaidu.gollu@samsung.com>
+ */
+
#include "qemu/osdep.h"
#include "hw/block/block.h"
#include "sysemu/dma.h"
diff --git a/hw/block/nvme-dif.h b/hw/block/nvme-dif.h
index 5a8e37c852..524faffbd7 100644
--- a/hw/block/nvme-dif.h
+++ b/hw/block/nvme-dif.h
@@ -1,3 +1,13 @@
+/*
+ * QEMU NVM Express End-to-End Data Protection support
+ *
+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.
+ *
+ * Authors:
+ * Klaus Jensen <k.jensen@samsung.com>
+ * Gollu Appalanaidu <anaidu.gollu@samsung.com>
+ */
+
#ifndef HW_NVME_DIF_H
#define HW_NVME_DIF_H
diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c
index 7f8d139a86..7bb618f182 100644
--- a/hw/block/nvme-ns.c
+++ b/hw/block/nvme-ns.c
@@ -73,7 +73,7 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
/* support DULBE and I/O optimization fields */
id_ns->nsfeat |= (0x4 | 0x10);
- if (nvme_ns_shared(ns)) {
+ if (ns->params.shared) {
id_ns->nmic |= NVME_NMIC_NS_SHARED;
}
@@ -387,25 +387,46 @@ static void nvme_zoned_ns_shutdown(NvmeNamespace *ns)
assert(ns->nr_open_zones == 0);
}
-static int nvme_ns_check_constraints(NvmeNamespace *ns, Error **errp)
+static int nvme_ns_check_constraints(NvmeCtrl *n, NvmeNamespace *ns,
+ Error **errp)
{
if (!ns->blkconf.blk) {
error_setg(errp, "block backend not configured");
return -1;
}
- if (ns->params.pi && !ns->params.ms) {
+ if (ns->params.pi && ns->params.ms < 8) {
error_setg(errp, "at least 8 bytes of metadata required to enable "
"protection information");
return -1;
}
+ if (ns->params.nsid > NVME_MAX_NAMESPACES) {
+ error_setg(errp, "invalid namespace id (must be between 0 and %d)",
+ NVME_MAX_NAMESPACES);
+ return -1;
+ }
+
+ if (!n->subsys) {
+ if (ns->params.detached) {
+ error_setg(errp, "detached requires that the nvme device is "
+ "linked to an nvme-subsys device");
+ return -1;
+ }
+
+ if (ns->params.shared) {
+ error_setg(errp, "shared requires that the nvme device is "
+ "linked to an nvme-subsys device");
+ return -1;
+ }
+ }
+
return 0;
}
-int nvme_ns_setup(NvmeNamespace *ns, Error **errp)
+int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
{
- if (nvme_ns_check_constraints(ns, errp)) {
+ if (nvme_ns_check_constraints(n, ns, errp)) {
return -1;
}
@@ -453,27 +474,62 @@ static void nvme_ns_realize(DeviceState *dev, Error **errp)
NvmeNamespace *ns = NVME_NS(dev);
BusState *s = qdev_get_parent_bus(dev);
NvmeCtrl *n = NVME(s->parent);
+ NvmeSubsystem *subsys = n->subsys;
+ uint32_t nsid = ns->params.nsid;
+ int i;
- if (nvme_ns_setup(ns, errp)) {
+ if (nvme_ns_setup(n, ns, errp)) {
return;
}
- if (ns->subsys) {
- if (nvme_subsys_register_ns(ns, errp)) {
+ if (!nsid) {
+ for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {
+ if (nvme_ns(n, i) || nvme_subsys_ns(subsys, i)) {
+ continue;
+ }
+
+ nsid = ns->params.nsid = i;
+ break;
+ }
+
+ if (!nsid) {
+ error_setg(errp, "no free namespace id");
return;
}
} else {
- if (nvme_register_namespace(n, ns, errp)) {
+ if (nvme_ns(n, nsid) || nvme_subsys_ns(subsys, nsid)) {
+ error_setg(errp, "namespace id '%d' already allocated", nsid);
return;
}
}
+
+ if (subsys) {
+ subsys->namespaces[nsid] = ns;
+
+ if (ns->params.detached) {
+ return;
+ }
+
+ if (ns->params.shared) {
+ for (i = 0; i < ARRAY_SIZE(subsys->ctrls); i++) {
+ NvmeCtrl *ctrl = subsys->ctrls[i];
+
+ if (ctrl) {
+ nvme_attach_ns(ctrl, ns);
+ }
+ }
+
+ return;
+ }
+ }
+
+ nvme_attach_ns(n, ns);
}
static Property nvme_ns_props[] = {
DEFINE_BLOCK_PROPERTIES(NvmeNamespace, blkconf),
- DEFINE_PROP_LINK("subsys", NvmeNamespace, subsys, TYPE_NVME_SUBSYS,
- NvmeSubsystem *),
DEFINE_PROP_BOOL("detached", NvmeNamespace, params.detached, false),
+ DEFINE_PROP_BOOL("shared", NvmeNamespace, params.shared, false),
DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0),
DEFINE_PROP_UUID("uuid", NvmeNamespace, params.uuid),
DEFINE_PROP_UINT16("ms", NvmeNamespace, params.ms, 0),
diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h
index 9ab7894fc8..fb0a41f912 100644
--- a/hw/block/nvme-ns.h
+++ b/hw/block/nvme-ns.h
@@ -29,6 +29,7 @@ typedef struct NvmeZone {
typedef struct NvmeNamespaceParams {
bool detached;
+ bool shared;
uint32_t nsid;
QemuUUID uuid;
@@ -60,8 +61,8 @@ typedef struct NvmeNamespace {
const uint32_t *iocs;
uint8_t csi;
uint16_t status;
+ int attached;
- NvmeSubsystem *subsys;
QTAILQ_ENTRY(NvmeNamespace) entry;
NvmeIdNsZoned *id_ns_zoned;
@@ -96,12 +97,7 @@ static inline uint32_t nvme_nsid(NvmeNamespace *ns)
return ns->params.nsid;
}
- return -1;
-}
-
-static inline bool nvme_ns_shared(NvmeNamespace *ns)
-{
- return !!ns->subsys;
+ return 0;
}
static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns)
@@ -225,7 +221,7 @@ static inline void nvme_aor_dec_active(NvmeNamespace *ns)
}
void nvme_ns_init_format(NvmeNamespace *ns);
-int nvme_ns_setup(NvmeNamespace *ns, Error **errp);
+int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
void nvme_ns_drain(NvmeNamespace *ns);
void nvme_ns_shutdown(NvmeNamespace *ns);
void nvme_ns_cleanup(NvmeNamespace *ns);
diff --git a/hw/block/nvme-subsys.c b/hw/block/nvme-subsys.c
index 9fadef8cec..283a97b79d 100644
--- a/hw/block/nvme-subsys.c
+++ b/hw/block/nvme-subsys.c
@@ -43,34 +43,6 @@ int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp)
return cntlid;
}
-int nvme_subsys_register_ns(NvmeNamespace *ns, Error **errp)
-{
- NvmeSubsystem *subsys = ns->subsys;
- NvmeCtrl *n;
- uint32_t nsid = nvme_nsid(ns);
- int i;
-
- assert(nsid && nsid <= NVME_SUBSYS_MAX_NAMESPACES);
-
- if (subsys->namespaces[nsid]) {
- error_setg(errp, "namespace %d already registerd to subsy %s",
- nvme_nsid(ns), subsys->parent_obj.id);
- return -1;
- }
-
- subsys->namespaces[nsid] = ns;
-
- for (i = 0; i < ARRAY_SIZE(subsys->ctrls); i++) {
- n = subsys->ctrls[i];
-
- if (n && nvme_register_namespace(n, ns, errp)) {
- return -1;
- }
- }
-
- return 0;
-}
-
static void nvme_subsys_setup(NvmeSubsystem *subsys)
{
const char *nqn = subsys->params.nqn ?
diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h
index aafa04b848..7d7ef5f7f1 100644
--- a/hw/block/nvme-subsys.h
+++ b/hw/block/nvme-subsys.h
@@ -14,7 +14,7 @@
OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS)
#define NVME_SUBSYS_MAX_CTRLS 32
-#define NVME_SUBSYS_MAX_NAMESPACES 256
+#define NVME_MAX_NAMESPACES 256
typedef struct NvmeCtrl NvmeCtrl;
typedef struct NvmeNamespace NvmeNamespace;
@@ -24,7 +24,7 @@ typedef struct NvmeSubsystem {
NvmeCtrl *ctrls[NVME_SUBSYS_MAX_CTRLS];
/* Allocated namespaces for this subsystem */
- NvmeNamespace *namespaces[NVME_SUBSYS_MAX_NAMESPACES + 1];
+ NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1];
struct {
char *nqn;
@@ -32,12 +32,11 @@ typedef struct NvmeSubsystem {
} NvmeSubsystem;
int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
-int nvme_subsys_register_ns(NvmeNamespace *ns, Error **errp);
static inline NvmeCtrl *nvme_subsys_ctrl(NvmeSubsystem *subsys,
uint32_t cntlid)
{
- if (!subsys) {
+ if (!subsys || cntlid >= NVME_SUBSYS_MAX_CTRLS) {
return NULL;
}
@@ -50,12 +49,10 @@ static inline NvmeCtrl *nvme_subsys_ctrl(NvmeSubsystem *subsys,
static inline NvmeNamespace *nvme_subsys_ns(NvmeSubsystem *subsys,
uint32_t nsid)
{
- if (!subsys) {
+ if (!subsys || !nsid || nsid > NVME_MAX_NAMESPACES) {
return NULL;
}
- assert(nsid && nsid <= NVME_SUBSYS_MAX_NAMESPACES);
-
return subsys->namespaces[nsid];
}
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 7244534a89..6b1f056a0e 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -93,10 +93,13 @@
*
* nvme namespace device parameters
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- * - `subsys`
- * If given, the namespace will be attached to all controllers in the
- * subsystem. Otherwise, `bus` must be given to attach this namespace to a
- * specific controller as a non-shared namespace.
+ * - `shared`
+ * When the parent nvme device (as defined explicitly by the 'bus' parameter
+ * or implicitly by the most recently defined NvmeBus) is linked to an
+ * nvme-subsys device, the namespace will be attached to all controllers in
+ * the subsystem. If set to 'off' (the default), the namespace will remain a
+ * private namespace and may only be attached to a single controller at a
+ * time.
*
* - `detached`
* This parameter is only valid together with the `subsys` parameter. If left
@@ -4242,7 +4245,7 @@ static uint16_t nvme_identify_ns_attached_list(NvmeCtrl *n, NvmeRequest *req)
continue;
}
- if (!nvme_ns_is_attached(ctrl, ns)) {
+ if (!nvme_ns(ctrl, c->nsid)) {
continue;
}
@@ -4868,6 +4871,21 @@ static uint16_t nvme_aer(NvmeCtrl *n, NvmeRequest *req)
return NVME_NO_COMPLETE;
}
+static void nvme_update_dmrsl(NvmeCtrl *n)
+{
+ int nsid;
+
+ for (nsid = 1; nsid <= NVME_MAX_NAMESPACES; nsid++) {
+ NvmeNamespace *ns = nvme_ns(n, nsid);
+ if (!ns) {
+ continue;
+ }
+
+ n->dmrsl = MIN_NON_ZERO(n->dmrsl,
+ BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1));
+ }
+}
+
static void __nvme_select_ns_iocs(NvmeCtrl *n, NvmeNamespace *ns);
static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
{
@@ -4884,6 +4902,10 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
trace_pci_nvme_ns_attachment(nvme_cid(req), dw10 & 0xf);
+ if (!nvme_nsid_valid(n, nsid)) {
+ return NVME_INVALID_NSID | NVME_DNR;
+ }
+
ns = nvme_subsys_ns(n->subsys, nsid);
if (!ns) {
return NVME_INVALID_FIELD | NVME_DNR;
@@ -4898,6 +4920,7 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
return NVME_NS_CTRL_LIST_INVALID | NVME_DNR;
}
+ *nr_ids = MIN(*nr_ids, NVME_CONTROLLER_LIST_SIZE - 1);
for (i = 0; i < *nr_ids; i++) {
ctrl = nvme_subsys_ctrl(n->subsys, ids[i]);
if (!ctrl) {
@@ -4905,18 +4928,25 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req)
}
if (attach) {
- if (nvme_ns_is_attached(ctrl, ns)) {
+ if (nvme_ns(ctrl, nsid)) {
return NVME_NS_ALREADY_ATTACHED | NVME_DNR;
}
- nvme_ns_attach(ctrl, ns);
+ if (ns->attached && !ns->params.shared) {
+ return NVME_NS_PRIVATE | NVME_DNR;
+ }
+
+ nvme_attach_ns(ctrl, ns);
__nvme_select_ns_iocs(ctrl, ns);
} else {
- if (!nvme_ns_is_attached(ctrl, ns)) {
+ if (!nvme_ns(ctrl, nsid)) {
return NVME_NS_NOT_ATTACHED | NVME_DNR;
}
- nvme_ns_detach(ctrl, ns);
+ ctrl->namespaces[nsid - 1] = NULL;
+ ns->attached--;
+
+ nvme_update_dmrsl(ctrl);
}
/*
@@ -5805,9 +5835,10 @@ static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
params->max_ioqpairs = params->num_queues - 1;
}
- if (n->conf.blk) {
- warn_report("drive property is deprecated; "
- "please use an nvme-ns device instead");
+ if (n->namespace.blkconf.blk && n->subsys) {
+ error_setg(errp, "subsystem support is unavailable with legacy "
+ "namespace ('drive' property)");
+ return;
}
if (params->max_ioqpairs < 1 ||
@@ -5870,75 +5901,6 @@ static void nvme_init_state(NvmeCtrl *n)
n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1);
}
-static int nvme_attach_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
-{
- if (nvme_ns_is_attached(n, ns)) {
- error_setg(errp,
- "namespace %d is already attached to controller %d",
- nvme_nsid(ns), n->cntlid);
- return -1;
- }
-
- nvme_ns_attach(n, ns);
-
- return 0;
-}
-
-int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp)
-{
- uint32_t nsid = nvme_nsid(ns);
-
- if (nsid > NVME_MAX_NAMESPACES) {
- error_setg(errp, "invalid namespace id (must be between 0 and %d)",
- NVME_MAX_NAMESPACES);
- return -1;
- }
-
- if (!nsid) {
- for (int i = 1; i <= n->num_namespaces; i++) {
- if (!nvme_ns(n, i)) {
- nsid = ns->params.nsid = i;
- break;
- }
- }
-
- if (!nsid) {
- error_setg(errp, "no free namespace id");
- return -1;
- }
- } else {
- if (n->namespaces[nsid - 1]) {
- error_setg(errp, "namespace id '%d' is already in use", nsid);
- return -1;
- }
- }
-
- trace_pci_nvme_register_namespace(nsid);
-
- /*
- * If subsys is not given, namespae is always attached to the controller
- * because there's no subsystem to manage namespace allocation.
- */
- if (!n->subsys) {
- if (ns->params.detached) {
- error_setg(errp,
- "detached needs nvme-subsys specified nvme or nvme-ns");
- return -1;
- }
-
- return nvme_attach_namespace(n, ns, errp);
- } else {
- if (!ns->params.detached) {
- return nvme_attach_namespace(n, ns, errp);
- }
- }
-
- n->dmrsl = MIN_NON_ZERO(n->dmrsl,
- BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1));
-
- return 0;
-}
-
static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
{
uint64_t cmb_size = n->params.cmb_size_mb * MiB;
@@ -6168,6 +6130,18 @@ static int nvme_init_subsys(NvmeCtrl *n, Error **errp)
return 0;
}
+void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns)
+{
+ uint32_t nsid = ns->params.nsid;
+ assert(nsid && nsid <= NVME_MAX_NAMESPACES);
+
+ n->namespaces[nsid - 1] = ns;
+ ns->attached++;
+
+ n->dmrsl = MIN_NON_ZERO(n->dmrsl,
+ BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1));
+}
+
static void nvme_realize(PCIDevice *pci_dev, Error **errp)
{
NvmeCtrl *n = NVME(pci_dev);
@@ -6199,13 +6173,11 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
ns = &n->namespace;
ns->params.nsid = 1;
- if (nvme_ns_setup(ns, errp)) {
+ if (nvme_ns_setup(n, ns, errp)) {
return;
}
- if (nvme_register_namespace(n, ns, errp)) {
- return;
- }
+ nvme_attach_ns(n, ns);
}
}
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 5b0031b11d..5d05ec368f 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -6,17 +6,9 @@
#include "nvme-subsys.h"
#include "nvme-ns.h"
-#define NVME_MAX_NAMESPACES 256
-
#define NVME_DEFAULT_ZONE_SIZE (128 * MiB)
#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
-/*
- * Subsystem namespace list for allocated namespaces should be larger than
- * attached namespace list in a controller.
- */
-QEMU_BUILD_BUG_ON(NVME_MAX_NAMESPACES > NVME_SUBSYS_MAX_NAMESPACES);
-
typedef struct NvmeParams {
char *serial;
uint32_t num_queues; /* deprecated since 5.1 */
@@ -86,6 +78,7 @@ static inline const char *nvme_adm_opc_str(uint8_t opc)
case NVME_ADM_CMD_SET_FEATURES: return "NVME_ADM_CMD_SET_FEATURES";
case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
+ case NVME_ADM_CMD_NS_ATTACHMENT: return "NVME_ADM_CMD_NS_ATTACHMENT";
case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM";
default: return "NVME_ADM_CMD_UNKNOWN";
}
@@ -165,7 +158,6 @@ typedef struct NvmeCtrl {
NvmeBar bar;
NvmeParams params;
NvmeBus bus;
- BlockConf conf;
uint16_t cntlid;
bool qs_created;
@@ -234,35 +226,6 @@ static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
return n->namespaces[nsid - 1];
}
-static inline bool nvme_ns_is_attached(NvmeCtrl *n, NvmeNamespace *ns)
-{
- int nsid;
-
- for (nsid = 1; nsid <= n->num_namespaces; nsid++) {
- if (nvme_ns(n, nsid) == ns) {
- return true;
- }
- }
-
- return false;
-}
-
-static inline void nvme_ns_attach(NvmeCtrl *n, NvmeNamespace *ns)
-{
- uint32_t nsid = nvme_nsid(ns);
- assert(nsid && nsid <= NVME_MAX_NAMESPACES);
-
- n->namespaces[nsid - 1] = ns;
-}
-
-static inline void nvme_ns_detach(NvmeCtrl *n, NvmeNamespace *ns)
-{
- uint32_t nsid = nvme_nsid(ns);
- assert(nsid && nsid <= NVME_MAX_NAMESPACES);
-
- n->namespaces[nsid - 1] = NULL;
-}
-
static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
{
NvmeSQueue *sq = req->sq;
@@ -291,7 +254,7 @@ typedef enum NvmeTxDirection {
NVME_TX_DIRECTION_FROM_DEVICE = 1,
} NvmeTxDirection;
-int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
+void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns);
uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
NvmeTxDirection dir, NvmeRequest *req);
uint16_t nvme_bounce_mdata(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 22da06986d..fa12e3a67a 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -51,7 +51,6 @@ hd_geometry_guess(void *blk, uint32_t cyls, uint32_t heads, uint32_t secs, int t
# nvme.c
# nvme traces for successful events
-pci_nvme_register_namespace(uint32_t nsid) "nsid %"PRIu32""
pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u"
pci_nvme_irq_pin(void) "pulsing IRQ pin"
pci_nvme_irq_masked(void) "IRQ is masked"
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 9935c6ddd5..40def78183 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -53,6 +53,7 @@ GlobalProperty hw_compat_5_1[] = {
{ "nvme", "use-intel-id", "on"},
{ "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
{ "pl011", "migrate-clk", "off" },
+ { "virtio-pci", "x-ats-page-aligned", "off"},
};
const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
@@ -529,20 +530,31 @@ void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
}
-static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque)
+bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
{
- MachineState *machine = opaque;
- MachineClass *mc = MACHINE_GET_CLASS(machine);
bool allowed = false;
strList *wl;
+ Object *obj = OBJECT(dev);
+
+ if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
+ return false;
+ }
for (wl = mc->allowed_dynamic_sysbus_devices;
!allowed && wl;
wl = wl->next) {
- allowed |= !!object_dynamic_cast(OBJECT(sbdev), wl->value);
+ allowed |= !!object_dynamic_cast(obj, wl->value);
}
- if (!allowed) {
+ return allowed;
+}
+
+static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque)
+{
+ MachineState *machine = opaque;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (!device_is_dynamic_sysbus(mc, DEVICE(sbdev))) {
error_report("Option '-device %s' cannot be handled by this machine",
object_class_get_name(object_get_class(OBJECT(sbdev))));
exit(1);
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index a733e2fb87..fd0fa157e8 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -963,16 +963,18 @@ void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
}
-void pcie_ats_init(PCIDevice *dev, uint16_t offset)
+void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned)
{
pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
offset, PCI_EXT_CAP_ATS_SIZEOF);
dev->exp.ats_cap = offset;
- /* Invalidate Queue Depth 0, Page Aligned Request 1 */
- pci_set_word(dev->config + offset + PCI_ATS_CAP,
- PCI_ATS_CAP_PAGE_ALIGNED);
+ /* Invalidate Queue Depth 0 */
+ if (aligned) {
+ pci_set_word(dev->config + offset + PCI_ATS_CAP,
+ PCI_ATS_CAP_PAGE_ALIGNED);
+ }
/* STU 0, Disabled by default */
pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index bddd5e7c48..fc911bbb7b 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -48,7 +48,9 @@ static void e500plat_machine_device_plug_cb(HotplugHandler *hotplug_dev,
PPCE500MachineState *pms = PPCE500_MACHINE(hotplug_dev);
if (pms->pbus_dev) {
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
+ MachineClass *mc = MACHINE_GET_CLASS(pms);
+
+ if (device_is_dynamic_sysbus(mc, dev)) {
platform_bus_link_device(pms->pbus_dev, SYS_BUS_DEVICE(dev));
}
}
@@ -58,7 +60,9 @@ static
HotplugHandler *e500plat_machine_get_hotpug_handler(MachineState *machine,
DeviceState *dev)
{
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (device_is_dynamic_sysbus(mc, dev)) {
return HOTPLUG_HANDLER(machine);
}
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index c1b67cf6fc..b321604d9b 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1856,7 +1856,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
}
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
- pcie_ats_init(pci_dev, last_pcie_cap_offset);
+ pcie_ats_init(pci_dev, last_pcie_cap_offset,
+ proxy->flags & VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED);
last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
}
@@ -1933,6 +1934,8 @@ static Property virtio_pci_properties[] = {
ignore_backend_features, false),
DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_ATS_BIT, false),
+ DEFINE_PROP_BIT("x-ats-page-aligned", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, true),
DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
index d7d5d403a9..2446dcd9ae 100644
--- a/hw/virtio/virtio-pci.h
+++ b/hw/virtio/virtio-pci.h
@@ -42,6 +42,7 @@ enum {
VIRTIO_PCI_FLAG_INIT_PM_BIT,
VIRTIO_PCI_FLAG_INIT_FLR_BIT,
VIRTIO_PCI_FLAG_AER_BIT,
+ VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -84,6 +85,10 @@ enum {
/* Advanced Error Reporting capability */
#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
+/* Page Aligned Address space Translation Service */
+#define VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED \
+ (1 << VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT)
+
typedef struct {
MSIMessage msg;
int virq;
diff --git a/include/block/nvme.h b/include/block/nvme.h
index b0a4e42916..4ac926fbc6 100644
--- a/include/block/nvme.h
+++ b/include/block/nvme.h
@@ -847,6 +847,7 @@ enum NvmeStatusCodes {
NVME_FEAT_NOT_NS_SPEC = 0x010f,
NVME_FW_REQ_SUSYSTEM_RESET = 0x0110,
NVME_NS_ALREADY_ATTACHED = 0x0118,
+ NVME_NS_PRIVATE = 0x0119,
NVME_NS_NOT_ATTACHED = 0x011A,
NVME_NS_CTRL_LIST_INVALID = 0x011C,
NVME_CONFLICTING_ATTRS = 0x0180,
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 4a90549ad8..ad6c8fd537 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -36,7 +36,46 @@ void machine_set_cpu_numa_node(MachineState *machine,
const CpuInstanceProperties *props,
Error **errp);
+/**
+ * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices
+ * @mc: Machine class
+ * @type: type to allow (should be a subtype of TYPE_SYS_BUS_DEVICE)
+ *
+ * Add the QOM type @type to the list of devices of which are subtypes
+ * of TYPE_SYS_BUS_DEVICE but which are still permitted to be dynamically
+ * created (eg by the user on the command line with -device).
+ * By default if the user tries to create any devices on the command line
+ * that are subtypes of TYPE_SYS_BUS_DEVICE they will get an error message;
+ * for the special cases which are permitted for this machine model, the
+ * machine model class init code must call this function to add them
+ * to the list of specifically permitted devices.
+ */
void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type);
+
+/**
+ * device_is_dynamic_sysbus: test whether device is a dynamic sysbus device
+ * @mc: Machine class
+ * @dev: device to check
+ *
+ * Returns: true if @dev is a sysbus device on the machine's list
+ * of dynamically pluggable sysbus devices; otherwise false.
+ *
+ * This function checks whether @dev is a valid dynamic sysbus device,
+ * by first confirming that it is a sysbus device and then checking it
+ * against the list of permitted dynamic sysbus devices which has been
+ * set up by the machine using machine_class_allow_dynamic_sysbus_dev().
+ *
+ * It is valid to call this with something that is not a subclass of
+ * TYPE_SYS_BUS_DEVICE; the function will return false in this case.
+ * This allows hotplug callback functions to be written as:
+ * if (device_is_dynamic_sysbus(mc, dev)) {
+ * handle dynamic sysbus case;
+ * } else if (some other kind of hotplug) {
+ * handle that;
+ * }
+ */
+bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev);
+
/*
* Checks that backend isn't used, preps it for exclusive usage and
* returns migratable MemoryRegion provided by backend.
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 26c9cc45a4..c09b648dff 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -78,8 +78,8 @@ struct X86MachineState {
#define X86_MACHINE_SMM "smm"
#define X86_MACHINE_ACPI "acpi"
-#define X86_MACHINE_OEM_ID "oem-id"
-#define X86_MACHINE_OEM_TABLE_ID "oem-table-id"
+#define X86_MACHINE_OEM_ID "x-oem-id"
+#define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id"
#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
index 14c58ebdb6..6063bee0ec 100644
--- a/include/hw/pci/pcie.h
+++ b/include/hw/pci/pcie.h
@@ -137,7 +137,7 @@ void pcie_acs_reset(PCIDevice *dev);
void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num);
-void pcie_ats_init(PCIDevice *dev, uint16_t offset);
+void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned);
void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fe68f464b3..193a49ec7f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -942,7 +942,6 @@ struct ARMCPU {
uint64_t id_aa64mmfr2;
uint64_t id_aa64dfr0;
uint64_t id_aa64dfr1;
- uint64_t reset_pmcr_el0;
} isar;
uint64_t midr;
uint32_t revidr;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5d9d56a33c..f0a9e968c9 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -141,7 +141,6 @@ static void aarch64_a57_initfn(Object *obj)
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
- cpu->isar.reset_pmcr_el0 = 0x41013000;
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
}
@@ -195,7 +194,6 @@ static void aarch64_a53_initfn(Object *obj)
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
- cpu->isar.reset_pmcr_el0 = 0x41033000;
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
}
@@ -247,7 +245,6 @@ static void aarch64_a72_initfn(Object *obj)
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
- cpu->isar.reset_pmcr_el0 = 0x41023000;
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
}
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 8252fd29f9..046e476f65 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -301,7 +301,6 @@ static void cortex_a8_initfn(Object *obj)
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
cpu->reset_auxcr = 2;
- cpu->isar.reset_pmcr_el0 = 0x41002000;
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
}
@@ -374,7 +373,6 @@ static void cortex_a9_initfn(Object *obj)
cpu->clidr = (1 << 27) | (1 << 24) | 3;
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
- cpu->isar.reset_pmcr_el0 = 0x41093000;
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
}
@@ -445,7 +443,6 @@ static void cortex_a7_initfn(Object *obj)
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
- cpu->isar.reset_pmcr_el0 = 0x41072000;
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
}
@@ -488,7 +485,6 @@ static void cortex_a15_initfn(Object *obj)
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
- cpu->isar.reset_pmcr_el0 = 0x410F3000;
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
}
@@ -721,7 +717,6 @@ static void cortex_r5_initfn(Object *obj)
cpu->isar.id_isar6 = 0x0;
cpu->mp_is_up = true;
cpu->pmsav7_dregion = 16;
- cpu->isar.reset_pmcr_el0 = 0x41151800;
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8fb6cc96e4..d9220be7c5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -38,6 +38,7 @@
#endif
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
+#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
#ifndef CONFIG_USER_ONLY
@@ -1148,9 +1149,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
static inline uint32_t pmu_num_counters(CPUARMState *env)
{
- ARMCPU *cpu = env_archcpu(env);
-
- return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
+ return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
}
/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
@@ -5754,6 +5753,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.resetvalue = 0,
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
#endif
+ /* The only field of MDCR_EL2 that has a defined architectural reset value
+ * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
+ */
+ { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
+ .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS,
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
{ .name = "HPFAR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
@@ -6683,7 +6689,7 @@ static void define_pmu_regs(ARMCPU *cpu)
* field as main ID register, and we implement four counters in
* addition to the cycle count register.
*/
- unsigned int i, pmcrn = pmu_num_counters(&cpu->env);
+ unsigned int i, pmcrn = PMCR_NUM_COUNTERS;
ARMCPRegInfo pmcr = {
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
.access = PL0_RW,
@@ -6698,10 +6704,10 @@ static void define_pmu_regs(ARMCPU *cpu)
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = cpu->isar.reset_pmcr_el0,
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
+ PMCRLC,
.writefn = pmcr_write, .raw_writefn = raw_write,
};
-
define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &pmcr64);
for (i = 0; i < pmcrn; i++) {
@@ -7819,17 +7825,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
REGINFO_SENTINEL
};
- /*
- * The only field of MDCR_EL2 that has a defined architectural reset
- * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
- */
- ARMCPRegInfo mdcr_el2 = {
- .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
- .access = PL2_RW, .resetvalue = pmu_num_counters(env),
- .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2),
- };
- define_one_arm_cp_reg(cpu, &mdcr_el2);
define_arm_cp_regs(cpu, vpidr_regs);
define_arm_cp_regs(cpu, el2_cp_reginfo);
if (arm_feature(env, ARM_FEATURE_V8)) {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 581335e49d..dff85f6db9 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -566,8 +566,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 7, 1));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
ARM64_SYS_REG(3, 0, 0, 7, 2));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
- ARM64_SYS_REG(3, 3, 9, 12, 0));
/*
* Note that if AArch32 support is not present in the host,
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index e020c83d2a..156d4174aa 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -73,7 +73,7 @@
#define OEM_ID "TEST"
#define OEM_TABLE_ID "OEM"
-#define OEM_TEST_ARGS "-machine oem-id="OEM_ID",oem-table-id="OEM_TABLE_ID
+#define OEM_TEST_ARGS "-machine x-oem-id="OEM_ID",x-oem-table-id="OEM_TABLE_ID
typedef struct {
bool tcg_only;
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-23 23:12:36 +0200