diff options
52 files changed, 2346 insertions, 1967 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index caf7e8aca8..36eeb42d19 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1577,7 +1577,7 @@ F: include/migration/failover.h F: docs/COLO-FT.txt COLO Proxy -M: Zhang Chen <zhangchen.fnst@cn.fujitsu.com> +M: Zhang Chen <zhangckid@gmail.com> M: Li Zhijian <lizhijian@cn.fujitsu.com> S: Supported F: docs/colo-proxy.txt diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d84b01d1b8..ff6866624a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -329,6 +329,41 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); } +void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) +{ + if (TCG_TARGET_HAS_direct_jump) { + uintptr_t offset = tb->jmp_target_arg[n]; + uintptr_t tc_ptr = (uintptr_t)tb->tc_ptr; + tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); + } else { + tb->jmp_target_arg[n] = addr; + } +} + +/* Called with tb_lock held. */ +static inline void tb_add_jump(TranslationBlock *tb, int n, + TranslationBlock *tb_next) +{ + assert(n < ARRAY_SIZE(tb->jmp_list_next)); + if (tb->jmp_list_next[n]) { + /* Another thread has already done this while we were + * outside of the lock; nothing to do in this case */ + return; + } + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, + "Linking TBs %p [" TARGET_FMT_lx + "] index %d -> %p [" TARGET_FMT_lx "]\n", + tb->tc_ptr, tb->pc, n, + tb_next->tc_ptr, tb_next->pc); + + /* patch the native jump address */ + tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); + + /* add in TB jmp circular list */ + tb->jmp_list_next[n] = tb_next->jmp_list_first; + tb_next->jmp_list_first = (uintptr_t)tb | n; +} + static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 37ecafa931..2d1ed06065 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1289,13 +1289,13 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID; tb->jmp_reset_offset[1] = TB_JMP_RESET_OFFSET_INVALID; tcg_ctx.tb_jmp_reset_offset = tb->jmp_reset_offset; -#ifdef USE_DIRECT_JUMP - tcg_ctx.tb_jmp_insn_offset = tb->jmp_insn_offset; - tcg_ctx.tb_jmp_target_addr = NULL; -#else - tcg_ctx.tb_jmp_insn_offset = NULL; - tcg_ctx.tb_jmp_target_addr = tb->jmp_target_addr; -#endif + if (TCG_TARGET_HAS_direct_jump) { + tcg_ctx.tb_jmp_insn_offset = tb->jmp_target_arg; + tcg_ctx.tb_jmp_target_addr = NULL; + } else { + tcg_ctx.tb_jmp_insn_offset = NULL; + tcg_ctx.tb_jmp_target_addr = tb->jmp_target_arg; + } #ifdef CONFIG_PROFILER tcg_ctx.tb_count++; @@ -1329,7 +1329,27 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_in_addr_range(tb->pc)) { qemu_log_lock(); qemu_log("OUT: [size=%d]\n", gen_code_size); - log_disas(tb->tc_ptr, gen_code_size); + if (tcg_ctx.data_gen_ptr) { + size_t code_size = tcg_ctx.data_gen_ptr - tb->tc_ptr; + size_t data_size = gen_code_size - code_size; + size_t i; + + log_disas(tb->tc_ptr, code_size); + + for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { + if (sizeof(tcg_target_ulong) == 8) { + qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", + (uintptr_t)tcg_ctx.data_gen_ptr + i, + *(uint64_t *)(tcg_ctx.data_gen_ptr + i)); + } else { + qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", + (uintptr_t)tcg_ctx.data_gen_ptr + i, + *(uint32_t *)(tcg_ctx.data_gen_ptr + i)); + } + } + } else { + log_disas(tb->tc_ptr, gen_code_size); + } qemu_log("\n"); qemu_log_flush(); qemu_log_unlock(); @@ -350,7 +350,6 @@ cocoa="no" softmmu="yes" linux_user="no" bsd_user="no" -aix="no" blobs="yes" pkgversion="" pie="" @@ -554,8 +553,6 @@ elif check_define __NetBSD__; then targetos='NetBSD' elif check_define __APPLE__; then targetos='Darwin' -elif check_define _AIX; then - targetos='AIX' else # This is a fatal error, but don't report it yet, because we # might be going to just print the --help text, or it might @@ -764,10 +761,6 @@ SunOS) LIBS="$solarisnetlibs $LIBS" libs_qga="$solarisnetlibs $libs_qga" ;; -AIX) - aix="yes" - make="${MAKE-gmake}" -;; Haiku) haiku="yes" QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS $QEMU_CFLAGS" @@ -4211,7 +4204,7 @@ elif compile_prog "" "$pthread_lib -lrt" ; then fi if test "$darwin" != "yes" -a "$mingw32" != "yes" -a "$solaris" != yes -a \ - "$aix" != "yes" -a "$haiku" != "yes" ; then + "$haiku" != "yes" ; then libs_softmmu="-lutil $libs_softmmu" fi @@ -5520,10 +5513,6 @@ if test "$darwin" = "yes" ; then echo "CONFIG_DARWIN=y" >> $config_host_mak fi -if test "$aix" = "yes" ; then - echo "CONFIG_AIX=y" >> $config_host_mak -fi - if test "$solaris" = "yes" ; then echo "CONFIG_SOLARIS=y" >> $config_host_mak fi diff --git a/docs/colo-proxy.txt b/docs/colo-proxy.txt index f6a624fb8a..8b726ea094 100644 --- a/docs/colo-proxy.txt +++ b/docs/colo-proxy.txt @@ -170,10 +170,11 @@ Primary(ip:3.3.3.3): -chardev socket,id=compare0-0,host=3.3.3.3,port=9001 -chardev socket,id=compare_out,host=3.3.3.3,port=9005,server,nowait -chardev socket,id=compare_out0,host=3.3.3.3,port=9005 +-object iothread,id=iothread1 -object filter-mirror,id=m0,netdev=hn0,queue=tx,outdev=mirror0 -object filter-redirector,netdev=hn0,id=redire0,queue=rx,indev=compare_out -object filter-redirector,netdev=hn0,id=redire1,queue=rx,outdev=compare0 --object colo-compare,id=comp0,primary_in=compare0-0,secondary_in=compare1,outdev=compare_out0 +-object colo-compare,id=comp0,primary_in=compare0-0,secondary_in=compare1,outdev=compare_out0,iothread=iothread1 Secondary(ip:3.3.3.8): -netdev tap,id=hn0,vhost=off,script=/etc/qemu-ifup,down script=/etc/qemu-ifdown diff --git a/hw/net/e1000.c b/hw/net/e1000.c index f2e5072d27..eebe3a9c13 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -1127,7 +1127,7 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = { getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV), getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL), getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC), - getreg(TNCRS), getreg(SEC), getreg(CEXTERR), getreg(RLEC), + getreg(TNCRS), getreg(SEQEC), getreg(CEXTERR), getreg(RLEC), getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC), getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC), getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL), @@ -1223,7 +1223,7 @@ static const uint8_t mac_reg_access[0x8000] = { [FFLT] = markflag(MAC), [FFMT] = markflag(MAC), [SCC] = markflag(MAC), [FCRUC] = markflag(MAC), [LATECOL] = markflag(MAC), [COLC] = markflag(MAC), - [SEC] = markflag(MAC), [CEXTERR] = markflag(MAC), + [SEQEC] = markflag(MAC), [CEXTERR] = markflag(MAC), [XONTXC] = markflag(MAC), [XOFFRXC] = markflag(MAC), [RJC] = markflag(MAC), [RNBC] = markflag(MAC), [MGTPDC] = markflag(MAC), [MGTPTC] = markflag(MAC), diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h index 23eed50b9c..ae99f58bab 100644 --- a/hw/net/e1000_regs.h +++ b/hw/net/e1000_regs.h @@ -260,7 +260,7 @@ #define E1000_COLC 0x04028 /* Collision Count - R/clr */ #define E1000_DC 0x04030 /* Defer Count - R/clr */ #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ -#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ +#define E1000_SEQEC 0x04038 /* Sequence Error Count - R/clr */ #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 81405640f0..43a8d89955 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -2855,7 +2855,7 @@ static uint32_t (*e1000e_macreg_readops[])(E1000ECore *, int) = { e1000e_getreg(RDLEN0), e1000e_getreg(RDH1), e1000e_getreg(LATECOL), - e1000e_getreg(SEC), + e1000e_getreg(SEQEC), e1000e_getreg(XONTXC), e1000e_getreg(WUS), e1000e_getreg(GORCL), diff --git a/hw/net/e1000x_common.h b/hw/net/e1000x_common.h index 21bf28e0cc..3072ce9d50 100644 --- a/hw/net/e1000x_common.h +++ b/hw/net/e1000x_common.h @@ -40,7 +40,7 @@ enum { defreg(VFTA), defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV), defreg(ITR), defreg(SCC), defreg(ECOL), defreg(MCC), defreg(LATECOL), defreg(COLC), defreg(DC), - defreg(TNCRS), defreg(SEC), defreg(CEXTERR), defreg(RLEC), + defreg(TNCRS), defreg(SEQEC), defreg(CEXTERR), defreg(RLEC), defreg(XONRXC), defreg(XONTXC), defreg(XOFFRXC), defreg(XOFFTXC), defreg(FCRUC), defreg(AIT), defreg(TDFH), defreg(TDFT), defreg(TDFHS), defreg(TDFTS), defreg(TDFPC), defreg(WUC), diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index 4f0f6d71e5..9273473d59 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -69,10 +69,10 @@ struct rocker { QLIST_ENTRY(rocker) next; }; -#define ROCKER "rocker" +#define TYPE_ROCKER "rocker" -#define to_rocker(obj) \ - OBJECT_CHECK(Rocker, (obj), ROCKER) +#define ROCKER(obj) \ + OBJECT_CHECK(Rocker, (obj), TYPE_ROCKER) static QLIST_HEAD(, rocker) rockers; @@ -239,10 +239,6 @@ static int tx_consume(Rocker *r, DescInfo *info) } iov[iovcnt].iov_len = frag_len; iov[iovcnt].iov_base = g_malloc(frag_len); - if (!iov[iovcnt].iov_base) { - err = -ROCKER_ENOMEM; - goto err_no_mem; - } pci_dma_read(dev, frag_addr, iov[iovcnt].iov_base, iov[iovcnt].iov_len); @@ -259,7 +255,6 @@ static int tx_consume(Rocker *r, DescInfo *info) err = fp_port_eg(r->fp_port[port], iov, iovcnt); err_too_many_frags: -err_no_mem: err_bad_attr: for (i = 0; i < ROCKER_TX_FRAGS_MAX; i++) { g_free(iov[i].iov_base); @@ -671,10 +666,7 @@ int rx_produce(World *world, uint32_t pport, */ data = g_malloc(data_size); - if (!data) { - err = -ROCKER_ENOMEM; - goto out; - } + iov_to_buf(iov, iovcnt, 0, data, data_size); pci_dma_write(dev, frag_addr, data, data_size); g_free(data); @@ -719,11 +711,6 @@ static void rocker_test_dma_ctrl(Rocker *r, uint32_t val) buf = g_malloc(r->test_dma_size); - if (!buf) { - DPRINTF("test dma buffer alloc failed"); - return; - } - switch (val) { case ROCKER_TEST_DMA_CTRL_CLEAR: memset(buf, 0, r->test_dma_size); @@ -1249,20 +1236,18 @@ rollback: return err; } -static int rocker_msix_init(Rocker *r) +static int rocker_msix_init(Rocker *r, Error **errp) { PCIDevice *dev = PCI_DEVICE(r); int err; - Error *local_err = NULL; err = msix_init(dev, ROCKER_MSIX_VEC_COUNT(r->fp_ports), &r->msix_bar, ROCKER_PCI_MSIX_BAR_IDX, ROCKER_PCI_MSIX_TABLE_OFFSET, &r->msix_bar, ROCKER_PCI_MSIX_BAR_IDX, ROCKER_PCI_MSIX_PBA_OFFSET, - 0, &local_err); + 0, errp); if (err) { - error_report_err(local_err); return err; } @@ -1298,9 +1283,9 @@ static World *rocker_world_type_by_name(Rocker *r, const char *name) return NULL; } -static int pci_rocker_init(PCIDevice *dev) +static void pci_rocker_realize(PCIDevice *dev, Error **errp) { - Rocker *r = to_rocker(dev); + Rocker *r = ROCKER(dev); const MACAddr zero = { .a = { 0, 0, 0, 0, 0, 0 } }; const MACAddr dflt = { .a = { 0x52, 0x54, 0x00, 0x12, 0x35, 0x01 } }; static int sw_index; @@ -1310,23 +1295,15 @@ static int pci_rocker_init(PCIDevice *dev) r->worlds[ROCKER_WORLD_TYPE_OF_DPA] = of_dpa_world_alloc(r); - for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) { - if (!r->worlds[i]) { - err = -ENOMEM; - goto err_world_alloc; - } - } - if (!r->world_name) { r->world_name = g_strdup(world_name(r->worlds[ROCKER_WORLD_TYPE_OF_DPA])); } r->world_dflt = rocker_world_type_by_name(r, r->world_name); if (!r->world_dflt) { - fprintf(stderr, - "rocker: requested world \"%s\" does not exist\n", + error_setg(errp, + "invalid argument requested world %s does not exist", r->world_name); - err = -EINVAL; goto err_world_type_by_name; } @@ -1346,7 +1323,7 @@ static int pci_rocker_init(PCIDevice *dev) /* MSI-X init */ - err = rocker_msix_init(r); + err = rocker_msix_init(r, errp); if (err) { goto err_msix_init; } @@ -1354,11 +1331,11 @@ static int pci_rocker_init(PCIDevice *dev) /* validate switch properties */ if (!r->name) { - r->name = g_strdup(ROCKER); + r->name = g_strdup(TYPE_ROCKER); } if (rocker_find(r->name)) { - err = -EEXIST; + error_setg(errp, "%s already exists", r->name); goto err_duplicate; } @@ -1372,10 +1349,10 @@ static int pci_rocker_init(PCIDevice *dev) #define ROCKER_IFNAMSIZ 16 #define MAX_ROCKER_NAME_LEN (ROCKER_IFNAMSIZ - 1 - 3 - 3) if (strlen(r->name) > MAX_ROCKER_NAME_LEN) { - fprintf(stderr, - "rocker: name too long; please shorten to at most %d chars\n", + error_setg(errp, + "name too long; please shorten to at most %d chars", MAX_ROCKER_NAME_LEN); - return -EINVAL; + goto err_name_too_long; } if (memcmp(&r->fp_start_macaddr, &zero, sizeof(zero)) == 0) { @@ -1393,9 +1370,6 @@ static int pci_rocker_init(PCIDevice *dev) } r->rings = g_new(DescRing *, rocker_pci_ring_count(r)); - if (!r->rings) { - goto err_rings_alloc; - } /* Rings are ordered like this: * - command ring @@ -1407,14 +1381,9 @@ static int pci_rocker_init(PCIDevice *dev) * ..... */ - err = -ENOMEM; for (i = 0; i < rocker_pci_ring_count(r); i++) { DescRing *ring = desc_ring_alloc(r, i); - if (!ring) { - goto err_ring_alloc; - } - if (i == ROCKER_RING_CMD) { desc_ring_set_consume(ring, cmd_consume, ROCKER_MSIX_VEC_CMD); } else if (i == ROCKER_RING_EVENT) { @@ -1434,48 +1403,31 @@ static int pci_rocker_init(PCIDevice *dev) fp_port_alloc(r, r->name, &r->fp_start_macaddr, i, &r->fp_ports_peers[i]); - if (!port) { - goto err_port_alloc; - } - r->fp_port[i] = port; fp_port_set_world(port, r->world_dflt); } QLIST_INSERT_HEAD(&rockers, r, next); - return 0; + return; -err_port_alloc: - for (--i; i >= 0; i--) { - FpPort *port = r->fp_port[i]; - fp_port_free(port); - } - i = rocker_pci_ring_count(r); -err_ring_alloc: - for (--i; i >= 0; i--) { - desc_ring_free(r->rings[i]); - } - g_free(r->rings); -err_rings_alloc: +err_name_too_long: err_duplicate: rocker_msix_uninit(r); err_msix_init: object_unparent(OBJECT(&r->msix_bar)); object_unparent(OBJECT(&r->mmio)); err_world_type_by_name: -err_world_alloc: for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) { if (r->worlds[i]) { world_free(r->worlds[i]); } } - return err; } static void pci_rocker_uninit(PCIDevice *dev) { - Rocker *r = to_rocker(dev); + Rocker *r = ROCKER(dev); int i; QLIST_REMOVE(r, next); @@ -1508,7 +1460,7 @@ static void pci_rocker_uninit(PCIDevice *dev) static void rocker_reset(DeviceState *dev) { - Rocker *r = to_rocker(dev); + Rocker *r = ROCKER(dev); int i; for (i = 0; i < ROCKER_WORLD_TYPE_MAX; i++) { @@ -1546,7 +1498,7 @@ static Property rocker_properties[] = { }; static const VMStateDescription rocker_vmsd = { - .name = ROCKER, + .name = TYPE_ROCKER, .unmigratable = 1, }; @@ -1555,7 +1507,7 @@ static void rocker_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->init = pci_rocker_init; + k->realize = pci_rocker_realize; k->exit = pci_rocker_uninit; k->vendor_id = PCI_VENDOR_ID_REDHAT; k->device_id = PCI_DEVICE_ID_REDHAT_ROCKER; @@ -1569,7 +1521,7 @@ static void rocker_class_init(ObjectClass *klass, void *data) } static const TypeInfo rocker_info = { - .name = ROCKER, + .name = TYPE_ROCKER, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(Rocker), .class_init = rocker_class_init, diff --git a/hw/net/rocker/rocker_desc.c b/hw/net/rocker/rocker_desc.c index 6184c40f72..b009da4f89 100644 --- a/hw/net/rocker/rocker_desc.c +++ b/hw/net/rocker/rocker_desc.c @@ -65,10 +65,6 @@ char *desc_get_buf(DescInfo *info, bool read_only) info->buf_size = size; } - if (!info->buf) { - return NULL; - } - pci_dma_read(dev, le64_to_cpu(info->desc.buf_addr), info->buf, size); return info->buf; @@ -142,9 +138,6 @@ bool desc_ring_set_size(DescRing *ring, uint32_t size) ring->head = ring->tail = 0; ring->info = g_renew(DescInfo, ring->info, size); - if (!ring->info) { - return false; - } memset(ring->info, 0, size * sizeof(DescInfo)); @@ -345,9 +338,6 @@ DescRing *desc_ring_alloc(Rocker *r, int index) DescRing *ring; ring = g_new0(DescRing, 1); - if (!ring) { - return NULL; - } ring->r = r; ring->index = index; diff --git a/hw/net/rocker/rocker_fp.c b/hw/net/rocker/rocker_fp.c index 1305ac36cc..4b3c9847db 100644 --- a/hw/net/rocker/rocker_fp.c +++ b/hw/net/rocker/rocker_fp.c @@ -226,10 +226,6 @@ FpPort *fp_port_alloc(Rocker *r, char *sw_name, { FpPort *port = g_new0(FpPort, 1); - if (!port) { - return NULL; - } - port->r = r; port->index = index; port->pport = index + 1; diff --git a/hw/net/rocker/rocker_of_dpa.c b/hw/net/rocker/rocker_of_dpa.c index 9b1e0d2441..191a58e0a7 100644 --- a/hw/net/rocker/rocker_of_dpa.c +++ b/hw/net/rocker/rocker_of_dpa.c @@ -368,9 +368,6 @@ static OfDpaFlow *of_dpa_flow_alloc(uint64_t cookie) int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) / 1000; flow = g_new0(OfDpaFlow, 1); - if (!flow) { - return NULL; - } flow->cookie = cookie; flow->mask.tbl_id = 0xffffffff; @@ -813,10 +810,6 @@ static OfDpaGroup *of_dpa_group_alloc(uint32_t id) { OfDpaGroup *group = g_new0(OfDpaGroup, 1); - if (!group) { - return NULL; - } - group->id = id; return group; @@ -1867,9 +1860,6 @@ static int of_dpa_cmd_flow_add(OfDpa *of_dpa, uint64_t cookie, } flow = of_dpa_flow_alloc(cookie); - if (!flow) { - return -ROCKER_ENOMEM; - } err = of_dpa_cmd_flow_add_mod(of_dpa, flow, flow_tlvs); if (err) { @@ -2040,17 +2030,10 @@ static int of_dpa_cmd_add_l2_flood(OfDpa *of_dpa, OfDpaGroup *group, rocker_tlv_get_le16(group_tlvs[ROCKER_TLV_OF_DPA_GROUP_COUNT]); tlvs = g_new0(RockerTlv *, group->l2_flood.group_count + 1); - if (!tlvs) { - return -ROCKER_ENOMEM; - } g_free(group->l2_flood.group_ids); group->l2_flood.group_ids = g_new0(uint32_t, group->l2_flood.group_count); - if (!group->l2_flood.group_ids) { - err = -ROCKER_ENOMEM; - goto err_out; - } rocker_tlv_parse_nested(tlvs, group->l2_flood.group_count, group_tlvs[ROCKER_TLV_OF_DPA_GROUP_IDS]); @@ -2157,9 +2140,6 @@ static int of_dpa_cmd_group_add(OfDpa *of_dpa, uint32_t group_id, } group = of_dpa_group_alloc(group_id); - if (!group) { - return -ROCKER_ENOMEM; - } err = of_dpa_cmd_group_do(of_dpa, group_id, group, group_tlvs); if (err) { diff --git a/hw/net/rocker/rocker_world.c b/hw/net/rocker/rocker_world.c index 89777e9684..f73c5340ed 100644 --- a/hw/net/rocker/rocker_world.c +++ b/hw/net/rocker/rocker_world.c @@ -51,13 +51,11 @@ World *world_alloc(Rocker *r, size_t sizeof_private, { World *w = g_malloc0(sizeof(World) + sizeof_private); - if (w) { - w->r = r; - w->type = type; - w->ops = ops; - if (w->ops->init) { - w->ops->init(w); - } + w->r = r; + w->type = type; + w->ops = ops; + if (w->ops->init) { + w->ops->init(w); } return w; diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c index 671c7e48c6..3be24bbee7 100644 --- a/hw/net/rtl8139.c +++ b/hw/net/rtl8139.c @@ -3132,38 +3132,6 @@ static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) /* */ -static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) -{ - rtl8139_io_writeb(opaque, addr & 0xFF, val); -} - -static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val) -{ - rtl8139_io_writew(opaque, addr & 0xFF, val); -} - -static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val) -{ - rtl8139_io_writel(opaque, addr & 0xFF, val); -} - -static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr) -{ - return rtl8139_io_readb(opaque, addr & 0xFF); -} - -static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr) -{ - uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF); - return val; -} - -static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr) -{ - uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF); - return val; -} - static int rtl8139_post_load(void *opaque, int version_id) { RTL8139State* s = opaque; @@ -3344,22 +3312,6 @@ static const MemoryRegionOps rtl8139_io_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static const MemoryRegionOps rtl8139_mmio_ops = { - .old_mmio = { - .read = { - rtl8139_mmio_readb, - rtl8139_mmio_readw, - rtl8139_mmio_readl, - }, - .write = { - rtl8139_mmio_writeb, - rtl8139_mmio_writew, - rtl8139_mmio_writel, - }, - }, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - static void rtl8139_timer(void *opaque) { RTL8139State *s = opaque; @@ -3422,8 +3374,9 @@ static void pci_rtl8139_realize(PCIDevice *dev, Error **errp) memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, "rtl8139", 0x100); - memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s, - "rtl8139", 0x100); + memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io, + 0, 0x100); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); diff --git a/include/elf.h b/include/elf.h index cd51434877..e8a515ce3d 100644 --- a/include/elf.h +++ b/include/elf.h @@ -942,8 +942,9 @@ typedef struct { #define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ #define R_390_TLS_TPOFF 56 /* Negate offset in static TLS block. */ +#define R_390_20 57 /* Keep this the last entry. */ -#define R_390_NUM 57 +#define R_390_NUM 58 /* x86-64 relocation types */ #define R_X86_64_NONE 0 /* No reloc */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ff8fbe423d..673fc066d0 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -301,15 +301,6 @@ static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif -#if defined(_ARCH_PPC) \ - || defined(__x86_64__) || defined(__i386__) \ - || defined(__sparc__) || defined(__aarch64__) \ - || defined(__s390x__) || defined(__mips__) \ - || defined(CONFIG_TCG_INTERPRETER) -/* NOTE: Direct jump patching must be atomic to be thread-safe. */ -#define USE_DIRECT_JUMP -#endif - struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ target_ulong cs_base; /* CS base for this block */ @@ -347,11 +338,8 @@ struct TranslationBlock { */ uint16_t jmp_reset_offset[2]; /* offset of original jump target */ #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ -#ifdef USE_DIRECT_JUMP - uint16_t jmp_insn_offset[2]; /* offset of native jump instruction */ -#else - uintptr_t jmp_target_addr[2]; /* target address for indirect jump */ -#endif + uintptr_t jmp_target_arg[2]; /* target address or offset */ + /* Each TB has an assosiated circular list of TBs jumping to this one. * jmp_list_first points to the first TB jumping to this one. * jmp_list_next is used to point to the next TB in a list. @@ -373,84 +361,7 @@ void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags); - -#if defined(USE_DIRECT_JUMP) - -#if defined(CONFIG_TCG_INTERPRETER) -static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) -{ - /* patch the branch destination */ - atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); - /* no need to flush icache explicitly */ -} -#elif defined(_ARCH_PPC) -void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); -#define tb_set_jmp_target1 ppc_tb_set_jmp_target -#elif defined(__i386__) || defined(__x86_64__) -static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) -{ - /* patch the branch destination */ - atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); - /* no need to flush icache explicitly */ -} -#elif defined(__s390x__) -static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) -{ - /* patch the branch destination */ - intptr_t disp = addr - (jmp_addr - 2); - atomic_set((int32_t *)jmp_addr, disp / 2); - /* no need to flush icache explicitly */ -} -#elif defined(__aarch64__) -void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); -#define tb_set_jmp_target1 aarch64_tb_set_jmp_target -#elif defined(__sparc__) || defined(__mips__) -void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); -#else -#error tb_set_jmp_target1 is missing -#endif - -static inline void tb_set_jmp_target(TranslationBlock *tb, - int n, uintptr_t addr) -{ - uint16_t offset = tb->jmp_insn_offset[n]; - tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); -} - -#else - -/* set the jump target */ -static inline void tb_set_jmp_target(TranslationBlock *tb, - int n, uintptr_t addr) -{ - tb->jmp_target_addr[n] = addr; -} - -#endif - -/* Called with tb_lock held. */ -static inline void tb_add_jump(TranslationBlock *tb, int n, - TranslationBlock *tb_next) -{ - assert(n < ARRAY_SIZE(tb->jmp_list_next)); - if (tb->jmp_list_next[n]) { - /* Another thread has already done this while we were - * outside of the lock; nothing to do in this case */ - return; - } - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, - "Linking TBs %p [" TARGET_FMT_lx - "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, - tb_next->tc_ptr, tb_next->pc); - - /* patch the native jump address */ - tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); - - /* add in TB jmp circular list */ - tb->jmp_list_next[n] = tb_next->jmp_list_first; - tb_next->jmp_list_first = (uintptr_t)tb | n; -} +void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); /* GETPC is the true target of the return instruction that we'll execute. */ #if defined(CONFIG_TCG_INTERPRETER) diff --git a/include/qemu/sockets.h b/include/qemu/sockets.h index 639cc079d9..4f7311b52a 100644 --- a/include/qemu/sockets.h +++ b/include/qemu/sockets.h @@ -45,7 +45,8 @@ void socket_listen_cleanup(int fd, Error **errp); int socket_dgram(SocketAddress *remote, SocketAddress *local, Error **errp); /* Old, ipv4 only bits. Don't use for new code. */ -int parse_host_port(struct sockaddr_in *saddr, const char *str); +int parse_host_port(struct sockaddr_in *saddr, const char *str, + Error **errp); int socket_init(void); /** diff --git a/include/sysemu/iothread.h b/include/sysemu/iothread.h index e6da1a4087..d2985b30ba 100644 --- a/include/sysemu/iothread.h +++ b/include/sysemu/iothread.h @@ -24,6 +24,9 @@ typedef struct { QemuThread thread; AioContext *ctx; + GMainContext *worker_context; + GMainLoop *main_loop; + GOnce once; QemuMutex init_done_lock; QemuCond init_done_cond; /* is thread initialization done? */ bool stopping; @@ -41,5 +44,6 @@ typedef struct { char *iothread_get_id(IOThread *iothread); AioContext *iothread_get_aio_context(IOThread *iothread); void iothread_stop_all(void); +GMainContext *iothread_get_g_main_context(IOThread *iothread); #endif /* IOTHREAD_H */ diff --git a/iothread.c b/iothread.c index beeb870534..44c8944dc4 100644 --- a/iothread.c +++ b/iothread.c @@ -57,6 +57,23 @@ static void *iothread_run(void *opaque) while (!atomic_read(&iothread->stopping)) { aio_poll(iothread->ctx, true); + + if (atomic_read(&iothread->worker_context)) { + GMainLoop *loop; + + g_main_context_push_thread_default(iothread->worker_context); + iothread->main_loop = + g_main_loop_new(iothread->worker_context, TRUE); + loop = iothread->main_loop; + + g_main_loop_run(iothread->main_loop); + iothread->main_loop = NULL; + g_main_loop_unref(loop); + + g_main_context_pop_thread_default(iothread->worker_context); + g_main_context_unref(iothread->worker_context); + iothread->worker_context = NULL; + } } rcu_unregister_thread(); @@ -73,6 +90,9 @@ static int iothread_stop(Object *object, void *opaque) } iothread->stopping = true; aio_notify(iothread->ctx); + if (atomic_read(&iothread->main_loop)) { + g_main_loop_quit(iothread->main_loop); + } qemu_thread_join(&iothread->thread); return 0; } @@ -125,6 +145,7 @@ static void iothread_complete(UserCreatable *obj, Error **errp) qemu_mutex_init(&iothread->init_done_lock); qemu_cond_init(&iothread->init_done_cond); + iothread->once = (GOnce) G_ONCE_INIT; /* This assumes we are called from a thread with useful CPU affinity for us * to inherit. @@ -309,3 +330,27 @@ void iothread_stop_all(void) object_child_foreach(container, iothread_stop, NULL); } + +static gpointer iothread_g_main_context_init(gpointer opaque) +{ + AioContext *ctx; + IOThread *iothread = opaque; + GSource *source; + + iothread->worker_context = g_main_context_new(); + + ctx = iothread_get_aio_context(iothread); + source = aio_get_g_source(ctx); + g_source_attach(source, iothread->worker_context); + g_source_unref(source); + + aio_notify(iothread->ctx); + return NULL; +} + +GMainContext *iothread_get_g_main_context(IOThread *iothread) +{ + g_once(&iothread->once, iothread_g_main_context_init, iothread); + + return iothread->worker_context; +} diff --git a/net/colo-compare.c b/net/colo-compare.c index 5fe8e3fad9..b3f35d729a 100644 --- a/net/colo-compare.c +++ b/net/colo-compare.c @@ -29,6 +29,7 @@ #include "qemu/sockets.h" #include "qapi-visit.h" #include "net/colo.h" +#include "sysemu/iothread.h" #define TYPE_COLO_COMPARE "colo-compare" #define COLO_COMPARE(obj) \ @@ -41,27 +42,27 @@ #define REGULAR_PACKET_CHECK_MS 3000 /* - + CompareState ++ - | | - +---------------+ +---------------+ +---------------+ - |conn list +--->conn +--------->conn | - +---------------+ +---------------+ +---------------+ - | | | | | | - +---------------+ +---v----+ +---v----+ +---v----+ +---v----+ - |primary | |secondary |primary | |secondary - |packet | |packet + |packet | |packet + - +--------+ +--------+ +--------+ +--------+ - | | | | - +---v----+ +---v----+ +---v----+ +---v----+ - |primary | |secondary |primary | |secondary - |packet | |packet + |packet | |packet + - +--------+ +--------+ +--------+ +--------+ - | | | | - +---v----+ +---v----+ +---v----+ +---v----+ - |primary | |secondary |primary | |secondary - |packet | |packet + |packet | |packet + - +--------+ +--------+ +--------+ +--------+ -*/ + * + CompareState ++ + * | | + * +---------------+ +---------------+ +---------------+ + * | conn list + - > conn + ------- > conn + -- > ...... + * +---------------+ +---------------+ +---------------+ + * | | | | | | + * +---------------+ +---v----+ +---v----+ +---v----+ +---v----+ + * |primary | |secondary |primary | |secondary + * |packet | |packet + |packet | |packet + + * +--------+ +--------+ +--------+ +--------+ + * | | | | + * +---v----+ +---v----+ +---v----+ +---v----+ + * |primary | |secondary |primary | |secondary + * |packet | |packet + |packet | |packet + + * +--------+ +--------+ +--------+ +--------+ + * | | | | + * +---v----+ +---v----+ +---v----+ +---v----+ + * |primary | |secondary |primary | |secondary + * |packet | |packet + |packet | |packet + + * +--------+ +--------+ +--------+ +--------+ + */ typedef struct CompareState { Object parent; @@ -75,18 +76,17 @@ typedef struct CompareState { SocketReadState sec_rs; bool vnet_hdr; - /* connection list: the connections belonged to this NIC could be found - * in this list. - * element type: Connection + /* + * Record the connection that through the NIC + * Element type: Connection */ GQueue conn_list; - /* hashtable to save connection */ + /* Record the connection without repetition */ GHashTable *connection_track_table; - /* compare thread, a thread for each NIC */ - QemuThread thread; + IOThread *iothread; GMainContext *worker_context; - GMainLoop *compare_loop; + QEMUTimer *packet_check_timer; } CompareState; typedef struct CompareClass { @@ -186,7 +186,10 @@ static int packet_enqueue(CompareState *s, int mode) * return: 0 means packet same * > 0 || < 0 means packet different */ -static int colo_packet_compare_common(Packet *ppkt, Packet *spkt, int offset) +static int colo_packet_compare_common(Packet *ppkt, + Packet *spkt, + int poffset, + int soffset) { if (trace_event_get_state_backends(TRACE_COLO_COMPARE_MISCOMPARE)) { char pri_ip_src[20], pri_ip_dst[20], sec_ip_src[20], sec_ip_dst[20]; @@ -201,12 +204,13 @@ static int colo_packet_compare_common(Packet *ppkt, Packet *spkt, int offset) sec_ip_src, sec_ip_dst); } - offset = ppkt->vnet_hdr_len + offset; + poffset = ppkt->vnet_hdr_len + poffset; + soffset = ppkt->vnet_hdr_len + soffset; - if (ppkt->size == spkt->size) { - return memcmp(ppkt->data + offset, - spkt->data + offset, - spkt->size - offset); + if (ppkt->size - poffset == spkt->size - soffset) { + return memcmp(ppkt->data + poffset, + spkt->data + soffset, + spkt->size - soffset); } else { trace_colo_compare_main("Net packet size are not the same"); return -1; @@ -263,13 +267,22 @@ static int colo_packet_compare_tcp(Packet *spkt, Packet *ppkt) * so we just need skip this field. */ if (ptcp->th_off > 5) { - ptrdiff_t tcp_offset; + ptrdiff_t ptcp_offset, stcp_offset; - tcp_offset = ppkt->transport_header - (uint8_t *)ppkt->data - + (ptcp->th_off * 4) - ppkt->vnet_hdr_len; - res = colo_packet_compare_common(ppkt, spkt, tcp_offset); + ptcp_offset = ppkt->transport_header - (uint8_t *)ppkt->data + + (ptcp->th_off * 4) - ppkt->vnet_hdr_len; + stcp_offset = spkt->transport_header - (uint8_t *)spkt->data + + (stcp->th_off * 4) - spkt->vnet_hdr_len; + + /* + * When network is busy, some tcp options(like sack) will unpredictable + * occur in primary side or secondary side. it will make packet size + * not same, but the two packet's payload is identical. colo just + * care about packet payload, so we skip the option field. + */ + res = colo_packet_compare_common(ppkt, spkt, ptcp_offset, stcp_offset); } else if (ptcp->th_sum == stcp->th_sum) { - res = colo_packet_compare_common(ppkt, spkt, ETH_HLEN); + res = colo_packet_compare_common(ppkt, spkt, ETH_HLEN, ETH_HLEN); } else { res = -1; } @@ -330,6 +343,7 @@ static int colo_packet_compare_udp(Packet *spkt, Packet *ppkt) * the ip payload here. */ ret = colo_packet_compare_common(ppkt, spkt, + network_header_length + ETH_HLEN, network_header_length + ETH_HLEN); if (ret) { @@ -367,6 +381,7 @@ static int colo_packet_compare_icmp(Packet *spkt, Packet *ppkt) * the ip payload here. */ if (colo_packet_compare_common(ppkt, spkt, + network_header_length + ETH_HLEN, network_header_length + ETH_HLEN)) { trace_colo_compare_icmp_miscompare("primary pkt size", ppkt->size); @@ -404,7 +419,7 @@ static int colo_packet_compare_other(Packet *spkt, Packet *ppkt) sec_ip_src, sec_ip_dst); } - return colo_packet_compare_common(ppkt, spkt, 0); + return colo_packet_compare_common(ppkt, spkt, 0, 0); } static int colo_old_packet_check_one(Packet *pkt, int64_t *check_time) @@ -430,8 +445,11 @@ static int colo_old_packet_check_one_conn(Connection *conn, (GCompareFunc)colo_old_packet_check_one); if (result) { - /* do checkpoint will flush old packet */ - /* TODO: colo_notify_checkpoint();*/ + /* Do checkpoint will flush old packet */ + /* + * TODO: Notify colo frame to do checkpoint. + * colo_compare_inconsistent_notify(); + */ return 0; } @@ -469,7 +487,7 @@ static void colo_compare_connection(void *opaque, void *user_data) while (!g_queue_is_empty(&conn->primary_list) && !g_queue_is_empty(&conn->secondary_list)) { - pkt = g_queue_pop_tail(&conn->primary_list); + pkt = g_queue_pop_head(&conn->primary_list); switch (conn->ip_proto) { case IPPROTO_TCP: result = g_queue_find_custom(&conn->secondary_list, @@ -507,7 +525,7 @@ static void colo_compare_connection(void *opaque, void *user_data) * until next comparison. */ trace_colo_compare_main("packet different"); - g_queue_push_tail(&conn->primary_list, pkt); + g_queue_push_head(&conn->primary_list, pkt); /* TODO: colo_notify_checkpoint();*/ break; } @@ -597,22 +615,40 @@ static void compare_sec_chr_in(void *opaque, const uint8_t *buf, int size) * Check old packet regularly so it can watch for any packets * that the secondary hasn't produced equivalents of. */ -static gboolean check_old_packet_regular(void *opaque) +static void check_old_packet_regular(void *opaque) { CompareState *s = opaque; /* if have old packet we will notify checkpoint */ colo_old_packet_check(s); + timer_mod(s->packet_check_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + REGULAR_PACKET_CHECK_MS); +} - return TRUE; +static void colo_compare_timer_init(CompareState *s) +{ + AioContext *ctx = iothread_get_aio_context(s->iothread); + + s->packet_check_timer = aio_timer_new(ctx, QEMU_CLOCK_VIRTUAL, + SCALE_MS, check_old_packet_regular, + s); + timer_mod(s->packet_check_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + REGULAR_PACKET_CHECK_MS); } -static void *colo_compare_thread(void *opaque) +static void colo_compare_timer_del(CompareState *s) { - CompareState *s = opaque; - GSource *timeout_source; + if (s->packet_check_timer) { + timer_del(s->packet_check_timer); + timer_free(s->packet_check_timer); + s->packet_check_timer = NULL; + } + } - s->worker_context = g_main_context_new(); +static void colo_compare_iothread(CompareState *s) +{ + object_ref(OBJECT(s->iothread)); + s->worker_context = iothread_get_g_main_context(s->iothread); qemu_chr_fe_set_handlers(&s->chr_pri_in, compare_chr_can_read, compare_pri_chr_in, NULL, NULL, @@ -621,20 +657,7 @@ static void *colo_compare_thread(void *opaque) compare_sec_chr_in, NULL, NULL, s, s->worker_context, true); - s->compare_loop = g_main_loop_new(s->worker_context, FALSE); - - /* To kick any packets that the secondary doesn't match */ - timeout_source = g_timeout_source_new(REGULAR_PACKET_CHECK_MS); - g_source_set_callback(timeout_source, - (GSourceFunc)check_old_packet_regular, s, NULL); - g_source_attach(timeout_source, s->worker_context); - - g_main_loop_run(s->compare_loop); - - g_source_unref(timeout_source); - g_main_loop_unref(s->compare_loop); - g_main_context_unref(s->worker_context); - return NULL; + colo_compare_timer_init(s); } static char *compare_get_pri_indev(Object *obj, Error **errp) @@ -759,12 +782,10 @@ static void colo_compare_complete(UserCreatable *uc, Error **errp) { CompareState *s = COLO_COMPARE(uc); Chardev *chr; - char thread_name[64]; - static int compare_id; - if (!s->pri_indev || !s->sec_indev || !s->outdev) { + if (!s->pri_indev || !s->sec_indev || !s->outdev || !s->iothread) { error_setg(errp, "colo compare needs 'primary_in' ," - "'secondary_in','outdev' property set"); + "'secondary_in','outdev','iothread' property set"); return; } else if (!strcmp(s->pri_indev, s->outdev) || !strcmp(s->sec_indev, s->outdev) || @@ -799,12 +820,7 @@ static void colo_compare_complete(UserCreatable *uc, Error **errp) g_free, connection_destroy); - sprintf(thread_name, "colo-compare %d", compare_id); - qemu_thread_create(&s->thread, thread_name, - colo_compare_thread, s, - QEMU_THREAD_JOINABLE); - compare_id++; - + colo_compare_iothread(s); return; } @@ -848,6 +864,10 @@ static void colo_compare_init(Object *obj) object_property_add_str(obj, "outdev", compare_get_outdev, compare_set_outdev, NULL); + object_property_add_link(obj, "iothread", TYPE_IOTHREAD, + (Object **)&s->iothread, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, NULL); s->vnet_hdr = false; object_property_add_bool(obj, "vnet_hdr_support", compare_get_vnet_hdr, @@ -861,16 +881,21 @@ static void colo_compare_finalize(Object *obj) qemu_chr_fe_deinit(&s->chr_pri_in, false); qemu_chr_fe_deinit(&s->chr_sec_in, false); qemu_chr_fe_deinit(&s->chr_out, false); - - g_main_loop_quit(s->compare_loop); - qemu_thread_join(&s->thread); - + if (s->iothread) { + colo_compare_timer_del(s); + } /* Release all unhandled packets after compare thead exited */ g_queue_foreach(&s->conn_list, colo_flush_packets, s); g_queue_clear(&s->conn_list); - g_hash_table_destroy(s->connection_track_table); + if (s->connection_track_table) { + g_hash_table_destroy(s->connection_track_table); + } + + if (s->iothread) { + object_unref(OBJECT(s->iothread)); + } g_free(s->pri_indev); g_free(s->sec_indev); g_free(s->outdev); diff --git a/net/filter-rewriter.c b/net/filter-rewriter.c index 98120095de..2be388f539 100644 --- a/net/filter-rewriter.c +++ b/net/filter-rewriter.c @@ -99,7 +99,8 @@ static int handle_primary_tcp_pkt(NetFilterState *nf, /* handle packets to the secondary from the primary */ tcp_pkt->th_ack = htonl(ntohl(tcp_pkt->th_ack) + conn->offset); - net_checksum_calculate((uint8_t *)pkt->data, pkt->size); + net_checksum_calculate((uint8_t *)pkt->data + pkt->vnet_hdr_len, + pkt->size - pkt->vnet_hdr_len); } } @@ -138,7 +139,8 @@ static int handle_secondary_tcp_pkt(NetFilterState *nf, /* handle packets to the primary from the secondary*/ tcp_pkt->th_seq = htonl(ntohl(tcp_pkt->th_seq) - conn->offset); - net_checksum_calculate((uint8_t *)pkt->data, pkt->size); + net_checksum_calculate((uint8_t *)pkt->data + pkt->vnet_hdr_len, + pkt->size - pkt->vnet_hdr_len); } } @@ -100,7 +100,8 @@ static int get_str_sep(char *buf, int buf_size, const char **pp, int sep) return 0; } -int parse_host_port(struct sockaddr_in *saddr, const char *str) +int parse_host_port(struct sockaddr_in *saddr, const char *str, + Error **errp) { char buf[512]; struct hostent *he; @@ -108,24 +109,35 @@ int parse_host_port(struct sockaddr_in *saddr, const char *str) int port; p = str; - if (get_str_sep(buf, sizeof(buf), &p, ':') < 0) + if (get_str_sep(buf, sizeof(buf), &p, ':') < 0) { + error_setg(errp, "host address '%s' doesn't contain ':' " + "separating host from port", str); return -1; + } saddr->sin_family = AF_INET; if (buf[0] == '\0') { saddr->sin_addr.s_addr = 0; } else { if (qemu_isdigit(buf[0])) { - if (!inet_aton(buf, &saddr->sin_addr)) + if (!inet_aton(buf, &saddr->sin_addr)) { + error_setg(errp, "host address '%s' is not a valid " + "IPv4 address", buf); return -1; + } } else { - if ((he = gethostbyname(buf)) == NULL) + he = gethostbyname(buf); + if (he == NULL) { + error_setg(errp, "can't resolve host address '%s'", buf); return - 1; + } saddr->sin_addr = *(struct in_addr *)he->h_addr; } } port = strtol(p, (char **)&r, 0); - if (r == p) + if (r == p) { + error_setg(errp, "port number '%s' is invalid", p); return -1; + } saddr->sin_port = htons(port); return 0; } diff --git a/net/socket.c b/net/socket.c index 18af2ab5f3..e6b471c63d 100644 --- a/net/socket.c +++ b/net/socket.c @@ -209,7 +209,9 @@ static void net_socket_send_dgram(void *opaque) } } -static int net_socket_mcast_create(struct sockaddr_in *mcastaddr, struct in_addr *localaddr) +static int net_socket_mcast_create(struct sockaddr_in *mcastaddr, + struct in_addr *localaddr, + Error **errp) { struct ip_mreq imr; int fd; @@ -221,16 +223,16 @@ static int net_socket_mcast_create(struct sockaddr_in *mcastaddr, struct in_addr #endif if (!IN_MULTICAST(ntohl(mcastaddr->sin_addr.s_addr))) { - fprintf(stderr, "qemu: error: specified mcastaddr \"%s\" (0x%08x) " - "does not contain a multicast address\n", - inet_ntoa(mcastaddr->sin_addr), - (int)ntohl(mcastaddr->sin_addr.s_addr)); + error_setg(errp, "specified mcastaddr %s (0x%08x) " + "does not contain a multicast address", + inet_ntoa(mcastaddr->sin_addr), + (int)ntohl(mcastaddr->sin_addr.s_addr)); return -1; - } + fd = qemu_socket(PF_INET, SOCK_DGRAM, 0); if (fd < 0) { - perror("socket(PF_INET, SOCK_DGRAM)"); + error_setg_errno(errp, errno, "can't create datagram socket"); return -1; } @@ -242,13 +244,15 @@ static int net_socket_mcast_create(struct sockaddr_in *mcastaddr, struct in_addr val = 1; ret = qemu_setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val)); if (ret < 0) { - perror("setsockopt(SOL_SOCKET, SO_REUSEADDR)"); + error_setg_errno(errp, errno, + "can't set socket option SO_REUSEADDR"); goto fail; } ret = bind(fd, (struct sockaddr *)mcastaddr, sizeof(*mcastaddr)); if (ret < 0) { - perror("bind"); + error_setg_errno(errp, errno, "can't bind ip=%s to socket", + inet_ntoa(mcastaddr->sin_addr)); goto fail; } @@ -263,7 +267,9 @@ static int net_socket_mcast_create(struct sockaddr_in *mcastaddr, struct in_addr ret = qemu_setsockopt(fd, IPPROTO_IP, IP_ADD_MEMBERSHIP, &imr, sizeof(struct ip_mreq)); if (ret < 0) { - perror("setsockopt(IP_ADD_MEMBERSHIP)"); + error_setg_errno(errp, errno, + "can't add socket to multicast group %s", + inet_ntoa(imr.imr_multiaddr)); goto fail; } @@ -272,7 +278,8 @@ static int net_socket_mcast_create(struct sockaddr_in *mcastaddr, struct in_addr ret = qemu_setsockopt(fd, IPPROTO_IP, IP_MULTICAST_LOOP, &loop, sizeof(loop)); if (ret < 0) { - perror("setsockopt(SOL_IP, IP_MULTICAST_LOOP)"); + error_setg_errno(errp, errno, + "can't force multicast message to loopback"); goto fail; } @@ -281,7 +288,8 @@ static int net_socket_mcast_create(struct sockaddr_in *mcastaddr, struct in_addr ret = qemu_setsockopt(fd, IPPROTO_IP, IP_MULTICAST_IF, localaddr, sizeof(*localaddr)); if (ret < 0) { - perror("setsockopt(IP_MULTICAST_IF)"); + error_setg_errno(errp, errno, + "can't set the default network send interface"); goto fail; } } @@ -321,7 +329,8 @@ static NetSocketState *net_socket_fd_init_dgram(NetClientState *peer, const char *model, const char *name, int fd, int is_connected, - const char *mcast) + const char *mcast, + Error **errp) { struct sockaddr_in saddr; int newfd; @@ -334,22 +343,17 @@ static NetSocketState *net_socket_fd_init_dgram(NetClientState *peer, */ if (is_connected && mcast != NULL) { - if (parse_host_port(&saddr, mcast) < 0) { - fprintf(stderr, - "qemu: error: init_dgram: fd=%d failed parse_host_port()\n", - fd); + if (parse_host_port(&saddr, mcast, errp) < 0) { goto err; } /* must be bound */ if (saddr.sin_addr.s_addr == 0) { - fprintf(stderr, "qemu: error: init_dgram: fd=%d unbound, " - "cannot setup multicast dst addr\n", fd); + error_setg(errp, "can't setup multicast destination address"); goto err; } /* clone dgram socket */ - newfd = net_socket_mcast_create(&saddr, NULL); + newfd = net_socket_mcast_create(&saddr, NULL, errp); if (newfd < 0) { - /* error already reported by net_socket_mcast_create() */ goto err; } /* clone newfd to fd, close newfd */ @@ -431,26 +435,27 @@ static NetSocketState *net_socket_fd_init_stream(NetClientState *peer, static NetSocketState *net_socket_fd_init(NetClientState *peer, const char *model, const char *name, - int fd, int is_connected, const char *mc) + int fd, int is_connected, + const char *mc, Error **errp) { int so_type = -1, optlen=sizeof(so_type); if(getsockopt(fd, SOL_SOCKET, SO_TYPE, (char *)&so_type, (socklen_t *)&optlen)< 0) { - fprintf(stderr, "qemu: error: getsockopt(SO_TYPE) for fd=%d failed\n", - fd); + error_setg(errp, "can't get socket option SO_TYPE"); closesocket(fd); return NULL; } switch(so_type) { case SOCK_DGRAM: - return net_socket_fd_init_dgram(peer, model, name, fd, is_connected, mc); + return net_socket_fd_init_dgram(peer, model, name, fd, is_connected, + mc, errp); case SOCK_STREAM: return net_socket_fd_init_stream(peer, model, name, fd, is_connected); default: - /* who knows ... this could be a eg. a pty, do warn and continue as stream */ - fprintf(stderr, "qemu: warning: socket type=%d for fd=%d is not SOCK_DGRAM or SOCK_STREAM\n", so_type, fd); - return net_socket_fd_init_stream(peer, model, name, fd, is_connected); + error_report("socket type=%d for fd=%d must be either" + " SOCK_DGRAM or SOCK_STREAM", so_type, fd); + closesocket(fd); } return NULL; } @@ -484,19 +489,21 @@ static void net_socket_accept(void *opaque) static int net_socket_listen_init(NetClientState *peer, const char *model, const char *name, - const char *host_str) + const char *host_str, + Error **errp) { NetClientState *nc; NetSocketState *s; struct sockaddr_in saddr; int fd, ret; - if (parse_host_port(&saddr, host_str) < 0) + if (parse_host_port(&saddr, host_str, errp) < 0) { return -1; + } fd = qemu_socket(PF_INET, SOCK_STREAM, 0); if (fd < 0) { - perror("socket"); + error_setg_errno(errp, errno, "can't create stream socket"); return -1; } qemu_set_nonblock(fd); @@ -505,13 +512,14 @@ static int net_socket_listen_init(NetClientState *peer, ret = bind(fd, (struct sockaddr *)&saddr, sizeof(saddr)); if (ret < 0) { - perror("bind"); + error_setg_errno(errp, errno, "can't bind ip=%s to socket", + inet_ntoa(saddr.sin_addr)); closesocket(fd); return -1; } ret = listen(fd, 0); if (ret < 0) { - perror("listen"); + error_setg_errno(errp, errno, "can't listen on socket"); closesocket(fd); return -1; } @@ -530,18 +538,20 @@ static int net_socket_listen_init(NetClientState *peer, static int net_socket_connect_init(NetClientState *peer, const char *model, const char *name, - const char *host_str) + const char *host_str, + Error **errp) { NetSocketState *s; int fd, connected, ret; struct sockaddr_in saddr; - if (parse_host_port(&saddr, host_str) < 0) + if (parse_host_port(&saddr, host_str, errp) < 0) { return -1; + } fd = qemu_socket(PF_INET, SOCK_STREAM, 0); if (fd < 0) { - perror("socket"); + error_setg_errno(errp, errno, "can't create stream socket"); return -1; } qemu_set_nonblock(fd); @@ -557,7 +567,7 @@ static int net_socket_connect_init(NetClientState *peer, errno == EINVAL) { break; } else { - perror("connect"); + error_setg_errno(errp, errno, "can't connect socket"); closesocket(fd); return -1; } @@ -566,9 +576,11 @@ static int net_socket_connect_init(NetClientState *peer, break; } } - s = net_socket_fd_init(peer, model, name, fd, connected, NULL); - if (!s) + s = net_socket_fd_init(peer, model, name, fd, connected, NULL, errp); + if (!s) { return -1; + } + snprintf(s->nc.info_str, sizeof(s->nc.info_str), "socket: connect to %s:%d", inet_ntoa(saddr.sin_addr), ntohs(saddr.sin_port)); @@ -579,31 +591,38 @@ static int net_socket_mcast_init(NetClientState *peer, const char *model, const char *name, const char *host_str, - const char *localaddr_str) + const char *localaddr_str, + Error **errp) { NetSocketState *s; int fd; struct sockaddr_in saddr; struct in_addr localaddr, *param_localaddr; - if (parse_host_port(&saddr, host_str) < 0) + if (parse_host_port(&saddr, host_str, errp) < 0) { return -1; + } if (localaddr_str != NULL) { - if (inet_aton(localaddr_str, &localaddr) == 0) + if (inet_aton(localaddr_str, &localaddr) == 0) { + error_setg(errp, "localaddr '%s' is not a valid IPv4 address", + localaddr_str); return -1; + } param_localaddr = &localaddr; } else { param_localaddr = NULL; } - fd = net_socket_mcast_create(&saddr, param_localaddr); - if (fd < 0) + fd = net_socket_mcast_create(&saddr, param_localaddr, errp); + if (fd < 0) { return -1; + } - s = net_socket_fd_init(peer, model, name, fd, 0, NULL); - if (!s) + s = net_socket_fd_init(peer, model, name, fd, 0, NULL, errp); + if (!s) { return -1; + } s->dgram_dst = saddr; @@ -618,40 +637,44 @@ static int net_socket_udp_init(NetClientState *peer, const char *model, const char *name, const char *rhost, - const char *lhost) + const char *lhost, + Error **errp) { NetSocketState *s; int fd, ret; struct sockaddr_in laddr, raddr; - if (parse_host_port(&laddr, lhost) < 0) { + if (parse_host_port(&laddr, lhost, errp) < 0) { return -1; } - if (parse_host_port(&raddr, rhost) < 0) { + if (parse_host_port(&raddr, rhost, errp) < 0) { return -1; } fd = qemu_socket(PF_INET, SOCK_DGRAM, 0); if (fd < 0) { - perror("socket(PF_INET, SOCK_DGRAM)"); + error_setg_errno(errp, errno, "can't create datagram socket"); return -1; } ret = socket_set_fast_reuse(fd); if (ret < 0) { + error_setg_errno(errp, errno, + "can't set socket option SO_REUSEADDR"); closesocket(fd); return -1; } ret = bind(fd, (struct sockaddr *)&laddr, sizeof(laddr)); if (ret < 0) { - perror("bind"); + error_setg_errno(errp, errno, "can't bind ip=%s to socket", + inet_ntoa(laddr.sin_addr)); closesocket(fd); return -1; } qemu_set_nonblock(fd); - s = net_socket_fd_init(peer, model, name, fd, 0, NULL); + s = net_socket_fd_init(peer, model, name, fd, 0, NULL, errp); if (!s) { return -1; } @@ -667,8 +690,6 @@ static int net_socket_udp_init(NetClientState *peer, int net_init_socket(const Netdev *netdev, const char *name, NetClientState *peer, Error **errp) { - /* FIXME error_setg(errp, ...) on failure */ - Error *err = NULL; const NetdevSocketOptions *sock; assert(netdev->type == NET_CLIENT_DRIVER_SOCKET); @@ -676,41 +697,42 @@ int net_init_socket(const Netdev *netdev, const char *name, if (sock->has_listen + sock->has_connect + sock->has_mcast + sock->has_udp > 1) { - error_report("exactly one of listen=, connect=, mcast= or udp=" - " is required"); + error_setg(errp, "exactly one of listen=, connect=, mcast= or udp=" + " is required"); return -1; } if (sock->has_localaddr && !sock->has_mcast && !sock->has_udp) { - error_report("localaddr= is only valid with mcast= or udp="); + error_setg(errp, "localaddr= is only valid with mcast= or udp="); return -1; } if (sock->has_fd) { int fd; - fd = monitor_fd_param(cur_mon, sock->fd, &err); + fd = monitor_fd_param(cur_mon, sock->fd, errp); if (fd == -1) { - error_report_err(err); return -1; } qemu_set_nonblock(fd); - if (!net_socket_fd_init(peer, "socket", name, fd, 1, sock->mcast)) { + if (!net_socket_fd_init(peer, "socket", name, fd, 1, sock->mcast, + errp)) { return -1; } return 0; } if (sock->has_listen) { - if (net_socket_listen_init(peer, "socket", name, sock->listen) == -1) { + if (net_socket_listen_init(peer, "socket", name, sock->listen, errp) + < 0) { return -1; } return 0; } if (sock->has_connect) { - if (net_socket_connect_init(peer, "socket", name, sock->connect) == - -1) { + if (net_socket_connect_init(peer, "socket", name, sock->connect, errp) + < 0) { return -1; } return 0; @@ -720,7 +742,7 @@ int net_init_socket(const Netdev *netdev, const char *name, /* if sock->localaddr is missing, it has been initialized to "all bits * zero" */ if (net_socket_mcast_init(peer, "socket", name, sock->mcast, - sock->localaddr) == -1) { + sock->localaddr, errp) < 0) { return -1; } return 0; @@ -728,11 +750,11 @@ int net_init_socket(const Netdev *netdev, const char *name, assert(sock->has_udp); if (!sock->has_localaddr) { - error_report("localaddr= is mandatory with udp="); + error_setg(errp, "localaddr= is mandatory with udp="); return -1; } - if (net_socket_udp_init(peer, "socket", name, sock->udp, sock->localaddr) == - -1) { + if (net_socket_udp_init(peer, "socket", name, sock->udp, sock->localaddr, + errp) < 0) { return -1; } return 0; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 1ea597b9dd..e6c6aabdf0 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -297,7 +297,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault; #else - cc->do_unassigned_access = alpha_cpu_unassigned_access; + cc->do_transaction_failed = alpha_cpu_do_transaction_failed; cc->do_unaligned_access = alpha_cpu_do_unaligned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; dc->vmsd = &vmstate_alpha_cpu; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 0738e97d6d..6ae240969b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -486,9 +486,11 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); #ifndef CONFIG_USER_ONLY -QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, - int unused, unsigned size); +void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); #endif static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 34121f4cad..36407f77f5 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -163,6 +163,14 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, pt = env->ptbr; + /* TODO: rather than using ldq_phys() to read the page table we should + * use address_space_ldq() so that we can handle the case when + * the page table read gives a bus fault, rather than ignoring it. + * For the existing code the zero data that ldq_phys will return for + * an access to invalid memory will result in our treating the page + * table as invalid, which may even be the right behaviour. + */ + /* L1 page table read. */ index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff; L1pte = ldq_phys(cs->as, pt + index*8); diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 78a7d45590..3c06baa93a 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -49,22 +49,23 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, cpu_loop_exit(cs); } -void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size) +void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; + if (retaddr) { + cpu_restore_state(cs, retaddr); + } + env->trap_arg0 = addr; - env->trap_arg1 = is_write ? 1 : 0; + env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; cs->exception_index = EXCP_MCHK; env->error_code = 0; - - /* ??? We should cpu_restore_state to the faulting insn, but this hook - does not have access to the retaddr value from the original helper. - It's all moot until the QEMU PALcode grows an MCHK handler. */ - cpu_loop_exit(cs); } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index f465752208..5a92c4accb 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -25,11 +25,10 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "trace-tcg.h" +#include "exec/translator.h" #include "exec/log.h" @@ -44,8 +43,8 @@ typedef struct DisasContext DisasContext; struct DisasContext { - struct TranslationBlock *tb; - uint64_t pc; + DisasContextBase base; + #ifndef CONFIG_USER_ONLY uint64_t palbr; #endif @@ -69,36 +68,14 @@ struct DisasContext { TCGv sink; /* Temporary for immediate constants. */ TCGv lit; - - bool singlestep_enabled; }; -/* Return values from translate_one, indicating the state of the TB. - Note that zero indicates that we are not exiting the TB. */ - -typedef enum { - NO_EXIT, - - /* We have emitted one or more goto_tb. No fixup required. */ - EXIT_GOTO_TB, - - /* We are not using a goto_tb (for whatever reason), but have updated - the PC (for whatever reason), so there's no need to do it again on - exiting the TB. */ - EXIT_PC_UPDATED, - EXIT_PC_UPDATED_NOCHAIN, - - /* We are exiting the TB, but have neither emitted a goto_tb, nor - updated the PC for the next instruction to be executed. */ - EXIT_PC_STALE, - - /* We are exiting the TB due to page crossing or space constraints. */ - EXIT_FALLTHRU, - - /* We are ending the TB with a noreturn function call, e.g. longjmp. - No following code will be executed. */ - EXIT_NORETURN, -} ExitStatus; +/* Target-specific return values from translate_one, indicating the + state of the TB. Note that DISAS_NEXT indicates that we are not + exiting the TB. */ +#define DISAS_PC_UPDATED_NOCHAIN DISAS_TARGET_0 +#define DISAS_PC_UPDATED DISAS_TARGET_1 +#define DISAS_PC_STALE DISAS_TARGET_2 /* global register indexes */ static TCGv_env cpu_env; @@ -301,14 +278,14 @@ static void gen_excp_1(int exception, int error_code) tcg_temp_free_i32(tmp1); } -static ExitStatus gen_excp(DisasContext *ctx, int exception, int error_code) +static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code) { - tcg_gen_movi_i64(cpu_pc, ctx->pc); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); gen_excp_1(exception, error_code); - return EXIT_NORETURN; + return DISAS_NORETURN; } -static inline ExitStatus gen_invalid(DisasContext *ctx) +static inline DisasJumpType gen_invalid(DisasContext *ctx) { return gen_excp(ctx, EXCP_OPCDEC, 0); } @@ -434,9 +411,9 @@ static inline void gen_store_mem(DisasContext *ctx, tcg_temp_free(tmp); } -static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, - int32_t disp16, int mem_idx, - TCGMemOp op) +static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb, + int32_t disp16, int mem_idx, + TCGMemOp op) { TCGLabel *lab_fail, *lab_done; TCGv addr, val; @@ -468,7 +445,7 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, gen_set_label(lab_done); tcg_gen_movi_i64(cpu_lock_addr, -1); - return NO_EXIT; + return DISAS_NEXT; } static bool in_superpage(DisasContext *ctx, int64_t addr) @@ -484,8 +461,8 @@ static bool in_superpage(DisasContext *ctx, int64_t addr) static bool use_exit_tb(DisasContext *ctx) { - return ((ctx->tb->cflags & CF_LAST_IO) - || ctx->singlestep_enabled + return ((ctx->base.tb->cflags & CF_LAST_IO) + || ctx->base.singlestep_enabled || singlestep); } @@ -501,18 +478,18 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t dest) return true; } /* Check for the dest on the same page as the start of the TB. */ - return ((ctx->tb->pc ^ dest) & TARGET_PAGE_MASK) == 0; + return ((ctx->base.tb->pc ^ dest) & TARGET_PAGE_MASK) == 0; #else return true; #endif } -static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp) +static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) { - uint64_t dest = ctx->pc + (disp << 2); + uint64_t dest = ctx->base.pc_next + (disp << 2); if (ra != 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->pc); + tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); } /* Notice branch-to-next; used to initialize RA with the PC. */ @@ -521,53 +498,53 @@ static ExitStatus gen_bdirect(DisasContext *ctx, int ra, int32_t disp) } else if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb); - return EXIT_GOTO_TB; + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); + return DISAS_NORETURN; } else { tcg_gen_movi_i64(cpu_pc, dest); - return EXIT_PC_UPDATED; + return DISAS_PC_UPDATED; } } -static ExitStatus gen_bcond_internal(DisasContext *ctx, TCGCond cond, - TCGv cmp, int32_t disp) +static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond, + TCGv cmp, int32_t disp) { - uint64_t dest = ctx->pc + (disp << 2); + uint64_t dest = ctx->base.pc_next + (disp << 2); TCGLabel *lab_true = gen_new_label(); if (use_goto_tb(ctx, dest)) { tcg_gen_brcondi_i64(cond, cmp, 0, lab_true); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, ctx->pc); - tcg_gen_exit_tb((uintptr_t)ctx->tb); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); gen_set_label(lab_true); tcg_gen_goto_tb(1); tcg_gen_movi_i64(cpu_pc, dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb + 1); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + 1); - return EXIT_GOTO_TB; + return DISAS_NORETURN; } else { TCGv_i64 z = tcg_const_i64(0); TCGv_i64 d = tcg_const_i64(dest); - TCGv_i64 p = tcg_const_i64(ctx->pc); + TCGv_i64 p = tcg_const_i64(ctx->base.pc_next); tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p); tcg_temp_free_i64(z); tcg_temp_free_i64(d); tcg_temp_free_i64(p); - return EXIT_PC_UPDATED; + return DISAS_PC_UPDATED; } } -static ExitStatus gen_bcond(DisasContext *ctx, TCGCond cond, int ra, - int32_t disp, int mask) +static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra, + int32_t disp, int mask) { if (mask) { TCGv tmp = tcg_temp_new(); - ExitStatus ret; + DisasJumpType ret; tcg_gen_andi_i64(tmp, load_gpr(ctx, ra), 1); ret = gen_bcond_internal(ctx, cond, tmp, disp); @@ -609,11 +586,11 @@ static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src) } } -static ExitStatus gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, - int32_t disp) +static DisasJumpType gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, + int32_t disp) { TCGv cmp_tmp = tcg_temp_new(); - ExitStatus ret; + DisasJumpType ret; gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra)); ret = gen_bcond_internal(ctx, cond, cmp_tmp, disp); @@ -1159,7 +1136,7 @@ static void gen_rx(DisasContext *ctx, int ra, int set) tcg_temp_free(tmp); } -static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) +static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) { /* We're emulating OSF/1 PALcode. Many of these are trivial access to internal cpu registers. */ @@ -1185,7 +1162,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) palcode &= 0xbf; goto do_call_pal; } - return NO_EXIT; + return DISAS_NEXT; } #ifndef CONFIG_USER_ONLY @@ -1231,8 +1208,8 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) } /* Allow interrupts to be recognized right away. */ - tcg_gen_movi_i64(cpu_pc, ctx->pc); - return EXIT_PC_UPDATED_NOCHAIN; + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + return DISAS_PC_UPDATED_NOCHAIN; case 0x36: /* RDPS */ @@ -1270,7 +1247,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) palcode &= 0x3f; goto do_call_pal; } - return NO_EXIT; + return DISAS_NEXT; } #endif return gen_invalid(ctx); @@ -1281,7 +1258,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) #else { TCGv tmp = tcg_temp_new(); - uint64_t exc_addr = ctx->pc; + uint64_t exc_addr = ctx->base.pc_next; uint64_t entry = ctx->palbr; if (ctx->tbflags & ENV_FLAG_PAL_MODE) { @@ -1306,11 +1283,11 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) if (!use_exit_tb(ctx)) { tcg_gen_goto_tb(0); tcg_gen_movi_i64(cpu_pc, entry); - tcg_gen_exit_tb((uintptr_t)ctx->tb); - return EXIT_GOTO_TB; + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); + return DISAS_NORETURN; } else { tcg_gen_movi_i64(cpu_pc, entry); - return EXIT_PC_UPDATED; + return DISAS_PC_UPDATED; } } #endif @@ -1344,7 +1321,7 @@ static int cpu_pr_data(int pr) return 0; } -static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) +static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno) { void (*helper)(TCGv); int data; @@ -1366,7 +1343,7 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) gen_io_start(); helper(va); gen_io_end(); - return EXIT_PC_STALE; + return DISAS_PC_STALE; } else { helper(va); } @@ -1393,10 +1370,10 @@ static ExitStatus gen_mfpr(DisasContext *ctx, TCGv va, int regno) break; } - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) +static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno) { int data; @@ -1424,7 +1401,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) case 252: /* HALT */ gen_helper_halt(vb); - return EXIT_PC_STALE; + return DISAS_PC_STALE; case 251: /* ALARM */ @@ -1438,7 +1415,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) that ended with a CALL_PAL. Since the base register usually only changes during boot, flushing everything works well. */ gen_helper_tb_flush(cpu_env); - return EXIT_PC_STALE; + return DISAS_PC_STALE; case 32 ... 39: /* Accessing the "non-shadow" general registers. */ @@ -1467,7 +1444,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) break; } - return NO_EXIT; + return DISAS_NEXT; } #endif /* !USER_ONLY*/ @@ -1499,7 +1476,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno) } \ } while (0) -static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) +static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) { int32_t disp21, disp16, disp12 __attribute__((unused)); uint16_t fn11; @@ -1507,7 +1484,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) bool islit, real_islit; TCGv va, vb, vc, tmp, tmp2; TCGv_i32 t32; - ExitStatus ret; + DisasJumpType ret; /* Decode all instruction fields */ opc = extract32(insn, 26, 6); @@ -1530,7 +1507,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) lit = 0; } - ret = NO_EXIT; + ret = DISAS_NEXT; switch (opc) { case 0x00: /* CALL_PAL */ @@ -2428,11 +2405,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) case 0xC000: /* RPCC */ va = dest_gpr(ctx, ra); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (ctx->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); - ret = EXIT_PC_STALE; + ret = DISAS_PC_STALE; } else { gen_helper_load_pcc(va, cpu_env); } @@ -2478,9 +2455,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) vb = load_gpr(ctx, rb); tcg_gen_andi_i64(cpu_pc, vb, ~3); if (ra != 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->pc); + tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); } - ret = EXIT_PC_UPDATED; + ret = DISAS_PC_UPDATED; break; case 0x1B: @@ -2738,7 +2715,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) tcg_temp_free(tmp); tcg_gen_andi_i64(cpu_pc, vb, ~3); /* Allow interrupts to be recognized right away. */ - ret = EXIT_PC_UPDATED_NOCHAIN; + ret = DISAS_PC_UPDATED_NOCHAIN; break; #else goto invalid_opc; @@ -2952,32 +2929,23 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) return ret; } -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static int alpha_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUAlphaState *env = cs->env_ptr; - DisasContext ctx, *ctxp = &ctx; - target_ulong pc_start; - target_ulong pc_mask; - uint32_t insn; - ExitStatus ret; - int num_insns; - int max_insns; - - pc_start = tb->pc; + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUAlphaState *env = cpu->env_ptr; + int64_t bound, mask; - ctx.tb = tb; - ctx.pc = pc_start; - ctx.tbflags = tb->flags; - ctx.mem_idx = cpu_mmu_index(env, false); - ctx.implver = env->implver; - ctx.amask = env->amask; - ctx.singlestep_enabled = cs->singlestep_enabled; + ctx->tbflags = ctx->base.tb->flags; + ctx->mem_idx = cpu_mmu_index(env, false); + ctx->implver = env->implver; + ctx->amask = env->amask; #ifdef CONFIG_USER_ONLY - ctx.ir = cpu_std_ir; + ctx->ir = cpu_std_ir; #else - ctx.palbr = env->palbr; - ctx.ir = (ctx.tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); + ctx->palbr = env->palbr; + ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir); #endif /* ??? Every TB begins with unset rounding mode, to be initialized on @@ -2986,96 +2954,87 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) to reset the FP_STATUS to that default at the end of any TB that changes the default. We could even (gasp) dynamiclly figure out what default would be most efficient given the running program. */ - ctx.tb_rm = -1; + ctx->tb_rm = -1; /* Similarly for flush-to-zero. */ - ctx.tb_ftz = -1; + ctx->tb_ftz = -1; - TCGV_UNUSED_I64(ctx.zero); - TCGV_UNUSED_I64(ctx.sink); - TCGV_UNUSED_I64(ctx.lit); + TCGV_UNUSED_I64(ctx->zero); + TCGV_UNUSED_I64(ctx->sink); + TCGV_UNUSED_I64(ctx->lit); - num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - - if (in_superpage(&ctx, pc_start)) { - pc_mask = (1ULL << 41) - 1; + /* Bound the number of insns to execute to those left on the page. */ + if (in_superpage(ctx, ctx->base.pc_first)) { + mask = -1ULL << 41; } else { - pc_mask = ~TARGET_PAGE_MASK; + mask = TARGET_PAGE_MASK; } + bound = -(ctx->base.pc_first | mask) / 4; - gen_tb_start(tb); - tcg_clear_temp_count(); + return MIN(max_insns, bound); +} - do { - tcg_gen_insn_start(ctx.pc); - num_insns++; +static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { - ret = gen_excp(&ctx, EXCP_DEBUG, 0); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.pc += 4; - break; - } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - insn = cpu_ldl_code(env, ctx.pc); +static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + tcg_gen_insn_start(dcbase->pc_next); +} - ctx.pc += 4; - ret = translate_one(ctxp, insn); - free_context_temps(ctxp); +static bool alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); - if (tcg_check_temp_count()) { - qemu_log("TCG temporary leak before "TARGET_FMT_lx"\n", ctx.pc); - } + ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG, 0); - /* If we reach a page boundary, are single stepping, - or exhaust instruction count, stop generation. */ - if (ret == NO_EXIT - && ((ctx.pc & pc_mask) == 0 - || tcg_op_buf_full() - || num_insns >= max_insns - || singlestep - || ctx.singlestep_enabled)) { - ret = EXIT_FALLTHRU; - } - } while (ret == NO_EXIT); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next += 4; + return true; +} - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); - } +static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUAlphaState *env = cpu->env_ptr; + uint32_t insn = cpu_ldl_code(env, ctx->base.pc_next); + + ctx->base.pc_next += 4; + ctx->base.is_jmp = translate_one(ctx, insn); + + free_context_temps(ctx); + translator_loop_temp_check(&ctx->base); +} + +static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); - switch (ret) { - case EXIT_GOTO_TB: - case EXIT_NORETURN: + switch (ctx->base.is_jmp) { + case DISAS_NORETURN: break; - case EXIT_FALLTHRU: - if (use_goto_tb(&ctx, ctx.pc)) { + case DISAS_TOO_MANY: + if (use_goto_tb(ctx, ctx->base.pc_next)) { tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, ctx.pc); - tcg_gen_exit_tb((uintptr_t)ctx.tb); + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb); } /* FALLTHRU */ - case EXIT_PC_STALE: - tcg_gen_movi_i64(cpu_pc, ctx.pc); + case DISAS_PC_STALE: + tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); /* FALLTHRU */ - case EXIT_PC_UPDATED: - if (!use_exit_tb(&ctx)) { + case DISAS_PC_UPDATED: + if (!use_exit_tb(ctx)) { tcg_gen_lookup_and_goto_ptr(cpu_pc); break; } /* FALLTHRU */ - case EXIT_PC_UPDATED_NOCHAIN: - if (ctx.singlestep_enabled) { + case DISAS_PC_UPDATED_NOCHAIN: + if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG, 0); } else { tcg_gen_exit_tb(0); @@ -3084,22 +3043,28 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) default: g_assert_not_reached(); } +} - gen_tb_end(tb, num_insns); - - tb->size = ctx.pc - pc_start; - tb->icount = num_insns; +static void alpha_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size, 1); +} + +static const TranslatorOps alpha_tr_ops = { + .init_disas_context = alpha_tr_init_disas_context, + .tb_start = alpha_tr_tb_start, + .insn_start = alpha_tr_insn_start, + .breakpoint_check = alpha_tr_breakpoint_check, + .translate_insn = alpha_tr_translate_insn, + .tb_stop = alpha_tr_tb_stop, + .disas_log = alpha_tr_disas_log, +}; -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 1); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; + translator_loop(&alpha_tr_ops, &dc.base, cpu, tb); } void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 900870cd5a..b6e2652341 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -24,10 +24,9 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - +#include "exec/translator.h" #include "trace-tcg.h" #include "exec/log.h" @@ -39,7 +38,7 @@ typedef struct DisasCond { } DisasCond; typedef struct DisasContext { - struct TranslationBlock *tb; + DisasContextBase base; CPUState *cs; target_ulong iaoq_f; @@ -53,36 +52,25 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; - bool singlestep_enabled; bool psw_n_nonzero; } DisasContext; -/* Return values from translate_one, indicating the state of the TB. - Note that zero indicates that we are not exiting the TB. */ - -typedef enum { - NO_EXIT, - - /* We have emitted one or more goto_tb. No fixup required. */ - EXIT_GOTO_TB, - - /* We are not using a goto_tb (for whatever reason), but have updated - the iaq (for whatever reason), so don't do it again on exit. */ - EXIT_IAQ_N_UPDATED, +/* Target-specific return values from translate_one, indicating the + state of the TB. Note that DISAS_NEXT indicates that we are not + exiting the TB. */ - /* We are exiting the TB, but have neither emitted a goto_tb, nor - updated the iaq for the next instruction to be executed. */ - EXIT_IAQ_N_STALE, +/* We are not using a goto_tb (for whatever reason), but have updated + the iaq (for whatever reason), so don't do it again on exit. */ +#define DISAS_IAQ_N_UPDATED DISAS_TARGET_0 - /* We are ending the TB with a noreturn function call, e.g. longjmp. - No following code will be executed. */ - EXIT_NORETURN, -} ExitStatus; +/* We are exiting the TB, but have neither emitted a goto_tb, nor + updated the iaq for the next instruction to be executed. */ +#define DISAS_IAQ_N_STALE DISAS_TARGET_1 typedef struct DisasInsn { uint32_t insn, mask; - ExitStatus (*trans)(DisasContext *ctx, uint32_t insn, - const struct DisasInsn *f); + DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, + const struct DisasInsn *f); union { void (*ttt)(TCGv, TCGv, TCGv); void (*weww)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32); @@ -415,7 +403,7 @@ static void nullify_set(DisasContext *ctx, bool x) /* Mark the end of an instruction that may have been nullified. This is the pair to nullify_over. */ -static ExitStatus nullify_end(DisasContext *ctx, ExitStatus status) +static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) { TCGLabel *null_lab = ctx->null_lab; @@ -441,9 +429,9 @@ static ExitStatus nullify_end(DisasContext *ctx, ExitStatus status) ctx->null_cond = cond_make_n(); } - assert(status != EXIT_GOTO_TB && status != EXIT_IAQ_N_UPDATED); - if (status == EXIT_NORETURN) { - status = NO_EXIT; + assert(status != DISAS_NORETURN && status != DISAS_IAQ_N_UPDATED); + if (status == DISAS_NORETURN) { + status = DISAS_NEXT; } return status; } @@ -469,16 +457,16 @@ static void gen_excp_1(int exception) tcg_temp_free_i32(t); } -static ExitStatus gen_excp(DisasContext *ctx, int exception) +static DisasJumpType gen_excp(DisasContext *ctx, int exception) { copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); gen_excp_1(exception); - return EXIT_NORETURN; + return DISAS_NORETURN; } -static ExitStatus gen_illegal(DisasContext *ctx) +static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); return nullify_end(ctx, gen_excp(ctx, EXCP_SIGILL)); @@ -487,7 +475,7 @@ static ExitStatus gen_illegal(DisasContext *ctx) static bool use_goto_tb(DisasContext *ctx, target_ulong dest) { /* Suppress goto_tb in the case of single-steping and IO. */ - if ((ctx->tb->cflags & CF_LAST_IO) || ctx->singlestep_enabled) { + if ((ctx->base.tb->cflags & CF_LAST_IO) || ctx->base.singlestep_enabled) { return false; } return true; @@ -510,11 +498,11 @@ static void gen_goto_tb(DisasContext *ctx, int which, tcg_gen_goto_tb(which); tcg_gen_movi_tl(cpu_iaoq_f, f); tcg_gen_movi_tl(cpu_iaoq_b, b); - tcg_gen_exit_tb((uintptr_t)ctx->tb + which); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); @@ -839,9 +827,9 @@ static TCGv do_sub_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2) return sv; } -static ExitStatus do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, - unsigned shift, bool is_l, bool is_tsv, bool is_tc, - bool is_c, unsigned cf) +static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, + unsigned shift, bool is_l, bool is_tsv, bool is_tc, + bool is_c, unsigned cf) { TCGv dest, cb, cb_msb, sv, tmp; unsigned c = cf >> 1; @@ -908,11 +896,11 @@ static ExitStatus do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, /* Install the new nullification. */ cond_free(&ctx->null_cond); ctx->null_cond = cond; - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, - bool is_tsv, bool is_b, bool is_tc, unsigned cf) +static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, + bool is_tsv, bool is_b, bool is_tc, unsigned cf) { TCGv dest, sv, cb, cb_msb, zero, tmp; unsigned c = cf >> 1; @@ -974,11 +962,11 @@ static ExitStatus do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, /* Install the new nullification. */ cond_free(&ctx->null_cond); ctx->null_cond = cond; - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf) +static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, + TCGv in2, unsigned cf) { TCGv dest, sv; DisasCond cond; @@ -1003,11 +991,11 @@ static ExitStatus do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, /* Install the new nullification. */ cond_free(&ctx->null_cond); ctx->null_cond = cond; - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, - unsigned cf, void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, + unsigned cf, void (*fn)(TCGv, TCGv, TCGv)) { TCGv dest = dest_gpr(ctx, rt); @@ -1020,12 +1008,12 @@ static ExitStatus do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2, if (cf) { ctx->null_cond = do_log_cond(cf, dest); } - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus do_unit(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf, bool is_tc, - void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, + TCGv in2, unsigned cf, bool is_tc, + void (*fn)(TCGv, TCGv, TCGv)) { TCGv dest; DisasCond cond; @@ -1053,7 +1041,7 @@ static ExitStatus do_unit(DisasContext *ctx, unsigned rt, TCGv in1, cond_free(&ctx->null_cond); ctx->null_cond = cond; } - return NO_EXIT; + return DISAS_NEXT; } /* Emit a memory load. The modify parameter should be @@ -1185,9 +1173,9 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, #define do_store_tl do_store_32 #endif -static ExitStatus do_load(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify, TCGMemOp mop) +static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify, TCGMemOp mop) { TCGv dest; @@ -1203,12 +1191,12 @@ static ExitStatus do_load(DisasContext *ctx, unsigned rt, unsigned rb, do_load_tl(ctx, dest, rb, rx, scale, disp, modify, mop); save_gpr(ctx, rt, dest); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i32 tmp; @@ -1223,12 +1211,12 @@ static ExitStatus do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, gen_helper_loaded_fr0(cpu_env); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i64 tmp; @@ -1243,20 +1231,20 @@ static ExitStatus do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, gen_helper_loaded_fr0(cpu_env); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_long disp, int modify, TCGMemOp mop) +static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, + target_long disp, int modify, TCGMemOp mop) { nullify_over(ctx); do_store_tl(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i32 tmp; @@ -1266,12 +1254,12 @@ static ExitStatus do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, do_store_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); tcg_temp_free_i32(tmp); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i64 tmp; @@ -1281,11 +1269,11 @@ static ExitStatus do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, do_store_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); tcg_temp_free_i64(tmp); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) +static DisasJumpType do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) { TCGv_i32 tmp; @@ -1296,11 +1284,11 @@ static ExitStatus do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, save_frw_i32(rt, tmp); tcg_temp_free_i32(tmp); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) +static DisasJumpType do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, + void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) { TCGv_i32 dst; TCGv_i64 src; @@ -1314,11 +1302,11 @@ static ExitStatus do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, tcg_temp_free_i64(src); save_frw_i32(rt, dst); tcg_temp_free_i32(dst); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) +static DisasJumpType do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, + void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) { TCGv_i64 tmp; @@ -1329,11 +1317,11 @@ static ExitStatus do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, save_frd(rt, tmp); tcg_temp_free_i64(tmp); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) +static DisasJumpType do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, + void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) { TCGv_i32 src; TCGv_i64 dst; @@ -1347,13 +1335,13 @@ static ExitStatus do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, tcg_temp_free_i32(src); save_frd(rt, dst); tcg_temp_free_i64(dst); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fop_weww(DisasContext *ctx, unsigned rt, - unsigned ra, unsigned rb, - void (*func)(TCGv_i32, TCGv_env, - TCGv_i32, TCGv_i32)) +static DisasJumpType do_fop_weww(DisasContext *ctx, unsigned rt, + unsigned ra, unsigned rb, + void (*func)(TCGv_i32, TCGv_env, + TCGv_i32, TCGv_i32)) { TCGv_i32 a, b; @@ -1366,13 +1354,13 @@ static ExitStatus do_fop_weww(DisasContext *ctx, unsigned rt, tcg_temp_free_i32(b); save_frw_i32(rt, a); tcg_temp_free_i32(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus do_fop_dedd(DisasContext *ctx, unsigned rt, - unsigned ra, unsigned rb, - void (*func)(TCGv_i64, TCGv_env, - TCGv_i64, TCGv_i64)) +static DisasJumpType do_fop_dedd(DisasContext *ctx, unsigned rt, + unsigned ra, unsigned rb, + void (*func)(TCGv_i64, TCGv_env, + TCGv_i64, TCGv_i64)) { TCGv_i64 a, b; @@ -1385,13 +1373,13 @@ static ExitStatus do_fop_dedd(DisasContext *ctx, unsigned rt, tcg_temp_free_i64(b); save_frd(rt, a); tcg_temp_free_i64(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static ExitStatus do_dbranch(DisasContext *ctx, target_ulong dest, - unsigned link, bool is_n) +static DisasJumpType do_dbranch(DisasContext *ctx, target_ulong dest, + unsigned link, bool is_n) { if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { if (link != 0) { @@ -1401,7 +1389,7 @@ static ExitStatus do_dbranch(DisasContext *ctx, target_ulong dest, if (is_n) { ctx->null_cond.c = TCG_COND_ALWAYS; } - return NO_EXIT; + return DISAS_NEXT; } else { nullify_over(ctx); @@ -1417,18 +1405,18 @@ static ExitStatus do_dbranch(DisasContext *ctx, target_ulong dest, gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); } - nullify_end(ctx, NO_EXIT); + nullify_end(ctx, DISAS_NEXT); nullify_set(ctx, 0); gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); - return EXIT_GOTO_TB; + return DISAS_NORETURN; } } /* Emit a conditional branch to a direct target. If the branch itself is nullified, we should have already used nullify_over. */ -static ExitStatus do_cbranch(DisasContext *ctx, target_long disp, bool is_n, - DisasCond *cond) +static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool is_n, + DisasCond *cond) { target_ulong dest = iaoq_dest(ctx, disp); TCGLabel *taken = NULL; @@ -1480,16 +1468,16 @@ static ExitStatus do_cbranch(DisasContext *ctx, target_long disp, bool is_n, if (ctx->null_lab) { gen_set_label(ctx->null_lab); ctx->null_lab = NULL; - return EXIT_IAQ_N_STALE; + return DISAS_IAQ_N_STALE; } else { - return EXIT_GOTO_TB; + return DISAS_NORETURN; } } /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static ExitStatus do_ibranch(DisasContext *ctx, TCGv dest, - unsigned link, bool is_n) +static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, + unsigned link, bool is_n) { TCGv a0, a1, next, tmp; TCGCond c; @@ -1528,7 +1516,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv dest, tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); } tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } else { cond_prep(&ctx->null_cond); c = ctx->null_cond.c; @@ -1560,7 +1548,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv dest, } } - return NO_EXIT; + return DISAS_NEXT; } /* On Linux, page zero is normally marked execute only + gateway. @@ -1570,7 +1558,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv dest, in than the "be disp(sr2,r0)" instruction that probably sent us here, is the easiest way to handle the branch delay slot on the aforementioned BE. */ -static ExitStatus do_page_zero(DisasContext *ctx) +static DisasJumpType do_page_zero(DisasContext *ctx) { /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the @@ -1598,55 +1586,55 @@ static ExitStatus do_page_zero(DisasContext *ctx) switch (ctx->iaoq_f) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_SIGSEGV); - return EXIT_NORETURN; + return DISAS_NORETURN; case 0xb0: /* LWS */ gen_excp_1(EXCP_SYSCALL_LWS); - return EXIT_NORETURN; + return DISAS_NORETURN; case 0xe0: /* SET_THREAD_POINTER */ tcg_gen_mov_tl(cpu_cr27, cpu_gr[26]); tcg_gen_mov_tl(cpu_iaoq_f, cpu_gr[31]); tcg_gen_addi_tl(cpu_iaoq_b, cpu_iaoq_f, 4); - return EXIT_IAQ_N_UPDATED; + return DISAS_IAQ_N_UPDATED; case 0x100: /* SYSCALL */ gen_excp_1(EXCP_SYSCALL); - return EXIT_NORETURN; + return DISAS_NORETURN; default: do_sigill: gen_excp_1(EXCP_SIGILL); - return EXIT_NORETURN; + return DISAS_NORETURN; } } -static ExitStatus trans_nop(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_nop(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_break(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_break(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { nullify_over(ctx); return nullify_end(ctx, gen_excp(ctx, EXCP_DEBUG)); } -static ExitStatus trans_sync(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { /* No point in nullifying the memory barrier. */ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_mfia(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mfia(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); TCGv tmp = dest_gpr(ctx, rt); @@ -1654,11 +1642,11 @@ static ExitStatus trans_mfia(DisasContext *ctx, uint32_t insn, save_gpr(ctx, rt, tmp); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_mfsp(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mfsp(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); TCGv tmp = dest_gpr(ctx, rt); @@ -1668,11 +1656,11 @@ static ExitStatus trans_mfsp(DisasContext *ctx, uint32_t insn, save_gpr(ctx, rt, tmp); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_mfctl(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned ctl = extract32(insn, 21, 5); @@ -1708,11 +1696,11 @@ static ExitStatus trans_mfctl(DisasContext *ctx, uint32_t insn, } cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_mtctl(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rin = extract32(insn, 16, 5); unsigned ctl = extract32(insn, 21, 5); @@ -1729,11 +1717,11 @@ static ExitStatus trans_mtctl(DisasContext *ctx, uint32_t insn, } cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_mtsarcm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rin = extract32(insn, 16, 5); TCGv tmp = tcg_temp_new(); @@ -1744,11 +1732,11 @@ static ExitStatus trans_mtsarcm(DisasContext *ctx, uint32_t insn, tcg_temp_free(tmp); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_ldsid(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); TCGv dest = dest_gpr(ctx, rt); @@ -1758,7 +1746,7 @@ static ExitStatus trans_ldsid(DisasContext *ctx, uint32_t insn, save_gpr(ctx, rt, dest); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } static const DisasInsn table_system[] = { @@ -1774,8 +1762,8 @@ static const DisasInsn table_system[] = { { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, }; -static ExitStatus trans_base_idx_mod(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rb = extract32(insn, 21, 5); unsigned rx = extract32(insn, 16, 5); @@ -1788,11 +1776,11 @@ static ExitStatus trans_base_idx_mod(DisasContext *ctx, uint32_t insn, save_gpr(ctx, rb, dest); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_probe(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned rb = extract32(insn, 21, 5); @@ -1809,7 +1797,7 @@ static ExitStatus trans_probe(DisasContext *ctx, uint32_t insn, gen_helper_probe_r(dest, load_gpr(ctx, rb)); } save_gpr(ctx, rt, dest); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } static const DisasInsn table_mem_mgmt[] = { @@ -1830,8 +1818,8 @@ static const DisasInsn table_mem_mgmt[] = { { 0x04003180u, 0xfc003fa0u, trans_probe }, /* probei */ }; -static ExitStatus trans_add(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_add(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned r1 = extract32(insn, 16, 5); @@ -1844,7 +1832,7 @@ static ExitStatus trans_add(DisasContext *ctx, uint32_t insn, bool is_l = false; bool is_tc = false; bool is_tsv = false; - ExitStatus ret; + DisasJumpType ret; switch (ext) { case 0x6: /* ADD, SHLADD */ @@ -1874,8 +1862,8 @@ static ExitStatus trans_add(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, ret); } -static ExitStatus trans_sub(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_sub(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned r1 = extract32(insn, 16, 5); @@ -1886,7 +1874,7 @@ static ExitStatus trans_sub(DisasContext *ctx, uint32_t insn, bool is_b = false; bool is_tc = false; bool is_tsv = false; - ExitStatus ret; + DisasJumpType ret; switch (ext) { case 0x10: /* SUB */ @@ -1919,15 +1907,15 @@ static ExitStatus trans_sub(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, ret); } -static ExitStatus trans_log(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_log(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2; - ExitStatus ret; + DisasJumpType ret; if (cf) { nullify_over(ctx); @@ -1939,8 +1927,8 @@ static ExitStatus trans_log(DisasContext *ctx, uint32_t insn, } /* OR r,0,t -> COPY (according to gas) */ -static ExitStatus trans_copy(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_copy(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r1 = extract32(insn, 16, 5); unsigned rt = extract32(insn, 0, 5); @@ -1953,18 +1941,18 @@ static ExitStatus trans_copy(DisasContext *ctx, uint32_t insn, save_gpr(ctx, rt, cpu_gr[r1]); } cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_cmpclr(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_cmpclr(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2; - ExitStatus ret; + DisasJumpType ret; if (cf) { nullify_over(ctx); @@ -1975,15 +1963,15 @@ static ExitStatus trans_cmpclr(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, ret); } -static ExitStatus trans_uxor(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_uxor(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned r1 = extract32(insn, 16, 5); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2; - ExitStatus ret; + DisasJumpType ret; if (cf) { nullify_over(ctx); @@ -1994,8 +1982,8 @@ static ExitStatus trans_uxor(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, ret); } -static ExitStatus trans_uaddcm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_uaddcm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned r1 = extract32(insn, 16, 5); @@ -2003,7 +1991,7 @@ static ExitStatus trans_uaddcm(DisasContext *ctx, uint32_t insn, unsigned is_tc = extract32(insn, 6, 1); unsigned rt = extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2, tmp; - ExitStatus ret; + DisasJumpType ret; if (cf) { nullify_over(ctx); @@ -2016,15 +2004,15 @@ static ExitStatus trans_uaddcm(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, ret); } -static ExitStatus trans_dcor(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_dcor(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned cf = extract32(insn, 12, 4); unsigned is_i = extract32(insn, 6, 1); unsigned rt = extract32(insn, 0, 5); TCGv tmp; - ExitStatus ret; + DisasJumpType ret; nullify_over(ctx); @@ -2041,8 +2029,8 @@ static ExitStatus trans_dcor(DisasContext *ctx, uint32_t insn, return nullify_end(ctx, ret); } -static ExitStatus trans_ds(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 = extract32(insn, 21, 5); unsigned r1 = extract32(insn, 16, 5); @@ -2105,7 +2093,7 @@ static ExitStatus trans_ds(DisasContext *ctx, uint32_t insn, tcg_temp_free(add2); tcg_temp_free(dest); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } static const DisasInsn table_arith_log[] = { @@ -2126,7 +2114,7 @@ static const DisasInsn table_arith_log[] = { { 0x08000200u, 0xfc000320u, trans_add }, /* shladd */ }; -static ExitStatus trans_addi(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_addi(DisasContext *ctx, uint32_t insn) { target_long im = low_sextract(insn, 0, 11); unsigned e1 = extract32(insn, 11, 1); @@ -2135,7 +2123,7 @@ static ExitStatus trans_addi(DisasContext *ctx, uint32_t insn) unsigned r2 = extract32(insn, 21, 5); unsigned o1 = extract32(insn, 26, 1); TCGv tcg_im, tcg_r2; - ExitStatus ret; + DisasJumpType ret; if (cf) { nullify_over(ctx); @@ -2148,7 +2136,7 @@ static ExitStatus trans_addi(DisasContext *ctx, uint32_t insn) return nullify_end(ctx, ret); } -static ExitStatus trans_subi(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_subi(DisasContext *ctx, uint32_t insn) { target_long im = low_sextract(insn, 0, 11); unsigned e1 = extract32(insn, 11, 1); @@ -2156,7 +2144,7 @@ static ExitStatus trans_subi(DisasContext *ctx, uint32_t insn) unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); TCGv tcg_im, tcg_r2; - ExitStatus ret; + DisasJumpType ret; if (cf) { nullify_over(ctx); @@ -2169,14 +2157,14 @@ static ExitStatus trans_subi(DisasContext *ctx, uint32_t insn) return nullify_end(ctx, ret); } -static ExitStatus trans_cmpiclr(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_cmpiclr(DisasContext *ctx, uint32_t insn) { target_long im = low_sextract(insn, 0, 11); unsigned cf = extract32(insn, 12, 4); unsigned rt = extract32(insn, 16, 5); unsigned r2 = extract32(insn, 21, 5); TCGv tcg_im, tcg_r2; - ExitStatus ret; + DisasJumpType ret; if (cf) { nullify_over(ctx); @@ -2189,8 +2177,8 @@ static ExitStatus trans_cmpiclr(DisasContext *ctx, uint32_t insn) return nullify_end(ctx, ret); } -static ExitStatus trans_ld_idx_i(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ld_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned m = extract32(insn, 5, 1); @@ -2204,8 +2192,8 @@ static ExitStatus trans_ld_idx_i(DisasContext *ctx, uint32_t insn, return do_load(ctx, rt, rb, 0, 0, disp, modify, mop); } -static ExitStatus trans_ld_idx_x(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ld_idx_x(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned m = extract32(insn, 5, 1); @@ -2218,8 +2206,8 @@ static ExitStatus trans_ld_idx_x(DisasContext *ctx, uint32_t insn, return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, m, mop); } -static ExitStatus trans_st_idx_i(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_st_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { int disp = low_sextract(insn, 0, 5); unsigned m = extract32(insn, 5, 1); @@ -2233,8 +2221,8 @@ static ExitStatus trans_st_idx_i(DisasContext *ctx, uint32_t insn, return do_store(ctx, rr, rb, disp, modify, mop); } -static ExitStatus trans_ldcw(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned m = extract32(insn, 5, 1); @@ -2285,11 +2273,11 @@ static ExitStatus trans_ldcw(DisasContext *ctx, uint32_t insn, } save_gpr(ctx, rt, dest); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_stby(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { target_long disp = low_sextract(insn, 0, 5); unsigned m = extract32(insn, 5, 1); @@ -2321,7 +2309,7 @@ static ExitStatus trans_stby(DisasContext *ctx, uint32_t insn, } tcg_temp_free(addr); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } static const DisasInsn table_index_mem[] = { @@ -2332,7 +2320,7 @@ static const DisasInsn table_index_mem[] = { { 0x0c001300u, 0xfc0013c0, trans_stby }, }; -static ExitStatus trans_ldil(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) { unsigned rt = extract32(insn, 21, 5); target_long i = assemble_21(insn); @@ -2342,10 +2330,10 @@ static ExitStatus trans_ldil(DisasContext *ctx, uint32_t insn) save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_addil(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_addil(DisasContext *ctx, uint32_t insn) { unsigned rt = extract32(insn, 21, 5); target_long i = assemble_21(insn); @@ -2356,10 +2344,10 @@ static ExitStatus trans_addil(DisasContext *ctx, uint32_t insn) save_gpr(ctx, 1, tcg_r1); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_ldo(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_ldo(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); @@ -2376,11 +2364,11 @@ static ExitStatus trans_ldo(DisasContext *ctx, uint32_t insn) save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } -static ExitStatus trans_load(DisasContext *ctx, uint32_t insn, - bool is_mod, TCGMemOp mop) +static DisasJumpType trans_load(DisasContext *ctx, uint32_t insn, + bool is_mod, TCGMemOp mop) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); @@ -2389,7 +2377,7 @@ static ExitStatus trans_load(DisasContext *ctx, uint32_t insn, return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } -static ExitStatus trans_load_w(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); @@ -2410,7 +2398,7 @@ static ExitStatus trans_load_w(DisasContext *ctx, uint32_t insn) } } -static ExitStatus trans_fload_mod(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_fload_mod(DisasContext *ctx, uint32_t insn) { target_long i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); @@ -2422,8 +2410,8 @@ static ExitStatus trans_fload_mod(DisasContext *ctx, uint32_t insn) return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); } -static ExitStatus trans_store(DisasContext *ctx, uint32_t insn, - bool is_mod, TCGMemOp mop) +static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, + bool is_mod, TCGMemOp mop) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); @@ -2432,7 +2420,7 @@ static ExitStatus trans_store(DisasContext *ctx, uint32_t insn, return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } -static ExitStatus trans_store_w(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) { unsigned rb = extract32(insn, 21, 5); unsigned rt = extract32(insn, 16, 5); @@ -2452,7 +2440,7 @@ static ExitStatus trans_store_w(DisasContext *ctx, uint32_t insn) } } -static ExitStatus trans_fstore_mod(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_fstore_mod(DisasContext *ctx, uint32_t insn) { target_long i = assemble_16a(insn); unsigned t1 = extract32(insn, 1, 1); @@ -2464,7 +2452,7 @@ static ExitStatus trans_fstore_mod(DisasContext *ctx, uint32_t insn) return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); } -static ExitStatus trans_copr_w(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) { unsigned t0 = extract32(insn, 0, 5); unsigned m = extract32(insn, 5, 1); @@ -2499,7 +2487,7 @@ static ExitStatus trans_copr_w(DisasContext *ctx, uint32_t insn) return gen_illegal(ctx); } -static ExitStatus trans_copr_dw(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) { unsigned rt = extract32(insn, 0, 5); unsigned m = extract32(insn, 5, 1); @@ -2533,8 +2521,8 @@ static ExitStatus trans_copr_dw(DisasContext *ctx, uint32_t insn) } } -static ExitStatus trans_cmpb(DisasContext *ctx, uint32_t insn, - bool is_true, bool is_imm, bool is_dw) +static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, + bool is_true, bool is_imm, bool is_dw) { target_long disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); @@ -2565,8 +2553,8 @@ static ExitStatus trans_cmpb(DisasContext *ctx, uint32_t insn, return do_cbranch(ctx, disp, n, &cond); } -static ExitStatus trans_addb(DisasContext *ctx, uint32_t insn, - bool is_true, bool is_imm) +static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, + bool is_true, bool is_imm) { target_long disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); @@ -2607,7 +2595,7 @@ static ExitStatus trans_addb(DisasContext *ctx, uint32_t insn, return do_cbranch(ctx, disp, n, &cond); } -static ExitStatus trans_bb(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) { target_long disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); @@ -2633,7 +2621,7 @@ static ExitStatus trans_bb(DisasContext *ctx, uint32_t insn) return do_cbranch(ctx, disp, n, &cond); } -static ExitStatus trans_movb(DisasContext *ctx, uint32_t insn, bool is_imm) +static DisasJumpType trans_movb(DisasContext *ctx, uint32_t insn, bool is_imm) { target_long disp = assemble_12(insn) * 4; unsigned n = extract32(insn, 1, 1); @@ -2658,8 +2646,8 @@ static ExitStatus trans_movb(DisasContext *ctx, uint32_t insn, bool is_imm) return do_cbranch(ctx, disp, n, &cond); } -static ExitStatus trans_shrpw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_shrpw_sar(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned c = extract32(insn, 13, 3); @@ -2700,11 +2688,11 @@ static ExitStatus trans_shrpw_sar(DisasContext *ctx, uint32_t insn, if (c) { ctx->null_cond = do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_shrpw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_shrpw_imm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned cpos = extract32(insn, 5, 5); @@ -2741,11 +2729,11 @@ static ExitStatus trans_shrpw_imm(DisasContext *ctx, uint32_t insn, if (c) { ctx->null_cond = do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_extrw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_extrw_sar(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen = extract32(insn, 0, 5); unsigned is_se = extract32(insn, 10, 1); @@ -2780,11 +2768,11 @@ static ExitStatus trans_extrw_sar(DisasContext *ctx, uint32_t insn, if (c) { ctx->null_cond = do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_extrw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_extrw_imm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen = extract32(insn, 0, 5); unsigned pos = extract32(insn, 5, 5); @@ -2814,7 +2802,7 @@ static ExitStatus trans_extrw_imm(DisasContext *ctx, uint32_t insn, if (c) { ctx->null_cond = do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } static const DisasInsn table_sh_ex[] = { @@ -2824,8 +2812,8 @@ static const DisasInsn table_sh_ex[] = { { 0xd0001800u, 0xfc001800u, trans_extrw_imm }, }; -static ExitStatus trans_depw_imm_c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_depw_imm_c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen = extract32(insn, 0, 5); unsigned cpos = extract32(insn, 5, 5); @@ -2865,11 +2853,11 @@ static ExitStatus trans_depw_imm_c(DisasContext *ctx, uint32_t insn, if (c) { ctx->null_cond = do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_depw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_depw_imm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen = extract32(insn, 0, 5); unsigned cpos = extract32(insn, 5, 5); @@ -2902,11 +2890,11 @@ static ExitStatus trans_depw_imm(DisasContext *ctx, uint32_t insn, if (c) { ctx->null_cond = do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_depw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_depw_sar(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen = extract32(insn, 0, 5); unsigned nz = extract32(insn, 10, 1); @@ -2954,7 +2942,7 @@ static ExitStatus trans_depw_sar(DisasContext *ctx, uint32_t insn, if (c) { ctx->null_cond = do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } static const DisasInsn table_depw[] = { @@ -2963,7 +2951,7 @@ static const DisasInsn table_depw[] = { { 0xd4001800u, 0xfc001800u, trans_depw_imm_c }, }; -static ExitStatus trans_be(DisasContext *ctx, uint32_t insn, bool is_l) +static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) { unsigned n = extract32(insn, 1, 1); unsigned b = extract32(insn, 21, 5); @@ -2988,8 +2976,8 @@ static ExitStatus trans_be(DisasContext *ctx, uint32_t insn, bool is_l) } } -static ExitStatus trans_bl(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n = extract32(insn, 1, 1); unsigned link = extract32(insn, 21, 5); @@ -2998,8 +2986,8 @@ static ExitStatus trans_bl(DisasContext *ctx, uint32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } -static ExitStatus trans_bl_long(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n = extract32(insn, 1, 1); target_long disp = assemble_22(insn); @@ -3007,8 +2995,8 @@ static ExitStatus trans_bl_long(DisasContext *ctx, uint32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), 2, n); } -static ExitStatus trans_blr(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_blr(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n = extract32(insn, 1, 1); unsigned rx = extract32(insn, 16, 5); @@ -3020,8 +3008,8 @@ static ExitStatus trans_blr(DisasContext *ctx, uint32_t insn, return do_ibranch(ctx, tmp, link, n); } -static ExitStatus trans_bv(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bv(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n = extract32(insn, 1, 1); unsigned rx = extract32(insn, 16, 5); @@ -3038,8 +3026,8 @@ static ExitStatus trans_bv(DisasContext *ctx, uint32_t insn, return do_ibranch(ctx, dest, 0, n); } -static ExitStatus trans_bve(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bve(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n = extract32(insn, 1, 1); unsigned rb = extract32(insn, 21, 5); @@ -3056,64 +3044,64 @@ static const DisasInsn table_branch[] = { { 0xe800d000u, 0xfc00dffcu, trans_bve }, }; -static ExitStatus trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned ra = extract32(insn, 21, 5); return do_fop_wew(ctx, rt, ra, di->f.wew); } -static ExitStatus trans_fop_wew_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wew_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = assemble_rt64(insn); unsigned ra = assemble_ra64(insn); return do_fop_wew(ctx, rt, ra, di->f.wew); } -static ExitStatus trans_fop_ded(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_ded(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned ra = extract32(insn, 21, 5); return do_fop_ded(ctx, rt, ra, di->f.ded); } -static ExitStatus trans_fop_wed_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wed_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned ra = extract32(insn, 21, 5); return do_fop_wed(ctx, rt, ra, di->f.wed); } -static ExitStatus trans_fop_wed_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wed_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = assemble_rt64(insn); unsigned ra = extract32(insn, 21, 5); return do_fop_wed(ctx, rt, ra, di->f.wed); } -static ExitStatus trans_fop_dew_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_dew_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned ra = extract32(insn, 21, 5); return do_fop_dew(ctx, rt, ra, di->f.dew); } -static ExitStatus trans_fop_dew_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_dew_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned ra = assemble_ra64(insn); return do_fop_dew(ctx, rt, ra, di->f.dew); } -static ExitStatus trans_fop_weww_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_weww_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned rb = extract32(insn, 16, 5); @@ -3121,8 +3109,8 @@ static ExitStatus trans_fop_weww_0c(DisasContext *ctx, uint32_t insn, return do_fop_weww(ctx, rt, ra, rb, di->f.weww); } -static ExitStatus trans_fop_weww_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_weww_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = assemble_rt64(insn); unsigned rb = assemble_rb64(insn); @@ -3130,8 +3118,8 @@ static ExitStatus trans_fop_weww_0e(DisasContext *ctx, uint32_t insn, return do_fop_weww(ctx, rt, ra, rb, di->f.weww); } -static ExitStatus trans_fop_dedd(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_dedd(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned rb = extract32(insn, 16, 5); @@ -3179,8 +3167,8 @@ static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) tcg_gen_ori_i64(dst, src, INT64_MIN); } -static ExitStatus do_fcmp_s(DisasContext *ctx, unsigned ra, unsigned rb, - unsigned y, unsigned c) +static DisasJumpType do_fcmp_s(DisasContext *ctx, unsigned ra, unsigned rb, + unsigned y, unsigned c) { TCGv_i32 ta, tb, tc, ty; @@ -3198,11 +3186,11 @@ static ExitStatus do_fcmp_s(DisasContext *ctx, unsigned ra, unsigned rb, tcg_temp_free_i32(ty); tcg_temp_free_i32(tc); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_fcmp_s_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fcmp_s_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c = extract32(insn, 0, 5); unsigned y = extract32(insn, 13, 3); @@ -3211,8 +3199,8 @@ static ExitStatus trans_fcmp_s_0c(DisasContext *ctx, uint32_t insn, return do_fcmp_s(ctx, ra, rb, y, c); } -static ExitStatus trans_fcmp_s_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fcmp_s_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c = extract32(insn, 0, 5); unsigned y = extract32(insn, 13, 3); @@ -3221,8 +3209,8 @@ static ExitStatus trans_fcmp_s_0e(DisasContext *ctx, uint32_t insn, return do_fcmp_s(ctx, ra, rb, y, c); } -static ExitStatus trans_fcmp_d(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fcmp_d(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c = extract32(insn, 0, 5); unsigned y = extract32(insn, 13, 3); @@ -3245,11 +3233,11 @@ static ExitStatus trans_fcmp_d(DisasContext *ctx, uint32_t insn, tcg_temp_free_i32(ty); tcg_temp_free_i32(tc); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_ftest_t(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ftest_t(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned y = extract32(insn, 13, 3); unsigned cbit = (y ^ 1) - 1; @@ -3263,11 +3251,11 @@ static ExitStatus trans_ftest_t(DisasContext *ctx, uint32_t insn, ctx->null_cond = cond_make_0(TCG_COND_NE, t); tcg_temp_free(t); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_ftest_q(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ftest_q(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c = extract32(insn, 0, 5); int mask; @@ -3317,11 +3305,11 @@ static ExitStatus trans_ftest_q(DisasContext *ctx, uint32_t insn, ctx->null_cond = cond_make_0(TCG_COND_EQ, t); } done: - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_xmpyu(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_xmpyu(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned rb = assemble_rb64(insn); @@ -3337,7 +3325,7 @@ static ExitStatus trans_xmpyu(DisasContext *ctx, uint32_t insn, tcg_temp_free_i64(a); tcg_temp_free_i64(b); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } #define FOP_DED trans_fop_ded, .f.ded @@ -3512,7 +3500,8 @@ static inline int fmpyadd_s_reg(unsigned r) return (r & 16) * 2 + 16 + (r & 15); } -static ExitStatus trans_fmpyadd(DisasContext *ctx, uint32_t insn, bool is_sub) +static DisasJumpType trans_fmpyadd(DisasContext *ctx, + uint32_t insn, bool is_sub) { unsigned tm = extract32(insn, 0, 5); unsigned f = extract32(insn, 5, 1); @@ -3540,11 +3529,11 @@ static ExitStatus trans_fmpyadd(DisasContext *ctx, uint32_t insn, bool is_sub) is_sub ? gen_helper_fsub_d : gen_helper_fadd_d); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_fmpyfadd_s(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fmpyfadd_s(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = assemble_rt64(insn); unsigned neg = extract32(insn, 5, 1); @@ -3568,11 +3557,11 @@ static ExitStatus trans_fmpyfadd_s(DisasContext *ctx, uint32_t insn, tcg_temp_free_i32(c); save_frw_i32(rt, a); tcg_temp_free_i32(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } -static ExitStatus trans_fmpyfadd_d(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fmpyfadd_d(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt = extract32(insn, 0, 5); unsigned neg = extract32(insn, 5, 1); @@ -3596,7 +3585,7 @@ static ExitStatus trans_fmpyfadd_d(DisasContext *ctx, uint32_t insn, tcg_temp_free_i64(c); save_frd(rt, a); tcg_temp_free_i64(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } static const DisasInsn table_fp_fused[] = { @@ -3604,8 +3593,8 @@ static const DisasInsn table_fp_fused[] = { { 0xb8000800u, 0xfc0019c0u, trans_fmpyfadd_d } }; -static ExitStatus translate_table_int(DisasContext *ctx, uint32_t insn, - const DisasInsn table[], size_t n) +static DisasJumpType translate_table_int(DisasContext *ctx, uint32_t insn, + const DisasInsn table[], size_t n) { size_t i; for (i = 0; i < n; ++i) { @@ -3619,7 +3608,7 @@ static ExitStatus translate_table_int(DisasContext *ctx, uint32_t insn, #define translate_table(ctx, insn, table) \ translate_table_int(ctx, insn, table, ARRAY_SIZE(table)) -static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) +static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) { uint32_t opc = extract32(insn, 26, 6); @@ -3740,188 +3729,201 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) return gen_illegal(ctx); } -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static int hppa_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { - CPUHPPAState *env = cs->env_ptr; - DisasContext ctx; - ExitStatus ret; - int num_insns, max_insns, i; + DisasContext *ctx = container_of(dcbase, DisasContext, base); + TranslationBlock *tb = ctx->base.tb; + int i, bound; - ctx.tb = tb; - ctx.cs = cs; - ctx.iaoq_f = tb->pc; - ctx.iaoq_b = tb->cs_base; - ctx.singlestep_enabled = cs->singlestep_enabled; + ctx->cs = cs; + ctx->iaoq_f = tb->pc; + ctx->iaoq_b = tb->cs_base; + ctx->iaoq_n = -1; + TCGV_UNUSED(ctx->iaoq_n_var); - ctx.ntemps = 0; - for (i = 0; i < ARRAY_SIZE(ctx.temps); ++i) { - TCGV_UNUSED(ctx.temps[i]); + ctx->ntemps = 0; + for (i = 0; i < ARRAY_SIZE(ctx->temps); ++i) { + TCGV_UNUSED(ctx->temps[i]); } - /* Compute the maximum number of insns to execute, as bounded by - (1) icount, (2) single-stepping, (3) branch delay slots, or - (4) the number of insns remaining on the current page. */ - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (ctx.singlestep_enabled || singlestep) { - max_insns = 1; - } else if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } + bound = -(tb->pc | TARGET_PAGE_MASK) / 4; + return MIN(max_insns, bound); +} - num_insns = 0; - gen_tb_start(tb); +static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); /* Seed the nullification status from PSW[N], as shown in TB->FLAGS. */ - ctx.null_cond = cond_make_f(); - ctx.psw_n_nonzero = false; - if (tb->flags & 1) { - ctx.null_cond.c = TCG_COND_ALWAYS; - ctx.psw_n_nonzero = true; + ctx->null_cond = cond_make_f(); + ctx->psw_n_nonzero = false; + if (ctx->base.tb->flags & 1) { + ctx->null_cond.c = TCG_COND_ALWAYS; + ctx->psw_n_nonzero = true; } - ctx.null_lab = NULL; + ctx->null_lab = NULL; +} - do { - tcg_gen_insn_start(ctx.iaoq_f, ctx.iaoq_b); - num_insns++; +static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); - if (unlikely(cpu_breakpoint_test(cs, ctx.iaoq_f, BP_ANY))) { - ret = gen_excp(&ctx, EXCP_DEBUG); - break; - } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } + tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); +} + +static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); - if (ctx.iaoq_f < TARGET_PAGE_SIZE) { - ret = do_page_zero(&ctx); - assert(ret != NO_EXIT); + ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG); + ctx->base.pc_next = ctx->iaoq_f + 4; + return true; +} + +static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPUHPPAState *env = cs->env_ptr; + DisasJumpType ret; + int i, n; + + /* Execute one insn. */ + if (ctx->iaoq_f < TARGET_PAGE_SIZE) { + ret = do_page_zero(ctx); + assert(ret != DISAS_NEXT); + } else { + /* Always fetch the insn, even if nullified, so that we check + the page permissions for execute. */ + uint32_t insn = cpu_ldl_code(env, ctx->iaoq_f); + + /* Set up the IA queue for the next insn. + This will be overwritten by a branch. */ + if (ctx->iaoq_b == -1) { + ctx->iaoq_n = -1; + ctx->iaoq_n_var = get_temp(ctx); + tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { - /* Always fetch the insn, even if nullified, so that we check - the page permissions for execute. */ - uint32_t insn = cpu_ldl_code(env, ctx.iaoq_f); - - /* Set up the IA queue for the next insn. - This will be overwritten by a branch. */ - if (ctx.iaoq_b == -1) { - ctx.iaoq_n = -1; - ctx.iaoq_n_var = get_temp(&ctx); - tcg_gen_addi_tl(ctx.iaoq_n_var, cpu_iaoq_b, 4); - } else { - ctx.iaoq_n = ctx.iaoq_b + 4; - TCGV_UNUSED(ctx.iaoq_n_var); - } - - if (unlikely(ctx.null_cond.c == TCG_COND_ALWAYS)) { - ctx.null_cond.c = TCG_COND_NEVER; - ret = NO_EXIT; - } else { - ret = translate_one(&ctx, insn); - assert(ctx.null_lab == NULL); - } + ctx->iaoq_n = ctx->iaoq_b + 4; + TCGV_UNUSED(ctx->iaoq_n_var); } - for (i = 0; i < ctx.ntemps; ++i) { - tcg_temp_free(ctx.temps[i]); - TCGV_UNUSED(ctx.temps[i]); - } - ctx.ntemps = 0; - - /* If we see non-linear instructions, exhaust instruction count, - or run out of buffer space, stop generation. */ - /* ??? The non-linear instruction restriction is purely due to - the debugging dump. Otherwise we *could* follow unconditional - branches within the same page. */ - if (ret == NO_EXIT - && (ctx.iaoq_b != ctx.iaoq_f + 4 - || num_insns >= max_insns - || tcg_op_buf_full())) { - if (ctx.null_cond.c == TCG_COND_NEVER - || ctx.null_cond.c == TCG_COND_ALWAYS) { - nullify_set(&ctx, ctx.null_cond.c == TCG_COND_ALWAYS); - gen_goto_tb(&ctx, 0, ctx.iaoq_b, ctx.iaoq_n); - ret = EXIT_GOTO_TB; - } else { - ret = EXIT_IAQ_N_STALE; - } + if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { + ctx->null_cond.c = TCG_COND_NEVER; + ret = DISAS_NEXT; + } else { + ret = translate_one(ctx, insn); + assert(ctx->null_lab == NULL); } + } - ctx.iaoq_f = ctx.iaoq_b; - ctx.iaoq_b = ctx.iaoq_n; - if (ret == EXIT_NORETURN - || ret == EXIT_GOTO_TB - || ret == EXIT_IAQ_N_UPDATED) { - break; - } - if (ctx.iaoq_f == -1) { - tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); - copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_n, ctx.iaoq_n_var); - nullify_save(&ctx); - ret = EXIT_IAQ_N_UPDATED; - break; - } - if (ctx.iaoq_b == -1) { - tcg_gen_mov_tl(cpu_iaoq_b, ctx.iaoq_n_var); - } - } while (ret == NO_EXIT); + /* Free any temporaries allocated. */ + for (i = 0, n = ctx->ntemps; i < n; ++i) { + tcg_temp_free(ctx->temps[i]); + TCGV_UNUSED(ctx->temps[i]); + } + ctx->ntemps = 0; - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); + /* Advance the insn queue. */ + /* ??? The non-linear instruction restriction is purely due to + the debugging dump. Otherwise we *could* follow unconditional + branches within the same page. */ + if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { + if (ctx->null_cond.c == TCG_COND_NEVER + || ctx->null_cond.c == TCG_COND_ALWAYS) { + nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); + gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); + ret = DISAS_NORETURN; + } else { + ret = DISAS_IAQ_N_STALE; + } + } + ctx->iaoq_f = ctx->iaoq_b; + ctx->iaoq_b = ctx->iaoq_n; + ctx->base.is_jmp = ret; + + if (ret == DISAS_NORETURN || ret == DISAS_IAQ_N_UPDATED) { + return; + } + if (ctx->iaoq_f == -1) { + tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + nullify_save(ctx); + ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; + } else if (ctx->iaoq_b == -1) { + tcg_gen_mov_tl(cpu_iaoq_b, ctx->iaoq_n_var); } +} - switch (ret) { - case EXIT_GOTO_TB: - case EXIT_NORETURN: +static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { + case DISAS_NORETURN: break; - case EXIT_IAQ_N_STALE: - copy_iaoq_entry(cpu_iaoq_f, ctx.iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_b, cpu_iaoq_b); - nullify_save(&ctx); + case DISAS_TOO_MANY: + case DISAS_IAQ_N_STALE: + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + nullify_save(ctx); /* FALLTHRU */ - case EXIT_IAQ_N_UPDATED: - if (ctx.singlestep_enabled) { + case DISAS_IAQ_N_UPDATED: + if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); } break; default: - abort(); + g_assert_not_reached(); } - gen_tb_end(tb, num_insns); + /* We don't actually use this during normal translation, + but we should interact with the generic main loop. */ + ctx->base.pc_next = ctx->base.tb->pc + 4 * ctx->base.num_insns; +} - tb->size = num_insns * 4; - tb->icount = num_insns; +static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + TranslationBlock *tb = dcbase->tb; -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(tb->pc)) { - qemu_log_lock(); - switch (tb->pc) { - case 0x00: - qemu_log("IN:\n0x00000000: (null)\n\n"); - break; - case 0xb0: - qemu_log("IN:\n0x000000b0: light-weight-syscall\n\n"); - break; - case 0xe0: - qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n\n"); - break; - case 0x100: - qemu_log("IN:\n0x00000100: syscall\n\n"); - break; - default: - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, tb->size, 1); - qemu_log("\n"); - break; - } - qemu_log_unlock(); + switch (tb->pc) { + case 0x00: + qemu_log("IN:\n0x00000000: (null)\n"); + break; + case 0xb0: + qemu_log("IN:\n0x000000b0: light-weight-syscall\n"); + break; + case 0xe0: + qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n"); + break; + case 0x100: + qemu_log("IN:\n0x00000100: syscall\n"); + break; + default: + qemu_log("IN: %s\n", lookup_symbol(tb->pc)); + log_target_disas(cs, tb->pc, tb->size, 1); + break; } -#endif +} + +static const TranslatorOps hppa_tr_ops = { + .init_disas_context = hppa_tr_init_disas_context, + .tb_start = hppa_tr_tb_start, + .insn_start = hppa_tr_insn_start, + .breakpoint_check = hppa_tr_breakpoint_check, + .translate_insn = hppa_tr_translate_insn, + .tb_stop = hppa_tr_tb_stop, + .disas_log = hppa_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) + +{ + DisasContext ctx; + translator_loop(&hppa_tr_ops, &ctx.base, cs, tb); } void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb, diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index b41a248bee..c2525066ab 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -111,12 +111,20 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_direct_jump 1 + +#define TCG_TARGET_DEFAULT_MO (0) static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { __builtin___clear_cache((char *)start, (char *)stop); } -#define TCG_TARGET_DEFAULT_MO (0) +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif +#define TCG_TARGET_NEED_POOL_LABELS #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 04bc369a92..c2f3812214 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -10,7 +10,7 @@ * See the COPYING file in the top-level directory for details. */ -#include "tcg-be-ldst.h" +#include "tcg-pool.inc.c" #include "qemu/bitops.h" /* We're going to re-use TCGType in setting of the SF bit, which controls @@ -588,9 +588,11 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { - int i, wantinv, shift; tcg_target_long svalue = value; tcg_target_long ivalue = ~value; + tcg_target_long t0, t1, t2; + int s0, s1; + AArch64Insn opc; /* For 32-bit values, discard potential garbage in value. For 64-bit values within [2**31, 2**32-1], we can create smaller sequences by @@ -639,38 +641,29 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, } } - /* Would it take fewer insns to begin with MOVN? For the value and its - inverse, count the number of 16-bit lanes that are 0. */ - for (i = wantinv = 0; i < 64; i += 16) { - tcg_target_long mask = 0xffffull << i; - wantinv -= ((value & mask) == 0); - wantinv += ((ivalue & mask) == 0); - } - - if (wantinv <= 0) { - /* Find the lowest lane that is not 0x0000. */ - shift = ctz64(value) & (63 & -16); - tcg_out_insn(s, 3405, MOVZ, type, rd, value >> shift, shift); - /* Clear out the lane that we just set. */ - value &= ~(0xffffUL << shift); - /* Iterate until all non-zero lanes have been processed. */ - while (value) { - shift = ctz64(value) & (63 & -16); - tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift); - value &= ~(0xffffUL << shift); - } + /* Would it take fewer insns to begin with MOVN? */ + if (ctpop64(value) >= 32) { + t0 = ivalue; + opc = I3405_MOVN; } else { - /* Like above, but with the inverted value and MOVN to start. */ - shift = ctz64(ivalue) & (63 & -16); - tcg_out_insn(s, 3405, MOVN, type, rd, ivalue >> shift, shift); - ivalue &= ~(0xffffUL << shift); - while (ivalue) { - shift = ctz64(ivalue) & (63 & -16); - /* Provide MOVK with the non-inverted value. */ - tcg_out_insn(s, 3405, MOVK, type, rd, ~(ivalue >> shift), shift); - ivalue &= ~(0xffffUL << shift); + t0 = value; + opc = I3405_MOVZ; + } + s0 = ctz64(t0) & (63 & -16); + t1 = t0 & ~(0xffffUL << s0); + s1 = ctz64(t1) & (63 & -16); + t2 = t1 & ~(0xffffUL << s1); + if (t2 == 0) { + tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0); + if (t1 != 0) { + tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1); } + return; } + + /* For more than 2 insns, dump it into the constant pool. */ + new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0); + tcg_out_insn(s, 3305, LDR, 0, rd); } /* Define something more legible for general use. */ @@ -871,9 +864,8 @@ static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target) } } -#ifdef USE_DIRECT_JUMP - -void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { tcg_insn_unit i1, i2; TCGType rt = TCG_TYPE_I64; @@ -898,8 +890,6 @@ void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) flush_icache_range(jmp_addr, jmp_addr + 8); } -#endif - static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) { if (!l->has_value) { @@ -1073,6 +1063,8 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d, } #ifdef CONFIG_SOFTMMU +#include "tcg-ldst.inc.c" + /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) */ @@ -1412,7 +1404,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset != NULL) { - /* USE_DIRECT_JUMP */ + /* TCG_TARGET_HAS_direct_jump */ /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic write can be used to patch the target address. */ if ((uintptr_t)s->code_ptr & 7) { @@ -1420,11 +1412,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); /* actual branch destination will be patched by - aarch64_tb_set_jmp_target later. */ + tb_target_set_jmp_target later. */ tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG_TMP, 0); } else { - /* !USE_DIRECT_JUMP */ + /* !TCG_TARGET_HAS_direct_jump */ tcg_debug_assert(s->tb_jmp_target_addr != NULL); intptr_t offset = tcg_pcrel_diff(s, (s->tb_jmp_target_addr + a0)) >> 2; tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP); @@ -2032,6 +2024,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, 3207, RET, TCG_REG_LR); } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = NOP; + } +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index a38be15a39..94b3578c55 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -124,16 +124,25 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_div_i32 use_idiv_instructions #define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 0 enum { TCG_AREG0 = TCG_REG_R6, }; +#define TCG_TARGET_DEFAULT_MO (0) + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { __builtin___clear_cache((char *) start, (char *) stop); } -#define TCG_TARGET_DEFAULT_MO (0) +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif +#define TCG_TARGET_NEED_POOL_LABELS #endif diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 37efcf06af..db46aea38c 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -23,7 +23,7 @@ */ #include "elf.h" -#include "tcg-be-ldst.h" +#include "tcg-pool.inc.c" int arm_arch = __ARM_ARCH; @@ -86,6 +86,107 @@ static const int tcg_target_call_oarg_regs[2] = { #define TCG_REG_TMP TCG_REG_R12 +enum arm_cond_code_e { + COND_EQ = 0x0, + COND_NE = 0x1, + COND_CS = 0x2, /* Unsigned greater or equal */ + COND_CC = 0x3, /* Unsigned less than */ + COND_MI = 0x4, /* Negative */ + COND_PL = 0x5, /* Zero or greater */ + COND_VS = 0x6, /* Overflow */ + COND_VC = 0x7, /* No overflow */ + COND_HI = 0x8, /* Unsigned greater than */ + COND_LS = 0x9, /* Unsigned less or equal */ + COND_GE = 0xa, + COND_LT = 0xb, + COND_GT = 0xc, + COND_LE = 0xd, + COND_AL = 0xe, +}; + +#define TO_CPSR (1 << 20) + +#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) +#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) +#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) +#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) +#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) +#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) +#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) +#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) + +typedef enum { + ARITH_AND = 0x0 << 21, + ARITH_EOR = 0x1 << 21, + ARITH_SUB = 0x2 << 21, + ARITH_RSB = 0x3 << 21, + ARITH_ADD = 0x4 << 21, + ARITH_ADC = 0x5 << 21, + ARITH_SBC = 0x6 << 21, + ARITH_RSC = 0x7 << 21, + ARITH_TST = 0x8 << 21 | TO_CPSR, + ARITH_CMP = 0xa << 21 | TO_CPSR, + ARITH_CMN = 0xb << 21 | TO_CPSR, + ARITH_ORR = 0xc << 21, + ARITH_MOV = 0xd << 21, + ARITH_BIC = 0xe << 21, + ARITH_MVN = 0xf << 21, + + INSN_CLZ = 0x016f0f10, + INSN_RBIT = 0x06ff0f30, + + INSN_LDR_IMM = 0x04100000, + INSN_LDR_REG = 0x06100000, + INSN_STR_IMM = 0x04000000, + INSN_STR_REG = 0x06000000, + + INSN_LDRH_IMM = 0x005000b0, + INSN_LDRH_REG = 0x001000b0, + INSN_LDRSH_IMM = 0x005000f0, + INSN_LDRSH_REG = 0x001000f0, + INSN_STRH_IMM = 0x004000b0, + INSN_STRH_REG = 0x000000b0, + + INSN_LDRB_IMM = 0x04500000, + INSN_LDRB_REG = 0x06500000, + INSN_LDRSB_IMM = 0x005000d0, + INSN_LDRSB_REG = 0x001000d0, + INSN_STRB_IMM = 0x04400000, + INSN_STRB_REG = 0x06400000, + + INSN_LDRD_IMM = 0x004000d0, + INSN_LDRD_REG = 0x000000d0, + INSN_STRD_IMM = 0x004000f0, + INSN_STRD_REG = 0x000000f0, + + INSN_DMB_ISH = 0x5bf07ff5, + INSN_DMB_MCR = 0xba0f07ee, + + /* Architected nop introduced in v6k. */ + /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this + also Just So Happened to do nothing on pre-v6k so that we + don't need to conditionalize it? */ + INSN_NOP_v6k = 0xe320f000, + /* Otherwise the assembler uses mov r0,r0 */ + INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV, +} ARMInsn; + +#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) + +static const uint8_t tcg_cond_to_arm_cond[] = { + [TCG_COND_EQ] = COND_EQ, + [TCG_COND_NE] = COND_NE, + [TCG_COND_LT] = COND_LT, + [TCG_COND_GE] = COND_GE, + [TCG_COND_LE] = COND_LE, + [TCG_COND_GT] = COND_GT, + /* unsigned */ + [TCG_COND_LTU] = COND_CC, + [TCG_COND_GEU] = COND_CS, + [TCG_COND_LEU] = COND_LS, + [TCG_COND_GTU] = COND_HI, +}; + static inline void reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target) { ptrdiff_t offset = (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; @@ -103,9 +204,39 @@ static inline void reloc_pc24_atomic(tcg_insn_unit *code_ptr, tcg_insn_unit *tar static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_debug_assert(type == R_ARM_PC24); tcg_debug_assert(addend == 0); - reloc_pc24(code_ptr, (tcg_insn_unit *)value); + + if (type == R_ARM_PC24) { + reloc_pc24(code_ptr, (tcg_insn_unit *)value); + } else if (type == R_ARM_PC13) { + intptr_t diff = value - (uintptr_t)(code_ptr + 2); + tcg_insn_unit insn = *code_ptr; + bool u; + + if (diff >= -0xfff && diff <= 0xfff) { + u = (diff >= 0); + if (!u) { + diff = -diff; + } + } else { + int rd = extract32(insn, 12, 4); + int rt = rd == TCG_REG_PC ? TCG_REG_TMP : rd; + assert(diff >= 0x1000 && diff < 0x100000); + /* add rt, pc, #high */ + *code_ptr++ = ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD + | (TCG_REG_PC << 16) | (rt << 12) + | (20 << 7) | (diff >> 12)); + /* ldr rd, [rt, #low] */ + insn = deposit32(insn, 12, 4, rt); + diff &= 0xfff; + u = 1; + } + insn = deposit32(insn, 23, 1, u); + insn = deposit32(insn, 0, 12, diff); + *code_ptr = insn; + } else { + g_assert_not_reached(); + } } #define TCG_CT_CONST_ARM 0x100 @@ -237,98 +368,6 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, } } -#define TO_CPSR (1 << 20) - -typedef enum { - ARITH_AND = 0x0 << 21, - ARITH_EOR = 0x1 << 21, - ARITH_SUB = 0x2 << 21, - ARITH_RSB = 0x3 << 21, - ARITH_ADD = 0x4 << 21, - ARITH_ADC = 0x5 << 21, - ARITH_SBC = 0x6 << 21, - ARITH_RSC = 0x7 << 21, - ARITH_TST = 0x8 << 21 | TO_CPSR, - ARITH_CMP = 0xa << 21 | TO_CPSR, - ARITH_CMN = 0xb << 21 | TO_CPSR, - ARITH_ORR = 0xc << 21, - ARITH_MOV = 0xd << 21, - ARITH_BIC = 0xe << 21, - ARITH_MVN = 0xf << 21, - - INSN_CLZ = 0x016f0f10, - INSN_RBIT = 0x06ff0f30, - - INSN_LDR_IMM = 0x04100000, - INSN_LDR_REG = 0x06100000, - INSN_STR_IMM = 0x04000000, - INSN_STR_REG = 0x06000000, - - INSN_LDRH_IMM = 0x005000b0, - INSN_LDRH_REG = 0x001000b0, - INSN_LDRSH_IMM = 0x005000f0, - INSN_LDRSH_REG = 0x001000f0, - INSN_STRH_IMM = 0x004000b0, - INSN_STRH_REG = 0x000000b0, - - INSN_LDRB_IMM = 0x04500000, - INSN_LDRB_REG = 0x06500000, - INSN_LDRSB_IMM = 0x005000d0, - INSN_LDRSB_REG = 0x001000d0, - INSN_STRB_IMM = 0x04400000, - INSN_STRB_REG = 0x06400000, - - INSN_LDRD_IMM = 0x004000d0, - INSN_LDRD_REG = 0x000000d0, - INSN_STRD_IMM = 0x004000f0, - INSN_STRD_REG = 0x000000f0, - - INSN_DMB_ISH = 0x5bf07ff5, - INSN_DMB_MCR = 0xba0f07ee, - -} ARMInsn; - -#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) -#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) -#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) -#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) -#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) -#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) -#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) -#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) - -enum arm_cond_code_e { - COND_EQ = 0x0, - COND_NE = 0x1, - COND_CS = 0x2, /* Unsigned greater or equal */ - COND_CC = 0x3, /* Unsigned less than */ - COND_MI = 0x4, /* Negative */ - COND_PL = 0x5, /* Zero or greater */ - COND_VS = 0x6, /* Overflow */ - COND_VC = 0x7, /* No overflow */ - COND_HI = 0x8, /* Unsigned greater than */ - COND_LS = 0x9, /* Unsigned less or equal */ - COND_GE = 0xa, - COND_LT = 0xb, - COND_GT = 0xc, - COND_LE = 0xd, - COND_AL = 0xe, -}; - -static const uint8_t tcg_cond_to_arm_cond[] = { - [TCG_COND_EQ] = COND_EQ, - [TCG_COND_NE] = COND_NE, - [TCG_COND_LT] = COND_LT, - [TCG_COND_GE] = COND_GE, - [TCG_COND_LE] = COND_LE, - [TCG_COND_GT] = COND_GT, - /* unsigned */ - [TCG_COND_LTU] = COND_CC, - [TCG_COND_GEU] = COND_CS, - [TCG_COND_LEU] = COND_LS, - [TCG_COND_GTU] = COND_HI, -}; - static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) { tcg_out32(s, (cond << 28) | 0x0a000000 | @@ -377,16 +416,7 @@ static inline void tcg_out_dat_reg(TCGContext *s, static inline void tcg_out_nop(TCGContext *s) { - if (use_armv7_instructions) { - /* Architected nop introduced in v6k. */ - /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this - also Just So Happened to do nothing on pre-v6k so that we - don't need to conditionalize it? */ - tcg_out32(s, 0xe320f000); - } else { - /* Prior to that the assembler uses mov r0, r0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0)); - } + tcg_out32(s, INSN_NOP); } static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) @@ -416,9 +446,186 @@ static inline void tcg_out_dat_imm(TCGContext *s, (rn << 16) | (rd << 12) | im); } +/* Note that this routine is used for both LDR and LDRH formats, so we do + not wish to include an immediate shift at this point. */ +static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, + TCGReg rn, TCGReg rm, bool u, bool p, bool w) +{ + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) + | (w << 21) | (rn << 16) | (rt << 12) | rm); +} + +static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, + TCGReg rn, int imm8, bool p, bool w) +{ + bool u = 1; + if (imm8 < 0) { + imm8 = -imm8; + u = 0; + } + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | + (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); +} + +static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, + TCGReg rn, int imm12, bool p, bool w) +{ + bool u = 1; + if (imm12 < 0) { + imm12 = -imm12; + u = 0; + } + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | + (rn << 16) | (rt << 12) | imm12); +} + +static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); +} + +/* Register pre-increment with base writeback. */ +static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); +} + +static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); +} + +static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); +} + +static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg) +{ + /* The 12-bit range on the ldr insn is sometimes a bit too small. + In order to get around that we require two insns, one of which + will usually be a nop, but may be replaced in patch_reloc. */ + new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); + tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); + tcg_out_nop(s); +} + static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) { - int rot, opc, rn, diff; + int rot, diff, opc, sh1, sh2; + uint32_t tt0, tt1, tt2; /* Check a single MOV/MVN before anything else. */ rot = encode_imm(arg); @@ -466,24 +673,30 @@ static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) return; } - /* TODO: This is very suboptimal, we can easily have a constant - pool somewhere after all the instructions. */ + /* Look for sequences of two insns. If we have lots of 1's, we can + shorten the sequence by beginning with mvn and then clearing + higher bits with eor. */ + tt0 = arg; opc = ARITH_MOV; - rn = 0; - /* If we have lots of leading 1's, we can shorten the sequence by - beginning with mvn and then clearing higher bits with eor. */ - if (clz32(~arg) > clz32(arg)) { - opc = ARITH_MVN, arg = ~arg; + if (ctpop32(arg) > 16) { + tt0 = ~arg; + opc = ARITH_MVN; + } + sh1 = ctz32(tt0) & ~1; + tt1 = tt0 & ~(0xff << sh1); + sh2 = ctz32(tt1) & ~1; + tt2 = tt1 & ~(0xff << sh2); + if (tt2 == 0) { + rot = ((32 - sh1) << 7) & 0xf00; + tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); + rot = ((32 - sh2) << 7) & 0xf00; + tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, + ((tt0 >> sh2) & 0xff) | rot); + return; } - do { - int i = ctz32(arg) & ~1; - rot = ((32 - i) << 7) & 0xf00; - tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot); - arg &= ~(0xff << i); - opc = ARITH_EOR; - rn = rd; - } while (arg); + /* Otherwise, drop it into the constant pool. */ + tcg_out_movi_pool(s, cond, rd, arg); } static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, @@ -748,172 +961,6 @@ static inline void tcg_out_sextract(TCGContext *s, int cond, TCGReg rd, | (ofs << 7) | ((len - 1) << 16)); } -/* Note that this routine is used for both LDR and LDRH formats, so we do - not wish to include an immediate shift at this point. */ -static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, - TCGReg rn, TCGReg rm, bool u, bool p, bool w) -{ - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) - | (w << 21) | (rn << 16) | (rt << 12) | rm); -} - -static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, - TCGReg rn, int imm8, bool p, bool w) -{ - bool u = 1; - if (imm8 < 0) { - imm8 = -imm8; - u = 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf)); -} - -static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg rt, - TCGReg rn, int imm12, bool p, bool w) -{ - bool u = 1; - if (imm12 < 0) { - imm12 = -imm12; - u = 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | imm12); -} - -static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); -} - -/* Register pre-increment with base writeback. */ -static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); -} - -static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); -} - -static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); -} - static inline void tcg_out_ld32u(TCGContext *s, int cond, int rd, int rn, int32_t offset) { @@ -1007,10 +1054,7 @@ static void tcg_out_goto(TCGContext *s, int cond, tcg_insn_unit *addr) tcg_out_b(s, cond, disp); return; } - - assert(use_armv5t_instructions || (addri & 1) == 0); - tcg_out_movi32(s, cond, TCG_REG_TMP, addri); - tcg_out_bx(s, cond, TCG_REG_TMP); + tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); } /* The call case is mostly used for helpers - so it's not unreasonable @@ -1034,9 +1078,9 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr) tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); tcg_out_blx(s, COND_AL, TCG_REG_TMP); } else { + /* ??? Know that movi_pool emits exactly 2 insns. */ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4); - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); - tcg_out32(s, addri); + tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); } } @@ -1060,6 +1104,8 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a0) } #ifdef CONFIG_SOFTMMU +#include "tcg-ldst.inc.c" + /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -1172,30 +1218,48 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); - /* Should generate something like the following: - * shr tmp, addrlo, #TARGET_PAGE_BITS (1) + /* V7 generates the following: + * ubfx r0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS + * add r2, env, #high + * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr r0, [r2, #cmp] + * ldr r2, [r2, #add] + * movw tmp, #page_align_mask + * bic tmp, addrlo, tmp + * cmp r0, tmp + * + * Otherwise we generate: + * shr tmp, addrlo, #TARGET_PAGE_BITS * add r2, env, #high - * and r0, tmp, #(CPU_TLB_SIZE - 1) (2) - * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3) - * ldr r0, [r2, #cmp] (4) + * and r0, tmp, #(CPU_TLB_SIZE - 1) + * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr r0, [r2, #cmp] + * ldr r2, [r2, #add] * tst addrlo, #s_mask - * ldr r2, [r2, #add] (5) * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, - 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + if (use_armv7_instructions) { + tcg_out_extract(s, COND_AL, TCG_REG_R0, addrlo, + TARGET_PAGE_BITS, CPU_TLB_BITS); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, + 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + } /* We checked that the offset is contained within 16 bits above. */ - if (add_off > 0xfff || (use_armv6_instructions && cmp_off > 0xff)) { + if (add_off > 0xfff + || (use_armv6_instructions && TARGET_LONG_BITS == 64 + && cmp_off > 0xff)) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, (24 << 7) | (cmp_off >> 8)); base = TCG_REG_R2; add_off -= cmp_off & 0xff00; cmp_off &= 0xff; } - - tcg_out_dat_imm(s, COND_AL, ARITH_AND, - TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + if (!use_armv7_instructions) { + tcg_out_dat_imm(s, COND_AL, ARITH_AND, + TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + } tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); @@ -1211,24 +1275,40 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, } } + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + /* Check alignment. We don't support inline unaligned acceses, but we can easily support overalignment checks. */ if (a_bits < s_bits) { a_bits = s_bits; } - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - 1); - } - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + if (use_armv7_instructions) { + tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)); + int rot = encode_imm(mask); - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, - TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + if (rot >= 0) { + tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, + rotl(mask, rot) | (rot << 7)); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + addrlo, TCG_REG_TMP, 0); + } + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, 0); + } else { + if (a_bits) { + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, + (1 << a_bits) - 1); + } + tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R0, TCG_REG_TMP, + SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + } if (TARGET_LONG_BITS == 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0)); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); } return TCG_REG_R2; @@ -2129,6 +2209,14 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = INSN_NOP; + } +} + /* Compute frame size via macros, to share between tcg_target_qemu_prologue and tcg_register_jit. */ diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73a15f7e80..b89dababf4 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -108,6 +108,7 @@ extern bool have_popcnt; #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_extrl_i64_i32 0 @@ -166,6 +167,14 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, + uintptr_t jmp_addr, uintptr_t addr) +{ + /* patch the branch destination */ + atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + /* no need to flush icache explicitly */ +} + /* This defines the natural memory order supported by this * architecture before guarantees made by various barrier * instructions. @@ -177,4 +186,9 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif +#define TCG_TARGET_NEED_POOL_LABELS + #endif diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e4b120a40c..5231056fd3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -22,7 +22,7 @@ * THE SOFTWARE. */ -#include "tcg-be-ldst.h" +#include "tcg-pool.inc.c" #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { @@ -1182,9 +1182,14 @@ static void tcg_out_branch(TCGContext *s, int call, tcg_insn_unit *dest) tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); tcg_out32(s, disp); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (uintptr_t)dest); - tcg_out_modrm(s, OPC_GRP5, - call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev, TCG_REG_R10); + /* rip-relative addressing into the constant pool. + This is 6 + 8 = 14 bytes, as compared to using an + an immediate load 10 + 6 = 16 bytes, plus we may + be able to re-use the pool constant for more calls. */ + tcg_out_opc(s, OPC_GRP5, 0, 0, 0); + tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); + new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); + tcg_out32(s, 0); } } @@ -1214,6 +1219,8 @@ static void tcg_out_nopn(TCGContext *s, int n) } #if defined(CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -2595,6 +2602,11 @@ static void tcg_target_qemu_prologue(TCGContext *s) #endif } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0x90, count); +} + static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index e9558d15bc..a8222476f0 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -131,6 +131,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -201,11 +202,17 @@ extern bool use_mips32r2_instructions; #include <sys/cachectl.h> #endif +#define TCG_TARGET_DEFAULT_MO (0) + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { cacheflush ((void *)start, stop-start, ICACHE); } -#define TCG_TARGET_DEFAULT_MO (0) +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif #endif diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 1a8169f5fc..750baadf37 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -24,8 +24,6 @@ * THE SOFTWARE. */ -#include "tcg-be-ldst.h" - #ifdef HOST_WORDS_BIGENDIAN # define MIPS_BE 1 #else @@ -1112,6 +1110,8 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) } #if defined(CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + static void * const qemu_ld_helpers[16] = { [MO_UB] = helper_ret_ldub_mmu, [MO_SB] = helper_ret_ldsb_mmu, @@ -2642,7 +2642,8 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ } -void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); flush_icache_range(jmp_addr, jmp_addr + 4); diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5a092b038a..be52ad1d2e 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -83,6 +83,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -124,7 +125,13 @@ extern bool have_isa_3_00; #endif void flush_icache_range(uintptr_t start, uintptr_t stop); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_DEFAULT_MO (0) +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif +#define TCG_TARGET_NEED_POOL_LABELS + #endif diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 1f690df20d..21d764c102 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -22,7 +22,8 @@ * THE SOFTWARE. */ -#include "tcg-be-ldst.h" +#include "elf.h" +#include "tcg-pool.inc.c" #if defined _CALL_DARWIN || defined __APPLE__ #define TCG_TARGET_CALL_DARWIN @@ -41,29 +42,8 @@ # define TCG_REG_TMP1 TCG_REG_R12 #endif -/* For the 64-bit target, we don't like the 5 insn sequence needed to build - full 64-bit addresses. Better to have a base register to which we can - apply a 32-bit displacement. - - There are generally three items of interest: - (1) helper functions in the main executable, - (2) TranslationBlock data structures, - (3) the return address in the epilogue. - - For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer - will be inside the main executable, and thus near enough to make a - pointer to the epilogue be within 2GB of all helper functions. - - For softmmu, we'll let the kernel choose the address of code_gen_buffer, - and odds are it'll be somewhere close to the main malloc arena, and so - a pointer to the epilogue will be within 2GB of the TranslationBlocks. - - For --enable-pie, everything will be kinda near everything else, - somewhere in high memory. - - Thus we choose to keep the return address in a call-saved register. */ -#define TCG_REG_RA TCG_REG_R31 -#define USE_REG_RA (TCG_TARGET_REG_BITS == 64) +#define TCG_REG_TB TCG_REG_R31 +#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) /* Shorthand for size of a pointer. Avoid promotion to unsigned. */ #define SZP ((int)sizeof(void *)) @@ -81,8 +61,6 @@ static tcg_insn_unit *tb_ret_addr; -#include "elf.h" - bool have_isa_2_06; bool have_isa_3_00; @@ -247,9 +225,12 @@ static inline void tcg_out_bc_noaddr(TCGContext *s, int insn) static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_insn_unit *target = (tcg_insn_unit *)value; + tcg_insn_unit *target; + tcg_insn_unit old; + + value += addend; + target = (tcg_insn_unit *)value; - tcg_debug_assert(addend == 0); switch (type) { case R_PPC_REL14: reloc_pc14(code_ptr, target); @@ -257,6 +238,12 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, case R_PPC_REL24: reloc_pc24(code_ptr, target); break; + case R_PPC_ADDR16: + assert(value == (int16_t)value); + old = *code_ptr; + old = deposit32(old, 0, 16, value); + *code_ptr = old; + break; default: tcg_abort(); } @@ -616,50 +603,114 @@ static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); } -static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg) +/* Emit a move into ret of arg, if it can be done in one insn. */ +static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) { - if (arg == (int16_t) arg) { + if (arg == (int16_t)arg) { tcg_out32(s, ADDI | TAI(ret, 0, arg)); - } else { + return true; + } + if (arg == (int32_t)arg && (arg & 0xffff) == 0) { tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); - if (arg & 0xffff) { - tcg_out32(s, ORI | SAI(ret, ret, arg)); - } + return true; } + return false; } -static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg) +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, bool in_prologue) { + intptr_t tb_diff; + tcg_target_long tmp; + int shift; + tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); - if (type == TCG_TYPE_I32 || arg == (int32_t)arg) { - tcg_out_movi32(s, ret, arg); - } else if (arg == (uint32_t)arg && !(arg & 0x8000)) { + + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + arg = (int32_t)arg; + } + + /* Load 16-bit immediates with one insn. */ + if (tcg_out_movi_one(s, ret, arg)) { + return; + } + + /* Load addresses within the TB with one insn. */ + tb_diff = arg - (intptr_t)s->code_gen_ptr; + if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { + tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); + return; + } + + /* Load 32-bit immediates with two insns. Note that we've already + eliminated bare ADDIS, so we know both insns are required. */ + if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { + tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); + tcg_out32(s, ORI | SAI(ret, ret, arg)); + return; + } + if (arg == (uint32_t)arg && !(arg & 0x8000)) { tcg_out32(s, ADDI | TAI(ret, 0, arg)); tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); - } else { - int32_t high; + return; + } - if (USE_REG_RA) { - intptr_t diff = arg - (intptr_t)tb_ret_addr; - if (diff == (int32_t)diff) { - tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff); - return; - } + /* Load masked 16-bit value. */ + if (arg > 0 && (arg & 0x8000)) { + tmp = arg | 0x7fff; + if ((tmp & (tmp + 1)) == 0) { + int mb = clz64(tmp + 1) + 1; + tcg_out32(s, ADDI | TAI(ret, 0, arg)); + tcg_out_rld(s, RLDICL, ret, ret, 0, mb); + return; } + } - high = arg >> 31 >> 1; - tcg_out_movi32(s, ret, high); - if (high) { - tcg_out_shli64(s, ret, ret, 32); - } - if (arg & 0xffff0000) { - tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); - } - if (arg & 0xffff) { - tcg_out32(s, ORI | SAI(ret, ret, arg)); - } + /* Load common masks with 2 insns. */ + shift = ctz64(arg); + tmp = arg >> shift; + if (tmp == (int16_t)tmp) { + tcg_out32(s, ADDI | TAI(ret, 0, tmp)); + tcg_out_shli64(s, ret, ret, shift); + return; + } + shift = clz64(arg); + if (tcg_out_movi_one(s, ret, arg << shift)) { + tcg_out_shri64(s, ret, ret, shift); + return; + } + + /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ + if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { + tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); + return; + } + + /* Use the constant pool, if possible. */ + if (!in_prologue && USE_REG_TB) { + new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, + -(intptr_t)s->code_gen_ptr); + tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); + return; + } + + tmp = arg >> 31 >> 1; + tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); + if (tmp) { + tcg_out_shli64(s, ret, ret, 32); } + if (arg & 0xffff0000) { + tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); + } + if (arg & 0xffff) { + tcg_out32(s, ORI | SAI(ret, ret, arg)); + } +} + +static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg) +{ + tcg_out_movi_int(s, type, ret, arg, false); } static bool mask_operand(uint32_t c, int *mb, int *me) @@ -1295,47 +1346,43 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, insn); } -#ifdef __powerpc64__ -void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { - tcg_insn_unit i1, i2; - uint64_t pair; - intptr_t diff = addr - jmp_addr; - - if (in_range_b(diff)) { - i1 = B | (diff & 0x3fffffc); - i2 = NOP; - } else if (USE_REG_RA) { - intptr_t lo, hi; - diff = addr - (uintptr_t)tb_ret_addr; - lo = (int16_t)diff; - hi = (int32_t)(diff - lo); - tcg_debug_assert(diff == hi + lo); - i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16); - i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo); - } else { - tcg_debug_assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr); - i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16); - i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr); - } + if (TCG_TARGET_REG_BITS == 64) { + tcg_insn_unit i1, i2; + intptr_t tb_diff = addr - tc_ptr; + intptr_t br_diff = addr - (jmp_addr + 4); + uint64_t pair; + + /* This does not exercise the range of the branch, but we do + still need to be able to load the new value of TCG_REG_TB. + But this does still happen quite often. */ + if (tb_diff == (int16_t)tb_diff) { + i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); + i2 = B | (br_diff & 0x3fffffc); + } else { + intptr_t lo = (int16_t)tb_diff; + intptr_t hi = (int32_t)(tb_diff - lo); + assert(tb_diff == hi + lo); + i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); + i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); + } #ifdef HOST_WORDS_BIGENDIAN - pair = (uint64_t)i1 << 32 | i2; + pair = (uint64_t)i1 << 32 | i2; #else - pair = (uint64_t)i2 << 32 | i1; + pair = (uint64_t)i2 << 32 | i1; #endif - atomic_set((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); -} -#else -void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) -{ - intptr_t diff = addr - jmp_addr; - tcg_debug_assert(in_range_b(diff)); - atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_icache_range(jmp_addr, jmp_addr + 4); + atomic_set((uint64_t *)jmp_addr, pair); + flush_icache_range(jmp_addr, jmp_addr + 8); + } else { + intptr_t diff = addr - jmp_addr; + tcg_debug_assert(in_range_b(diff)); + atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); + flush_icache_range(jmp_addr, jmp_addr + 4); + } } -#endif static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) { @@ -1416,6 +1463,8 @@ static const uint32_t qemu_exts_opc[4] = { }; #if defined (CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ @@ -1827,6 +1876,14 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #endif } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = NOP; + } +} + /* Parameters for function call generation, used in tcg.c. */ #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_EXTEND_ARGS 1 @@ -1895,44 +1952,20 @@ static void tcg_target_qemu_prologue(TCGContext *s) #ifndef CONFIG_SOFTMMU if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); - - if (USE_REG_RA) { -#ifdef _CALL_AIX - /* Make the caller load the value as the TOC into R2. */ - tb_ret_addr = s->code_ptr + 2; - desc[1] = tb_ret_addr; - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2); - tcg_out32(s, BCCTR | BO_ALWAYS); -#elif defined(_CALL_ELF) && _CALL_ELF == 2 - /* Compute from the incoming R12 value. */ - tb_ret_addr = s->code_ptr + 2; - tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12, - tcg_ptr_byte_diff(tb_ret_addr, s->code_buf))); - tcg_out32(s, BCCTR | BO_ALWAYS); -#else - /* Reserve max 5 insns for the constant load. */ - tb_ret_addr = s->code_ptr + 6; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr); - tcg_out32(s, BCCTR | BO_ALWAYS); - while (s->code_ptr < tb_ret_addr) { - tcg_out32(s, NOP); - } -#endif - } else { - tcg_out32(s, BCCTR | BO_ALWAYS); - tb_ret_addr = s->code_ptr; + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); } + tcg_out32(s, BCCTR | BO_ALWAYS); /* Epilogue */ - tcg_debug_assert(tb_ret_addr == s->code_ptr); - s->code_gen_epilogue = tb_ret_addr; + s->code_gen_epilogue = tb_ret_addr = s->code_ptr; tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { @@ -1952,44 +1985,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, switch (opc) { case INDEX_op_exit_tb: - if (USE_REG_RA) { - ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr); - - /* Use a direct branch if we can, otherwise use the value in RA. - Note that the direct branch is always backward, thus we need - to account for the possibility of 5 insns from the movi. */ - if (!in_range_b(disp - 20)) { - tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); - tcg_out32(s, BCCTR | BO_ALWAYS); - break; - } - } tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); tcg_out_b(s, 0, tb_ret_addr); break; case INDEX_op_goto_tb: - tcg_debug_assert(s->tb_jmp_insn_offset); - /* Direct jump. */ -#ifdef __powerpc64__ - /* Ensure the next insns are 8-byte aligned. */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); - } - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); - /* To be replaced by either a branch+nop or a load into TMP1. */ - s->code_ptr += 2; - tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); + if (s->tb_jmp_insn_offset) { + /* Direct jump. */ + if (TCG_TARGET_REG_BITS == 64) { + /* Ensure the next insns are 8-byte aligned. */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + } else { + s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + tcg_out32(s, B); + s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); + break; + } + } else { + /* Indirect jump. */ + tcg_debug_assert(s->tb_jmp_insn_offset == NULL); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, + (intptr_t)(s->tb_jmp_insn_offset + args[0])); + } + tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); -#else - /* To be replaced by a branch. */ - s->code_ptr++; -#endif - s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); + s->tb_jmp_reset_offset[args[0]] = c = tcg_current_code_size(s); + if (USE_REG_TB) { + /* For the unlinked case, need to reset TCG_REG_TB. */ + c = -c; + assert(c == (int16_t)c); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c)); + } break; case INDEX_op_goto_ptr: tcg_out32(s, MTSPR | RS(args[0]) | CTR); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, 0); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); + } + tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); tcg_out32(s, BCCTR | BO_ALWAYS); break; case INDEX_op_br: @@ -2759,8 +2796,8 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ - if (USE_REG_RA) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */ + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ } } diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index bedda5edf6..6f2b06a7d1 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -95,6 +95,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT) #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 @@ -145,4 +146,18 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, + uintptr_t jmp_addr, uintptr_t addr) +{ + /* patch the branch destination */ + intptr_t disp = addr - (jmp_addr - 2); + atomic_set((int32_t *)jmp_addr, disp / 2); + /* no need to flush icache explicitly */ +} + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif +#define TCG_TARGET_NEED_POOL_LABELS + #endif diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 38b9e791ee..e7ab8e4df3 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -24,13 +24,12 @@ * THE SOFTWARE. */ -#include "tcg-be-ldst.h" - /* We only support generating code for 64-bit mode. */ #if TCG_TARGET_REG_BITS != 64 #error "unsupported code generation mode" #endif +#include "tcg-pool.inc.c" #include "elf.h" /* ??? The translation blocks produced by TCG are generally small enough to @@ -40,11 +39,8 @@ #define TCG_CT_CONST_S16 0x100 #define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_NN16 0x400 -#define TCG_CT_CONST_NN32 0x800 -#define TCG_CT_CONST_U31 0x1000 -#define TCG_CT_CONST_S33 0x2000 -#define TCG_CT_CONST_ZERO 0x4000 +#define TCG_CT_CONST_S33 0x400 +#define TCG_CT_CONST_ZERO 0x800 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -53,6 +49,12 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R1 +/* A scratch register that holds a pointer to the beginning of the TB. + We don't need this when we have pc-relative loads with the general + instructions extension facility. */ +#define TCG_REG_TB TCG_REG_R12 +#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) + #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 #endif @@ -72,6 +74,10 @@ typedef enum S390Opcode { RIL_CGFI = 0xc20c, RIL_CLFI = 0xc20f, RIL_CLGFI = 0xc20e, + RIL_CLRL = 0xc60f, + RIL_CLGRL = 0xc60a, + RIL_CRL = 0xc60d, + RIL_CGRL = 0xc608, RIL_IIHF = 0xc008, RIL_IILF = 0xc009, RIL_LARL = 0xc000, @@ -94,6 +100,8 @@ typedef enum S390Opcode { RI_AGHI = 0xa70b, RI_AHI = 0xa70a, RI_BRC = 0xa704, + RI_CHI = 0xa70e, + RI_CGHI = 0xa70f, RI_IIHH = 0xa500, RI_IIHL = 0xa501, RI_IILH = 0xa502, @@ -203,6 +211,8 @@ typedef enum S390Opcode { RXY_AG = 0xe308, RXY_AY = 0xe35a, RXY_CG = 0xe320, + RXY_CLG = 0xe321, + RXY_CLY = 0xe355, RXY_CY = 0xe359, RXY_LAY = 0xe371, RXY_LB = 0xe376, @@ -219,6 +229,8 @@ typedef enum S390Opcode { RXY_LRVG = 0xe30f, RXY_LRVH = 0xe31f, RXY_LY = 0xe358, + RXY_NG = 0xe380, + RXY_OG = 0xe381, RXY_STCY = 0xe372, RXY_STG = 0xe324, RXY_STHY = 0xe370, @@ -227,6 +239,7 @@ typedef enum S390Opcode { RXY_STRVG = 0xe32f, RXY_STRVH = 0xe33f, RXY_STY = 0xe350, + RXY_XG = 0xe382, RX_A = 0x5a, RX_C = 0x59, @@ -356,21 +369,29 @@ uint64_t s390_facilities; static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - intptr_t pcrel2 = (tcg_insn_unit *)value - (code_ptr - 1); - tcg_debug_assert(addend == -2); + intptr_t pcrel2; + uint32_t old; + + value += addend; + pcrel2 = (tcg_insn_unit *)value - code_ptr; switch (type) { case R_390_PC16DBL: - tcg_debug_assert(pcrel2 == (int16_t)pcrel2); + assert(pcrel2 == (int16_t)pcrel2); tcg_patch16(code_ptr, pcrel2); break; case R_390_PC32DBL: - tcg_debug_assert(pcrel2 == (int32_t)pcrel2); + assert(pcrel2 == (int32_t)pcrel2); tcg_patch32(code_ptr, pcrel2); break; - default: - tcg_abort(); + case R_390_20: + assert(value == sextract64(value, 0, 20)); + old = *(uint32_t *)code_ptr & 0xf00000ff; + old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); + tcg_patch32(code_ptr, old); break; + default: + g_assert_not_reached(); } } @@ -409,26 +430,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'J': ct->ct |= TCG_CT_CONST_S32; break; - case 'N': - ct->ct |= TCG_CT_CONST_NN16; - break; - case 'M': - ct->ct |= TCG_CT_CONST_NN32; - break; - case 'C': - /* ??? We have no insight here into whether the comparison is - signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit - signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses - a 32-bit unsigned immediate. If we were to use the (semi) - obvious "val == (int32_t)val" we would be enabling unsigned - comparisons vs very large numbers. The only solution is to - take the intersection of the ranges. */ - /* ??? Another possible solution is to simply lie and allow all - constants here and force the out-of-range values into a temp - register in tgen_cmp when we have knowledge of the actual - comparison code in use. */ - ct->ct |= TCG_CT_CONST_U31; - break; case 'Z': ct->ct |= TCG_CT_CONST_ZERO; break; @@ -459,12 +460,6 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, return val == (int32_t)val; } else if (ct & TCG_CT_CONST_S33) { return val >= -0xffffffffll && val <= 0xffffffffll; - } else if (ct & TCG_CT_CONST_NN16) { - return !(val < 0 && val == (int16_t)val); - } else if (ct & TCG_CT_CONST_NN32) { - return !(val < 0 && val == (int32_t)val); - } else if (ct & TCG_CT_CONST_U31) { - return val >= 0 && val <= 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { return val == 0; } @@ -557,14 +552,16 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) } } -/* load a register with an immediate value */ -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) -{ - static const S390Opcode lli_insns[4] = { - RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH - }; +static const S390Opcode lli_insns[4] = { + RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH +}; +static const S390Opcode ii_insns[4] = { + RI_IILL, RI_IILH, RI_IIHL, RI_IIHH +}; +static bool maybe_out_small_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ tcg_target_ulong uval = sval; int i; @@ -576,17 +573,37 @@ static void tcg_out_movi(TCGContext *s, TCGType type, /* Try all 32-bit insns that can load it in one go. */ if (sval >= -0x8000 && sval < 0x8000) { tcg_out_insn(s, RI, LGHI, ret, sval); - return; + return true; } for (i = 0; i < 4; i++) { tcg_target_long mask = 0xffffull << i*16; if ((uval & mask) == uval) { tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16); - return; + return true; } } + return false; +} + +/* load a register with an immediate value */ +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long sval, bool in_prologue) +{ + tcg_target_ulong uval; + + /* Try all 32-bit insns that can load it in one go. */ + if (maybe_out_small_movi(s, type, ret, sval)) { + return; + } + + uval = sval; + if (type == TCG_TYPE_I32) { + uval = (uint32_t)sval; + sval = (int32_t)sval; + } + /* Try all 48-bit insns that can load it in one go. */ if (s390_facilities & FACILITY_EXT_IMM) { if (sval == (int32_t)sval) { @@ -598,73 +615,76 @@ static void tcg_out_movi(TCGContext *s, TCGType type, return; } if ((uval & 0xffffffff) == 0) { - tcg_out_insn(s, RIL, LLIHF, ret, uval >> 31 >> 1); + tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32); return; } } - /* Try for PC-relative address load. */ + /* Try for PC-relative address load. For odd addresses, + attempt to use an offset from the start of the TB. */ if ((sval & 1) == 0) { ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1; if (off == (int32_t)off) { tcg_out_insn(s, RIL, LARL, ret, off); return; } - } - - /* If extended immediates are not present, then we may have to issue - several instructions to load the low 32 bits. */ - if (!(s390_facilities & FACILITY_EXT_IMM)) { - /* A 32-bit unsigned value can be loaded in 2 insns. And given - that the lli_insns loop above did not succeed, we know that - both insns are required. */ - if (uval <= 0xffffffff) { - tcg_out_insn(s, RI, LLILL, ret, uval); - tcg_out_insn(s, RI, IILH, ret, uval >> 16); - return; - } - - /* If all high bits are set, the value can be loaded in 2 or 3 insns. - We first want to make sure that all the high bits get set. With - luck the low 16-bits can be considered negative to perform that for - free, otherwise we load an explicit -1. */ - if (sval >> 31 >> 1 == -1) { - if (uval & 0x8000) { - tcg_out_insn(s, RI, LGHI, ret, uval); - } else { - tcg_out_insn(s, RI, LGHI, ret, -1); - tcg_out_insn(s, RI, IILL, ret, uval); - } - tcg_out_insn(s, RI, IILH, ret, uval >> 16); + } else if (USE_REG_TB && !in_prologue) { + ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr; + if (off == sextract64(off, 0, 20)) { + /* This is certain to be an address within TB, and therefore + OFF will be negative; don't try RX_LA. */ + tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off); return; } } - /* If we get here, both the high and low parts have non-zero bits. */ - - /* Recurse to load the lower 32-bits. */ - tcg_out_movi(s, TCG_TYPE_I64, ret, uval & 0xffffffff); + /* A 32-bit unsigned value can be loaded in 2 insns. And given + that LLILL, LLIHL, LLILF above did not succeed, we know that + both insns are required. */ + if (uval <= 0xffffffff) { + tcg_out_insn(s, RI, LLILL, ret, uval); + tcg_out_insn(s, RI, IILH, ret, uval >> 16); + return; + } - /* Insert data into the high 32-bits. */ - uval = uval >> 31 >> 1; - if (s390_facilities & FACILITY_EXT_IMM) { - if (uval < 0x10000) { - tcg_out_insn(s, RI, IIHL, ret, uval); - } else if ((uval & 0xffff) == 0) { - tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + /* When allowed, stuff it in the constant pool. */ + if (!in_prologue) { + if (USE_REG_TB) { + tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, sval, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); } else { - tcg_out_insn(s, RIL, IIHF, ret, uval); + tcg_out_insn(s, RIL, LGRL, ret, 0); + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); } + return; + } + + /* What's left is for the prologue, loading GUEST_BASE, and because + it failed to match above, is known to be a full 64-bit quantity. + We could try more than this, but it probably wouldn't pay off. */ + if (s390_facilities & FACILITY_EXT_IMM) { + tcg_out_insn(s, RIL, LLILF, ret, uval); + tcg_out_insn(s, RIL, IIHF, ret, uval >> 32); } else { - if (uval & 0xffff) { - tcg_out_insn(s, RI, IIHL, ret, uval); - } - if (uval & 0xffff0000) { - tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + const S390Opcode *insns = lli_insns; + int i; + + for (i = 0; i < 4; i++) { + uint16_t part = uval >> (16 * i); + if (part) { + tcg_out_insn_RI(s, insns[i], ret, part); + insns = ii_insns; + } } } } +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ + tcg_out_movi_int(s, type, ret, sval, false); +} /* Emit a load/store type instruction. Inputs are: DATA: The register to be loaded or stored. @@ -741,6 +761,13 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) return; } } + if (USE_REG_TB) { + ptrdiff_t disp = abs - (void *)s->code_gen_ptr; + if (disp == sextract64(disp, 0, 20)) { + tcg_out_ld(s, type, dest, TCG_REG_TB, disp); + return; + } + } tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff); tcg_out_ld(s, type, dest, dest, addr & 0xffff); @@ -940,8 +967,17 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) return; } - /* Fall back to loading the constant. */ - tcg_out_movi(s, type, TCG_TMP0, val); + /* Use the constant pool if USE_REG_TB, but not for small constants. */ + if (USE_REG_TB) { + if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) { + tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + return; + } + } else { + tcg_out_movi(s, type, TCG_TMP0, val); + } if (type == TCG_TYPE_I32) { tcg_out_insn(s, RR, NR, dest, TCG_TMP0); } else { @@ -949,66 +985,97 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } } -static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val) +static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) { static const S390Opcode oi_insns[4] = { RI_OILL, RI_OILH, RI_OIHL, RI_OIHH }; - static const S390Opcode nif_insns[2] = { + static const S390Opcode oif_insns[2] = { RIL_OILF, RIL_OIHF }; int i; /* Look for no-op. */ - if (val == 0) { + if (unlikely(val == 0)) { return; } - if (s390_facilities & FACILITY_EXT_IMM) { - /* Try all 32-bit insns that can perform it in one go. */ - for (i = 0; i < 4; i++) { - tcg_target_ulong mask = (0xffffull << i*16); - if ((val & mask) != 0 && (val & ~mask) == 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); - return; - } + /* Try all 32-bit insns that can perform it in one go. */ + for (i = 0; i < 4; i++) { + tcg_target_ulong mask = (0xffffull << i*16); + if ((val & mask) != 0 && (val & ~mask) == 0) { + tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); + return; } + } - /* Try all 48-bit insns that can perform it in one go. */ + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { for (i = 0; i < 2; i++) { tcg_target_ulong mask = (0xffffffffull << i*32); if ((val & mask) != 0 && (val & ~mask) == 0) { - tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32); + tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32); return; } } + } + /* Use the constant pool if USE_REG_TB, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, OR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0); + } + } else if (USE_REG_TB) { + tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit masks in each half. */ - tgen64_ori(s, dest, val & 0x00000000ffffffffull); - tgen64_ori(s, dest, val & 0xffffffff00000000ull); - } else { - /* With no extended-immediate facility, we don't need to be so - clever. Just iterate over the insns and mask in the constant. */ - for (i = 0; i < 4; i++) { - tcg_target_ulong mask = (0xffffull << i*16); - if ((val & mask) != 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); - } - } + tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tgen_ori(s, type, dest, val & 0x00000000ffffffffull); + tgen_ori(s, type, dest, val & 0xffffffff00000000ull); } } -static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val) +static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) { - /* Perform the xor by parts. */ - if (val & 0xffffffff) { - tcg_out_insn(s, RIL, XILF, dest, val); + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { + if ((val & 0xffffffff00000000ull) == 0) { + tcg_out_insn(s, RIL, XILF, dest, val); + return; + } + if ((val & 0x00000000ffffffffull) == 0) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + return; + } } - if (val > 0xffffffff) { - tcg_out_insn(s, RIL, XIHF, dest, val >> 31 >> 1); + + /* Use the constant pool if USE_REG_TB, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, XR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0); + } + } else if (USE_REG_TB) { + tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { + /* Perform the xor by parts. */ + tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + if (val & 0xffffffff) { + tcg_out_insn(s, RIL, XILF, dest, val); + } + if (val > 0xffffffff) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + } } } @@ -1016,6 +1083,8 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, TCGArg c2, bool c2const, bool need_carry) { bool is_unsigned = is_unsigned_cond(c); + S390Opcode op; + if (c2const) { if (c2 == 0) { if (!(is_unsigned && need_carry)) { @@ -1026,44 +1095,67 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, } return tcg_cond_to_ltr_cond[c]; } - /* If we only got here because of load-and-test, - and we couldn't use that, then we need to load - the constant into a register. */ - if (!(s390_facilities & FACILITY_EXT_IMM)) { - c2 = TCG_TMP0; - tcg_out_movi(s, type, c2, 0); - goto do_reg; - } } - if (is_unsigned) { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RIL, CLFI, r1, c2); - } else { - tcg_out_insn(s, RIL, CLGFI, r1, c2); - } - } else { + + if (!is_unsigned && c2 == (int16_t)c2) { + op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI); + tcg_out_insn_RI(s, op, r1, c2); + goto exit; + } + + if (s390_facilities & FACILITY_EXT_IMM) { if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RIL, CFI, r1, c2); - } else { - tcg_out_insn(s, RIL, CGFI, r1, c2); + op = (is_unsigned ? RIL_CLFI : RIL_CFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; + } else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) { + op = (is_unsigned ? RIL_CLGFI : RIL_CGFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; } } - } else { - do_reg: - if (is_unsigned) { + + /* Use the constant pool, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) { + c2 = TCG_TMP0; + /* fall through to reg-reg */ + } else if (USE_REG_TB) { if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, CLR, r1, c2); + op = (is_unsigned ? RXY_CLY : RXY_CY); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, + 4 - (intptr_t)s->code_gen_ptr); } else { - tcg_out_insn(s, RRE, CLGR, r1, c2); + op = (is_unsigned ? RXY_CLG : RXY_CG); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, c2, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); } + goto exit; } else { if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, CR, r1, c2); + op = (is_unsigned ? RIL_CLRL : RIL_CRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, (uint32_t)c2, R_390_PC32DBL, + s->code_ptr - 2, 2 + 4); } else { - tcg_out_insn(s, RRE, CGR, r1, c2); + op = (is_unsigned ? RIL_CLGRL : RIL_CGRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2); } + goto exit; } } + + if (type == TCG_TYPE_I32) { + op = (is_unsigned ? RR_CLR : RR_CR); + tcg_out_insn_RR(s, op, r1, c2); + } else { + op = (is_unsigned ? RRE_CLGR : RRE_CGR); + tcg_out_insn_RRE(s, op, r1, c2); + } + + exit: return tcg_cond_to_s390_cond[c]; } @@ -1245,11 +1337,11 @@ static void tgen_branch(TCGContext *s, int cc, TCGLabel *l) tgen_gotoi(s, cc, l->u.value_ptr); } else if (USE_LONG_BRANCHES) { tcg_out16(s, RIL_BRCL | (cc << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, -2); + tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2); s->code_ptr += 2; } else { tcg_out16(s, RI_BRC | (cc << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, -2); + tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); s->code_ptr += 1; } } @@ -1264,7 +1356,7 @@ static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc, } else { /* We need to keep the offset unchanged for retranslation. */ off = s->code_ptr[1]; - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, -2); + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); } tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); @@ -1282,7 +1374,7 @@ static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc, } else { /* We need to keep the offset unchanged for retranslation. */ off = s->code_ptr[1]; - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, -2); + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); } tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); @@ -1458,6 +1550,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data, } #if defined(CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + /* We're expecting to use a 20-bit signed offset on the tlb memory ops. Using the offset of the second entry in the last tlb table ensures that we can index all of the elements of the first entry. */ @@ -1544,7 +1638,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; TCGMemOp opc = get_memop(oi); - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, -2); + patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS == 64) { @@ -1565,7 +1659,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) TCGMemOpIdx oi = lb->oi; TCGMemOp opc = get_memop(oi); - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, -2); + patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS == 64) { @@ -1690,6 +1784,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_goto_tb: + a0 = args[0]; if (s->tb_jmp_insn_offset) { /* branch displacement must be aligned for atomic patching; * see if we need to add extra nop before branch @@ -1697,21 +1792,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { tcg_out16(s, NOP); } + tcg_debug_assert(!USE_REG_TB); tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); s->code_ptr += 2; } else { - /* load address stored at s->tb_jmp_target_addr + args[0] */ - tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0, - s->tb_jmp_target_addr + args[0]); + /* load address stored at s->tb_jmp_target_addr + a0 */ + tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, + s->tb_jmp_target_addr + a0); /* and go there */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); + } + s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + int ofs = -tcg_current_code_size(s); + assert(ofs == (int16_t)ofs); + tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); } - s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); break; case INDEX_op_goto_ptr: - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, args[0]); + a0 = args[0]; + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); + } + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); break; OP_32_64(ld8u): @@ -1801,7 +1909,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen64_ori(s, a0, a2); + tgen_ori(s, TCG_TYPE_I32, a0, a2); } else if (a0 == a1) { tcg_out_insn(s, RR, OR, a0, a2); } else { @@ -1812,7 +1920,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen64_xori(s, a0, a2); + tgen_xori(s, TCG_TYPE_I32, a0, a2); } else if (a0 == a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); } else { @@ -2033,7 +2141,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen64_ori(s, a0, a2); + tgen_ori(s, TCG_TYPE_I64, a0, a2); } else if (a0 == a1) { tcg_out_insn(s, RRE, OGR, a0, a2); } else { @@ -2044,7 +2152,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen64_xori(s, a0, a2); + tgen_xori(s, TCG_TYPE_I64, a0, a2); } else if (a0 == a1) { tcg_out_insn(s, RRE, XGR, a0, a2); } else { @@ -2233,16 +2341,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; - static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } }; - static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } }; static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; - static const TCGTargetOpDef r_r_rM = { .args_ct_str = { "r", "r", "rM" } }; - static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; - static const TCGTargetOpDef r_0_rN = { .args_ct_str = { "r", "0", "rN" } }; - static const TCGTargetOpDef r_0_rM = { .args_ct_str = { "r", "0", "rM" } }; static const TCGTargetOpDef a2_r = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; static const TCGTargetOpDef a2_ri @@ -2280,6 +2382,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &r_r_ri; case INDEX_op_sub_i32: case INDEX_op_sub_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); case INDEX_op_mul_i32: @@ -2290,34 +2398,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_mul_i64: return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); - case INDEX_op_or_i32: - /* The use of [iNM] constraints are optimization only, since a full - 64-bit immediate OR can always be performed with 4 sequential - OI[LH][LH] instructions. By rejecting certain negative ranges, - the immediate load plus the reg-reg OR is smaller. */ - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri) - : &r_0_rN); - case INDEX_op_or_i64: - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM) - : &r_0_rN); - - case INDEX_op_xor_i32: - /* Without EXT_IMM, no immediates are supported. Otherwise, - rejecting certain negative ranges leads to smaller code. */ - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri) - : &r_0_r); - case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM) - : &r_0_r); - - case INDEX_op_and_i32: - case INDEX_op_and_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); - case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: @@ -2335,10 +2415,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &r_r_ri; case INDEX_op_brcond_i32: - /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ - return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ); case INDEX_op_brcond_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ); + return &r_ri; case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2364,6 +2442,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return &r_r; case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: return &r_r_ri; case INDEX_op_qemu_ld_i32: @@ -2380,30 +2460,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "r", "rZ", "r" } }; return &dep; } - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - { - /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ - static const TCGTargetOpDef setc_z - = { .args_ct_str = { "r", "r", "rZ" } }; - static const TCGTargetOpDef setc_c - = { .args_ct_str = { "r", "r", "rC" } }; - return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z); - } case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: { - /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ - static const TCGTargetOpDef movc_z - = { .args_ct_str = { "r", "r", "rZ", "r", "0" } }; - static const TCGTargetOpDef movc_c - = { .args_ct_str = { "r", "r", "rC", "r", "0" } }; + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "ri", "r", "0" } }; static const TCGTargetOpDef movc_l - = { .args_ct_str = { "r", "r", "rC", "rI", "0" } }; - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_LOAD_ON_COND2 - ? &movc_l : &movc_c) - : &movc_z); + = { .args_ct_str = { "r", "r", "ri", "rI", "0" } }; + return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: @@ -2476,6 +2540,9 @@ static void tcg_target_init(TCGContext *s) /* XXX many insns can't be used with R0, so we better avoid it for now */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } } #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ @@ -2496,12 +2563,17 @@ static void tcg_target_qemu_prologue(TCGContext *s) #ifndef CONFIG_SOFTMMU if (guest_base >= 0x80000) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, + tcg_target_call_iarg_regs[1]); + } + /* br %r3 (go to TB) */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); @@ -2523,6 +2595,11 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0x07, count * sizeof(tcg_insn_unit)); +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 4515c9ab48..d8339bf010 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -124,6 +124,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 #define TCG_TARGET_HAS_extrl_i64_i32 1 #define TCG_TARGET_HAS_extrh_i64_i32 1 @@ -172,4 +173,8 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) } } +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + +#define TCG_TARGET_NEED_POOL_LABELS + #endif diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 18afce2f87..bd7c1461c6 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -22,7 +22,7 @@ * THE SOFTWARE. */ -#include "tcg-be-null.h" +#include "tcg-pool.inc.c" #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { @@ -87,6 +87,9 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { # define TCG_GUEST_BASE_REG TCG_REG_I5 #endif +#define TCG_REG_TB TCG_REG_I1 +#define USE_REG_TB (sizeof(void *) > 4) + static const int tcg_target_reg_alloc_order[] = { TCG_REG_L0, TCG_REG_L1, @@ -251,6 +254,8 @@ static const int tcg_target_call_oarg_regs[] = { #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) +#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) + #ifndef ASI_PRIMARY_LITTLE #define ASI_PRIMARY_LITTLE 0x88 #endif @@ -289,33 +294,46 @@ static inline int check_fit_i32(int32_t val, unsigned int bits) static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - uint32_t insn; + uint32_t insn = *code_ptr; + intptr_t pcrel; - tcg_debug_assert(addend == 0); - value = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); + value += addend; + pcrel = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); switch (type) { case R_SPARC_WDISP16: - if (!check_fit_ptr(value >> 2, 16)) { - tcg_abort(); - } - insn = *code_ptr; + assert(check_fit_ptr(pcrel >> 2, 16)); insn &= ~INSN_OFF16(-1); - insn |= INSN_OFF16(value); - *code_ptr = insn; + insn |= INSN_OFF16(pcrel); break; case R_SPARC_WDISP19: - if (!check_fit_ptr(value >> 2, 19)) { - tcg_abort(); - } - insn = *code_ptr; + assert(check_fit_ptr(pcrel >> 2, 19)); insn &= ~INSN_OFF19(-1); - insn |= INSN_OFF19(value); - *code_ptr = insn; + insn |= INSN_OFF19(pcrel); break; + case R_SPARC_13: + /* Note that we're abusing this reloc type for our own needs. */ + if (!check_fit_ptr(value, 13)) { + int adj = (value > 0 ? 0xff8 : -0x1000); + value -= adj; + assert(check_fit_ptr(value, 13)); + *code_ptr++ = (ARITH_ADD | INSN_RD(TCG_REG_T2) + | INSN_RS1(TCG_REG_TB) | INSN_IMM13(adj)); + insn ^= INSN_RS1(TCG_REG_TB) ^ INSN_RS1(TCG_REG_T2); + } + insn &= ~INSN_IMM13(-1); + insn |= INSN_IMM13(value); + break; + case R_SPARC_32: + /* Note that we're abusing this reloc type for our own needs. */ + code_ptr[0] = deposit32(code_ptr[0], 0, 22, value >> 10); + code_ptr[1] = deposit32(code_ptr[1], 0, 10, value); + return; default: - tcg_abort(); + g_assert_not_reached(); } + + *code_ptr = insn; } /* parse target specific constraints */ @@ -425,10 +443,11 @@ static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, bool in_prologue) { tcg_target_long hi, lo = (int32_t)arg; + tcg_target_long test, lsb; /* Make sure we test 32-bit constants for imm13 properly. */ if (type == TCG_TYPE_I32) { @@ -457,6 +476,39 @@ static void tcg_out_movi(TCGContext *s, TCGType type, return; } + /* A 21-bit constant, shifted. */ + lsb = ctz64(arg); + test = (tcg_target_long)arg >> lsb; + if (check_fit_tl(test, 13)) { + tcg_out_movi_imm13(s, ret, test); + tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); + return; + } else if (lsb > 10 && test == extract64(test, 0, 21)) { + tcg_out_sethi(s, ret, test << 10); + tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); + return; + } + + if (!in_prologue) { + if (USE_REG_TB) { + intptr_t diff = arg - (uintptr_t)s->code_gen_ptr; + if (check_fit_ptr(diff, 13)) { + tcg_out_arithi(s, ret, TCG_REG_TB, diff, ARITH_ADD); + } else { + new_pool_label(s, arg, R_SPARC_13, s->code_ptr, + -(intptr_t)s->code_gen_ptr); + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); + /* May be used to extend the 13-bit range in patch_reloc. */ + tcg_out32(s, NOP); + } + } else { + new_pool_label(s, arg, R_SPARC_32, s->code_ptr, 0); + tcg_out_sethi(s, ret, 0); + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | INSN_IMM13(0)); + } + return; + } + /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi = (arg - lo) >> 32; @@ -472,6 +524,12 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static inline void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + tcg_out_movi_int(s, type, ret, arg, false); +} + static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, TCGReg a2, int op) { @@ -514,6 +572,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) { + intptr_t diff = arg - (uintptr_t)s->code_gen_ptr; + if (USE_REG_TB && check_fit_ptr(diff, 13)) { + tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); + return; + } tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); } @@ -545,7 +608,7 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1, static inline void tcg_out_nop(TCGContext *s) { - tcg_out_sethi(s, TCG_REG_G0, 0); + tcg_out32(s, NOP); } static const uint8_t tcg_cond_to_bcond[] = { @@ -814,7 +877,8 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } -static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, + bool in_prologue) { ptrdiff_t disp = tcg_pcrel_diff(s, dest); @@ -822,14 +886,15 @@ static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest) tcg_out32(s, CALL | (uint32_t)disp >> 2); } else { uintptr_t desti = (uintptr_t)dest; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, desti & ~0xfff); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, + desti & ~0xfff, in_prologue); tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); } } static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) { - tcg_out_call_nodelay(s, dest); + tcg_out_call_nodelay(s, dest, false); tcg_out_nop(s); } @@ -917,7 +982,7 @@ static void build_trampolines(TCGContext *s) /* Set the env operand. */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); /* Tail call. */ - tcg_out_call_nodelay(s, qemu_ld_helpers[i]); + tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); } @@ -966,7 +1031,7 @@ static void build_trampolines(TCGContext *s) /* Set the env operand. */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); /* Tail call. */ - tcg_out_call_nodelay(s, qemu_st_helpers[i]); + tcg_out_call_nodelay(s, qemu_st_helpers[i], true); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); } } @@ -994,11 +1059,17 @@ static void tcg_target_qemu_prologue(TCGContext *s) #ifndef CONFIG_SOFTMMU if (guest_base != 0) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif + /* We choose TCG_REG_TB such that no move is required. */ + if (USE_REG_TB) { + QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); /* delay slot */ tcg_out_nop(s); @@ -1014,6 +1085,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) #endif } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = NOP; + } +} + #if defined(CONFIG_SOFTMMU) /* Perform the TLB load and compare. @@ -1158,7 +1237,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)]; } tcg_debug_assert(func != NULL); - tcg_out_call_nodelay(s, func); + tcg_out_call_nodelay(s, func, false); /* delay slot */ tcg_out_movi(s, TCG_TYPE_I32, param, oi); @@ -1237,7 +1316,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; tcg_debug_assert(func != NULL); - tcg_out_call_nodelay(s, func); + tcg_out_call_nodelay(s, func, false); /* delay slot */ tcg_out_movi(s, TCG_TYPE_I32, param, oi); @@ -1271,30 +1350,67 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if (check_fit_ptr(a0, 13)) { tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); tcg_out_movi_imm13(s, TCG_REG_O0, a0); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); + break; + } else if (USE_REG_TB) { + intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr; + if (check_fit_ptr(tb_diff, 13)) { + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + /* Note that TCG_REG_TB has been unwound to O1. */ + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD); + break; + } } + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); break; case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* direct jump method */ - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - /* Make sure to preserve links during retranslation. */ - tcg_out32(s, CALL | (*s->code_ptr & ~INSN_OP(-1))); + if (USE_REG_TB) { + /* make sure the patch is 8-byte aligned. */ + if ((intptr_t)s->code_ptr & 4) { + tcg_out_nop(s); + } + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + tcg_out_sethi(s, TCG_REG_T1, 0); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); + tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD); + } else { + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); + tcg_out32(s, CALL); + tcg_out_nop(s); + } } else { /* indirect jump method */ - tcg_out_ld_ptr(s, TCG_REG_T1, + tcg_out_ld_ptr(s, TCG_REG_TB, (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); + tcg_out_nop(s); + } + s->tb_jmp_reset_offset[a0] = c = tcg_current_code_size(s); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + c = -c; + if (check_fit_i32(c, 13)) { + tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, + TCG_REG_T1, ARITH_ADD); + } } - tcg_out_nop(s); - s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); break; case INDEX_op_goto_ptr: tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); - tcg_out_nop(s); + if (USE_REG_TB) { + tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR); + } else { + tcg_out_nop(s); + } break; case INDEX_op_br: tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); @@ -1708,15 +1824,43 @@ void tcg_register_jit(void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } -void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { - uint32_t *ptr = (uint32_t *)jmp_addr; - uintptr_t disp = addr - jmp_addr; + intptr_t tb_disp = addr - tc_ptr; + intptr_t br_disp = addr - jmp_addr; + tcg_insn_unit i1, i2; + + /* We can reach the entire address space for ILP32. + For LP64, the code_gen_buffer can't be larger than 2GB. */ + tcg_debug_assert(tb_disp == (int32_t)tb_disp); + tcg_debug_assert(br_disp == (int32_t)br_disp); + + if (!USE_REG_TB) { + atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2)); + flush_icache_range(jmp_addr, jmp_addr + 4); + return; + } - /* We can reach the entire address space for 32-bit. For 64-bit - the code_gen_buffer can't be larger than 2GB. */ - tcg_debug_assert(disp == (int32_t)disp); + /* This does not exercise the range of the branch, but we do + still need to be able to load the new value of TCG_REG_TB. + But this does still happen quite often. */ + if (check_fit_ptr(tb_disp, 13)) { + /* ba,pt %icc, addr */ + i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A) + | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp)); + i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB) + | INSN_IMM13(tb_disp)); + } else if (tb_disp >= 0) { + i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10); + i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) + | INSN_IMM13(tb_disp & 0x3ff)); + } else { + i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10); + i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) + | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); + } - atomic_set(ptr, deposit32(CALL, 0, 30, disp >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); + atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); + flush_icache_range(jmp_addr, jmp_addr + 8); } diff --git a/tcg/tcg-be-null.h b/tcg/tcg-be-null.h deleted file mode 100644 index 5222fe29e2..0000000000 --- a/tcg/tcg-be-null.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * TCG Backend Data: No backend data - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -typedef struct TCGBackendData { - /* Empty */ - char dummy; -} TCGBackendData; - - -/* - * Initialize TB backend data at the beginning of the TB. - */ - -static inline void tcg_out_tb_init(TCGContext *s) -{ -} - -/* - * Generate TB finalization at the end of block - */ - -static inline bool tcg_out_tb_finalize(TCGContext *s) -{ - return true; -} diff --git a/tcg/tcg-be-ldst.h b/tcg/tcg-ldst.inc.c index 17777aec5a..0e14cf4357 100644 --- a/tcg/tcg-be-ldst.h +++ b/tcg/tcg-ldst.inc.c @@ -20,8 +20,6 @@ * THE SOFTWARE. */ -#ifdef CONFIG_SOFTMMU - typedef struct TCGLabelQemuLdst { bool is_ld; /* qemu_ld: true, qemu_st: false */ TCGMemOpIdx oi; @@ -35,19 +33,6 @@ typedef struct TCGLabelQemuLdst { struct TCGLabelQemuLdst *next; } TCGLabelQemuLdst; -typedef struct TCGBackendData { - TCGLabelQemuLdst *labels; -} TCGBackendData; - - -/* - * Initialize TB backend data at the beginning of the TB. - */ - -static inline void tcg_out_tb_init(TCGContext *s) -{ - s->be->labels = NULL; -} /* * Generate TB finalization at the end of block @@ -56,12 +41,12 @@ static inline void tcg_out_tb_init(TCGContext *s) static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); -static bool tcg_out_tb_finalize(TCGContext *s) +static bool tcg_out_ldst_finalize(TCGContext *s) { TCGLabelQemuLdst *lb; /* qemu_ld/st slow paths */ - for (lb = s->be->labels; lb != NULL; lb = lb->next) { + for (lb = s->ldst_labels; lb != NULL; lb = lb->next) { if (lb->is_ld) { tcg_out_qemu_ld_slow_path(s, lb); } else { @@ -85,13 +70,9 @@ static bool tcg_out_tb_finalize(TCGContext *s) static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s) { - TCGBackendData *be = s->be; TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); - l->next = be->labels; - be->labels = l; + l->next = s->ldst_labels; + s->ldst_labels = l; return l; } -#else -#include "tcg-be-null.h" -#endif /* CONFIG_SOFTMMU */ diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c new file mode 100644 index 0000000000..8a85131405 --- /dev/null +++ b/tcg/tcg-pool.inc.c @@ -0,0 +1,85 @@ +/* + * TCG Backend Data: constant pool. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +typedef struct TCGLabelPoolData { + struct TCGLabelPoolData *next; + tcg_target_ulong data; + tcg_insn_unit *label; + intptr_t addend; + int type; +} TCGLabelPoolData; + + +static void new_pool_label(TCGContext *s, tcg_target_ulong data, int type, + tcg_insn_unit *label, intptr_t addend) +{ + TCGLabelPoolData *n = tcg_malloc(sizeof(*n)); + TCGLabelPoolData *i, **pp; + + n->data = data; + n->label = label; + n->type = type; + n->addend = addend; + + /* Insertion sort on the pool. */ + for (pp = &s->pool_labels; (i = *pp) && i->data < data; pp = &i->next) { + continue; + } + n->next = *pp; + *pp = n; +} + +/* To be provided by cpu/tcg-target.inc.c. */ +static void tcg_out_nop_fill(tcg_insn_unit *p, int count); + +static bool tcg_out_pool_finalize(TCGContext *s) +{ + TCGLabelPoolData *p = s->pool_labels; + tcg_target_ulong d, *a; + + if (p == NULL) { + return true; + } + + /* ??? Round up to qemu_icache_linesize, but then do not round + again when allocating the next TranslationBlock structure. */ + a = (void *)ROUND_UP((uintptr_t)s->code_ptr, sizeof(tcg_target_ulong)); + tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); + s->data_gen_ptr = a; + + /* Ensure the first comparison fails. */ + d = p->data + 1; + + for (; p != NULL; p = p->next) { + if (p->data != d) { + d = p->data; + if (unlikely((void *)a > s->code_gen_highwater)) { + return false; + } + *a++ = d; + } + patch_reloc(p->label, p->type, (intptr_t)(a - 1), p->addend); + } + + s->code_ptr = (void *)a; + return true; +} @@ -112,10 +112,9 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); -static void tcg_out_tb_init(TCGContext *s); -static bool tcg_out_tb_finalize(TCGContext *s); - - +#ifdef TCG_TARGET_NEED_LDST_LABELS +static bool tcg_out_ldst_finalize(TCGContext *s); +#endif static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; @@ -400,6 +399,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) return NULL; } s->code_gen_ptr = next; + s->data_gen_ptr = NULL; return tb; } @@ -470,8 +470,6 @@ void tcg_func_start(TCGContext *s) s->gen_op_buf[0].prev = 0; s->gen_next_op_idx = 1; s->gen_next_parm_idx = 0; - - s->be = tcg_malloc(sizeof(TCGBackendData)); } static inline int temp_idx(TCGContext *s, TCGTemp *ts) @@ -2619,7 +2617,12 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) s->code_buf = tb->tc_ptr; s->code_ptr = tb->tc_ptr; - tcg_out_tb_init(s); +#ifdef TCG_TARGET_NEED_LDST_LABELS + s->ldst_labels = NULL; +#endif +#ifdef TCG_TARGET_NEED_POOL_LABELS + s->pool_labels = NULL; +#endif num_insns = -1; for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) { @@ -2694,9 +2697,16 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); /* Generate TB finalization at the end of block */ - if (!tcg_out_tb_finalize(s)) { +#ifdef TCG_TARGET_NEED_LDST_LABELS + if (!tcg_out_ldst_finalize(s)) { return -1; } +#endif +#ifdef TCG_TARGET_NEED_POOL_LABELS + if (!tcg_out_pool_finalize(s)) { + return -1; + } +#endif /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); @@ -652,8 +652,8 @@ struct TCGContext { /* goto_tb support */ tcg_insn_unit *code_buf; uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ - uint16_t *tb_jmp_insn_offset; /* tb->jmp_insn_offset if USE_DIRECT_JUMP */ - uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */ + uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ + uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ TCGRegSet reserved_regs; intptr_t current_frame_offset; @@ -702,6 +702,7 @@ struct TCGContext { void *code_gen_buffer; size_t code_gen_buffer_size; void *code_gen_ptr; + void *data_gen_ptr; /* Threshold to flush the translated code buffer. */ void *code_gen_highwater; @@ -712,8 +713,13 @@ struct TCGContext { CPUState *cpu; /* *_trans */ TCGv_env tcg_env; /* *_exec */ - /* The TCGBackendData structure is private to tcg-target.inc.c. */ - struct TCGBackendData *be; + /* These structures are private to tcg-target.inc.c. */ +#ifdef TCG_TARGET_NEED_LDST_LABELS + struct TCGLabelQemuLdst *ldst_labels; +#endif +#ifdef TCG_TARGET_NEED_POOL_LABELS + struct TCGLabelPoolData *pool_labels; +#endif TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8df628a319..5d692e1f4b 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -86,6 +86,7 @@ #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_extrl_i64_i32 0 @@ -197,4 +198,16 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) We prefer consistency across hosts on this. */ #define TCG_TARGET_DEFAULT_MO (0) +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, + uintptr_t jmp_addr, uintptr_t addr) +{ + /* patch the branch destination */ + atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + /* no need to flush icache explicitly */ +} + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif /* TCG_TARGET_H */ diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index b6a15569f8..94461b2baf 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -22,8 +22,6 @@ * THE SOFTWARE. */ -#include "tcg-be-null.h" - /* TODO list: * - See TODO comments in code. */ diff --git a/util/cacheinfo.c b/util/cacheinfo.c index 593940f27b..db5172d07c 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -15,16 +15,7 @@ int qemu_dcache_linesize = 0; * Operating system specific detection mechanisms. */ -#if defined(_AIX) -# include <sys/systemcfg.h> - -static void sys_cache_info(int *isize, int *dsize) -{ - *isize = _system_configuration.icache_line; - *dsize = _system_configuration.dcache_line; -} - -#elif defined(_WIN32) +#if defined(_WIN32) static void sys_cache_info(int *isize, int *dsize) { |