diff options
42 files changed, 1377 insertions, 14278 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 5ec945c9af..caf7e8aca8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1647,12 +1647,6 @@ S: Maintained F: tcg/i386/ F: disas/i386.c -IA64 target -M: Aurelien Jarno <aurelien@aurel32.net> -S: Maintained -F: tcg/ia64/ -F: disas/ia64.c - MIPS target M: Aurelien Jarno <aurelien@aurel32.net> S: Maintained diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index 70cd474c01..22642e6f75 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) += tcg-all.o obj-$(CONFIG_SOFTMMU) += cputlb.o obj-y += cpu-exec.o cpu-exec-common.o translate-all.o +obj-y += translator.o diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c new file mode 100644 index 0000000000..afa3af478a --- /dev/null +++ b/accel/tcg/translator.c @@ -0,0 +1,138 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "exec/log.h" +#include "exec/translator.h" + +/* Pairs with tcg_clear_temp_count. + To be called by #TranslatorOps.{translate_insn,tb_stop} if + (1) the target is sufficiently clean to support reporting, + (2) as and when all temporaries are known to be consumed. + For most targets, (2) is at the end of translate_insn. */ +void translator_loop_temp_check(DisasContextBase *db) +{ + if (tcg_check_temp_count()) { + qemu_log("warning: TCG temporary leaks before " + TARGET_FMT_lx "\n", db->pc_next); + } +} + +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb) +{ + int max_insns; + + /* Initialize DisasContext */ + db->tb = tb; + db->pc_first = tb->pc; + db->pc_next = db->pc_first; + db->is_jmp = DISAS_NEXT; + db->num_insns = 0; + db->singlestep_enabled = cpu->singlestep_enabled; + + /* Instruction counting */ + max_insns = db->tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + if (db->singlestep_enabled || singlestep) { + max_insns = 1; + } + + max_insns = ops->init_disas_context(db, cpu, max_insns); + tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ + + /* Reset the temp count so that we can identify leaks */ + tcg_clear_temp_count(); + + /* Start translating. */ + gen_tb_start(db->tb); + ops->tb_start(db, cpu); + tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ + + while (true) { + db->num_insns++; + ops->insn_start(db, cpu); + tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ + + /* Pass breakpoint hits to target for further processing */ + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc == db->pc_next) { + if (ops->breakpoint_check(db, cpu, bp)) { + break; + } + } + } + /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate + that only one more instruction is to be executed. Otherwise + it should use DISAS_NORETURN when generating an exception, + but may use a DISAS_TARGET_* value for Something Else. */ + if (db->is_jmp > DISAS_TOO_MANY) { + break; + } + } + + /* Disassemble one instruction. The translate_insn hook should + update db->pc_next and db->is_jmp to indicate what should be + done next -- either exiting this loop or locate the start of + the next instruction. */ + if (db->num_insns == max_insns && (db->tb->cflags & CF_LAST_IO)) { + /* Accept I/O on the last instruction. */ + gen_io_start(); + ops->translate_insn(db, cpu); + gen_io_end(); + } else { + ops->translate_insn(db, cpu); + } + + /* Stop translation if translate_insn so indicated. */ + if (db->is_jmp != DISAS_NEXT) { + break; + } + + /* Stop translation if the output buffer is full, + or we have executed all of the allowed instructions. */ + if (tcg_op_buf_full() || db->num_insns >= max_insns) { + db->is_jmp = DISAS_TOO_MANY; + break; + } + } + + /* Emit code to exit the TB, as indicated by db->is_jmp. */ + ops->tb_stop(db, cpu); + gen_tb_end(db->tb, db->num_insns); + + /* The disas_log hook may use these values rather than recompute. */ + db->tb->size = db->pc_next - db->pc_first; + db->tb->icount = db->num_insns; + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) + && qemu_log_in_addr_range(db->pc_first)) { + qemu_log_lock(); + qemu_log("----------------\n"); + ops->disas_log(db, cpu); + qemu_log("\n"); + qemu_log_unlock(); + } +#endif +} @@ -634,9 +634,6 @@ case "$cpu" in cpu="$cpu" supported_cpu="yes" ;; - ia64) - cpu="$cpu" - ;; i386|i486|i586|i686|i86pc|BePC) cpu="i386" supported_cpu="yes" @@ -6459,9 +6456,6 @@ for i in $ARCH $TARGET_BASE_ARCH ; do i386|x86_64|x32) disas_config "I386" ;; - ia64*) - disas_config "IA64" - ;; lm32) disas_config "LM32" ;; @@ -313,8 +313,6 @@ void disas(FILE *out, void *code, unsigned long size) print_insn = print_insn_s390; #elif defined(__hppa__) print_insn = print_insn_hppa; -#elif defined(__ia64__) - print_insn = print_insn_ia64; #endif if (print_insn == NULL) { print_insn = print_insn_od_host; diff --git a/disas/Makefile.objs b/disas/Makefile.objs index 62632ef0dd..194648fb1a 100644 --- a/disas/Makefile.objs +++ b/disas/Makefile.objs @@ -11,7 +11,6 @@ arm-a64.o-cflags := -I$(libvixldir) -Wno-sign-compare common-obj-$(CONFIG_CRIS_DIS) += cris.o common-obj-$(CONFIG_HPPA_DIS) += hppa.o common-obj-$(CONFIG_I386_DIS) += i386.o -common-obj-$(CONFIG_IA64_DIS) += ia64.o common-obj-$(CONFIG_M68K_DIS) += m68k.o common-obj-$(CONFIG_MICROBLAZE_DIS) += microblaze.o common-obj-$(CONFIG_MIPS_DIS) += mips.o diff --git a/disas/i386.c b/disas/i386.c index f1e376ca4a..a557e678ec 100644 --- a/disas/i386.c +++ b/disas/i386.c @@ -683,6 +683,8 @@ fetch_data(struct disassemble_info *info, bfd_byte *addr) #define PREGRP105 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 105 } } #define PREGRP106 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 106 } } #define PREGRP107 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 107 } } +#define PREGRP108 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 108 } } +#define PREGRP109 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 109 } } #define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } } #define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } } @@ -1484,7 +1486,7 @@ static const unsigned char threebyte_0x38_uses_REPNZ_prefix[256] = { /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 1,1,0,0,0,0,0,1,0,0,0,0,0,0,0,0, /* ff */ + /* f0 */ 1,1,0,0,0,1,0,1,0,0,0,0,0,0,0,0, /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1508,7 +1510,7 @@ static const unsigned char threebyte_0x38_uses_REPZ_prefix[256] = { /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0, /* ff */ + /* f0 */ 0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0, /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1556,7 +1558,7 @@ static const unsigned char threebyte_0x3a_uses_REPNZ_prefix[256] = { /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* f0 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -2808,6 +2810,22 @@ static const struct dis386 prefix_user_table[][4] = { { "bsfS", { Gv, Ev } }, { "(bad)", { XX } }, }, + + /* PREGRP108 */ + { + { "bzhi", { Gv, Ev, Bv } }, + { "pext", { Gv, Bv, Ev } }, + { "(bad)", { XX } }, + { "pdep", { Gv, Bv, Ev } }, + }, + + /* PREGRP109 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "rorx", { Gv, Ev, Ib } }, + }, }; static const struct dis386 x86_64_table[][2] = { @@ -3108,7 +3126,7 @@ static const struct dis386 three_byte_table[][256] = { { PREGRP105 }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREGRP108 }, { "(bad)", { XX } }, { PREGRP106 }, /* f8 */ @@ -3394,7 +3412,7 @@ static const struct dis386 three_byte_table[][256] = { { "(bad)", { XX } }, { "(bad)", { XX } }, /* f0 */ - { "(bad)", { XX } }, + { PREGRP109 }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -3559,6 +3577,7 @@ ckvexprefix (void) } else { /* Two byte VEX prefix. */ newrex |= (vex2 & 0x80 ? 0 : REX_R); + newpfx |= PREFIX_VEX_0F; codep += 2; } diff --git a/disas/ia64.c b/disas/ia64.c deleted file mode 100644 index 140754c944..0000000000 --- a/disas/ia64.c +++ /dev/null @@ -1,10600 +0,0 @@ -/* ia64-dis.c -- Disassemble ia64 instructions - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, see - <http://www.gnu.org/licenses/>. */ - -#include "qemu/osdep.h" - -#include "disas/bfd.h" - -/* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006 - Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ - - -typedef uint64_t ia64_insn; - -enum ia64_insn_type - { - IA64_TYPE_NIL = 0, /* illegal type */ - IA64_TYPE_A, /* integer alu (I- or M-unit) */ - IA64_TYPE_I, /* non-alu integer (I-unit) */ - IA64_TYPE_M, /* memory (M-unit) */ - IA64_TYPE_B, /* branch (B-unit) */ - IA64_TYPE_F, /* floating-point (F-unit) */ - IA64_TYPE_X, /* long encoding (X-unit) */ - IA64_TYPE_DYN, /* Dynamic opcode */ - IA64_NUM_TYPES - }; - -enum ia64_unit - { - IA64_UNIT_NIL = 0, /* illegal unit */ - IA64_UNIT_I, /* integer unit */ - IA64_UNIT_M, /* memory unit */ - IA64_UNIT_B, /* branching unit */ - IA64_UNIT_F, /* floating-point unit */ - IA64_UNIT_L, /* long "unit" */ - IA64_UNIT_X, /* may be integer or branch unit */ - IA64_NUM_UNITS - }; - -/* Changes to this enumeration must be propagated to the operand table in - bfd/cpu-ia64-opc.c - */ -enum ia64_opnd - { - IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ - - /* constants */ - IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ - IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ - IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ - IA64_OPND_C1, /* the constant 1 */ - IA64_OPND_C8, /* the constant 8 */ - IA64_OPND_C16, /* the constant 16 */ - IA64_OPND_GR0, /* gr0 */ - IA64_OPND_IP, /* instruction pointer (ip) */ - IA64_OPND_PR, /* predicate register (pr) */ - IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ - IA64_OPND_PSR, /* processor status register (psr) */ - IA64_OPND_PSR_L, /* processor status register L (psr.l) */ - IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ - - /* register operands: */ - IA64_OPND_AR3, /* third application register # (bits 20-26) */ - IA64_OPND_B1, /* branch register # (bits 6-8) */ - IA64_OPND_B2, /* branch register # (bits 13-15) */ - IA64_OPND_CR3, /* third control register # (bits 20-26) */ - IA64_OPND_F1, /* first floating-point register # */ - IA64_OPND_F2, /* second floating-point register # */ - IA64_OPND_F3, /* third floating-point register # */ - IA64_OPND_F4, /* fourth floating-point register # */ - IA64_OPND_P1, /* first predicate # */ - IA64_OPND_P2, /* second predicate # */ - IA64_OPND_R1, /* first register # */ - IA64_OPND_R2, /* second register # */ - IA64_OPND_R3, /* third register # */ - IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ - - /* memory operands: */ - IA64_OPND_MR3, /* memory at addr of third register # */ - - /* indirect operands: */ - IA64_OPND_CPUID_R3, /* cpuid[reg] */ - IA64_OPND_DBR_R3, /* dbr[reg] */ - IA64_OPND_DTR_R3, /* dtr[reg] */ - IA64_OPND_ITR_R3, /* itr[reg] */ - IA64_OPND_IBR_R3, /* ibr[reg] */ - IA64_OPND_MSR_R3, /* msr[reg] */ - IA64_OPND_PKR_R3, /* pkr[reg] */ - IA64_OPND_PMC_R3, /* pmc[reg] */ - IA64_OPND_PMD_R3, /* pmd[reg] */ - IA64_OPND_RR_R3, /* rr[reg] */ - - /* immediate operands: */ - IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ - IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ - IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ - IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ - IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ - IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ - IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ - IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ - IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ - IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ - IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ - IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ - IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ - IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ - IA64_OPND_SOF, /* 8-bit stack frame size */ - IA64_OPND_SOL, /* 8-bit size of locals */ - IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ - IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ - IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ - IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ - IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ - IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ - IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ - IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ - IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ - IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ - IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ - IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ - IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ - IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ - IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ - IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ - IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ - IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ - IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ - IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ - IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ - IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ - IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ - IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ - IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ - IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ - - IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ - }; - -enum ia64_dependency_mode -{ - IA64_DV_RAW, - IA64_DV_WAW, - IA64_DV_WAR, -}; - -enum ia64_dependency_semantics -{ - IA64_DVS_NONE, - IA64_DVS_IMPLIED, - IA64_DVS_IMPLIEDF, - IA64_DVS_DATA, - IA64_DVS_INSTR, - IA64_DVS_SPECIFIC, - IA64_DVS_STOP, - IA64_DVS_OTHER, -}; - -enum ia64_resource_specifier -{ - IA64_RS_ANY, - IA64_RS_AR_K, - IA64_RS_AR_UNAT, - IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ - IA64_RS_ARb, /* 48-63, 112-127 */ - IA64_RS_BR, - IA64_RS_CFM, - IA64_RS_CPUID, - IA64_RS_CR_IRR, - IA64_RS_CR_LRR, - IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */ - IA64_RS_DBR, - IA64_RS_FR, - IA64_RS_FRb, - IA64_RS_GR0, - IA64_RS_GR, - IA64_RS_IBR, - IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ - IA64_RS_MSR, - IA64_RS_PKR, - IA64_RS_PMC, - IA64_RS_PMD, - IA64_RS_PR, /* non-rotating, 1-15 */ - IA64_RS_PRr, /* rotating, 16-62 */ - IA64_RS_PR63, - IA64_RS_RR, - - IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ - IA64_RS_CRX, /* CRs not in RS_CR */ - IA64_RS_PSR, /* PSR bits */ - IA64_RS_RSE, /* implementation-specific RSE resources */ - IA64_RS_AR_FPSR, -}; - -enum ia64_rse_resource -{ - IA64_RSE_N_STACKED_PHYS, - IA64_RSE_BOF, - IA64_RSE_STORE_REG, - IA64_RSE_LOAD_REG, - IA64_RSE_BSPLOAD, - IA64_RSE_RNATBITINDEX, - IA64_RSE_CFLE, - IA64_RSE_NDIRTY, -}; - -/* Information about a given resource dependency */ -struct ia64_dependency -{ - /* Name of the resource */ - const char *name; - /* Does this dependency need further specification? */ - enum ia64_resource_specifier specifier; - /* Mode of dependency */ - enum ia64_dependency_mode mode; - /* Dependency semantics */ - enum ia64_dependency_semantics semantics; - /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ -#define REG_NONE (-1) - int regindex; - /* Special info on semantics */ - const char *info; -}; - -/* Two arrays of indexes into the ia64_dependency table. - chks are dependencies to check for conflicts when an opcode is - encountered; regs are dependencies to register (mark as used) when an - opcode is used. chks correspond to readers (RAW) or writers (WAW or - WAR) of a resource, while regs correspond to writers (RAW or WAW) and - readers (WAR) of a resource. */ -struct ia64_opcode_dependency -{ - int nchks; - const unsigned short *chks; - int nregs; - const unsigned short *regs; -}; - -/* encode/extract the note/index for a dependency */ -#define RDEP(N,X) (((N)<<11)|(X)) -#define NOTE(X) (((X)>>11)&0x1F) -#define DEP(X) ((X)&0x7FF) - -/* A template descriptor describes the execution units that are active - for each of the three slots. It also specifies the location of - instruction group boundaries that may be present between two slots. */ -struct ia64_templ_desc - { - int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ - enum ia64_unit exec_unit[3]; - const char *name; - }; - -/* The opcode table is an array of struct ia64_opcode. */ - -struct ia64_opcode - { - /* The opcode name. */ - const char *name; - - /* The type of the instruction: */ - enum ia64_insn_type type; - - /* Number of output operands: */ - int num_outputs; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - ia64_insn opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - ia64_insn mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - enum ia64_opnd operands[5]; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned int flags; - - /* Used by ia64_find_next_opcode (). */ - short ent_index; - - /* Opcode dependencies. */ - const struct ia64_opcode_dependency *dependencies; - }; - -/* Values defined for the flags field of a struct ia64_opcode. */ - -#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ -#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ -#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ -#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ -#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ -#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ -#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ -#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ -#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ -#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ -#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ - -/* A macro to extract the major opcode from an instruction. */ -#define IA64_OP(i) (((i) >> 37) & 0xf) - -enum ia64_operand_class - { - IA64_OPND_CLASS_CST, /* constant */ - IA64_OPND_CLASS_REG, /* register */ - IA64_OPND_CLASS_IND, /* indirect register */ - IA64_OPND_CLASS_ABS, /* absolute value */ - IA64_OPND_CLASS_REL, /* IP-relative value */ - }; - -/* The operands table is an array of struct ia64_operand. */ - -struct ia64_operand -{ - enum ia64_operand_class class; - - /* Set VALUE as the operand bits for the operand of type SELF in the - instruction pointed to by CODE. If an error occurs, *CODE is not - modified and the returned string describes the cause of the - error. If no error occurs, NULL is returned. */ - const char *(*insert) (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code); - - /* Extract the operand bits for an operand of type SELF from - instruction CODE store them in *VALUE. If an error occurs, the - cause of the error is described by the string returned. If no - error occurs, NULL is returned. */ - const char *(*extract) (const struct ia64_operand *self, ia64_insn code, - ia64_insn *value); - - /* A string whose meaning depends on the operand class. */ - - const char *str; - - struct bit_field - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - } - field[4]; /* no operand has more than this many bit-fields */ - - unsigned int flags; - - const char *desc; /* brief description */ -}; - -/* Values defined for the flags field of a struct ia64_operand. */ - -/* Disassemble as signed decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) -/* Disassemble as unsigned decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) - -#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) - -static const char* -ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) -{ - return "internal error---this shouldn't happen"; -} - -static const char* -ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) -{ - return "internal error---this shouldn't happen"; -} - -static const char* -ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) -{ - return 0; -} - -static const char* -ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) -{ - return 0; -} - -static const char* -ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - if (value >= 1u << self->field[0].bits) - return "register number out of range"; - - *code |= value << self->field[0].shift; - return 0; -} - -static const char* -ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - *valuep = ((code >> self->field[0].shift) - & ((1u << self->field[0].bits) - 1)); - return 0; -} - -static const char* -ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - ia64_insn new = 0; - int i; - - for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1)) - << self->field[i].shift); - value >>= self->field[i].bits; - } - if (value) - return "integer operand out of range"; - - *code |= new; - return 0; -} - -static const char* -ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - uint64_t value = 0; - int i, bits = 0, total = 0; - - for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - bits = self->field[i].bits; - value |= ((code >> self->field[i].shift) - & ((((uint64_t) 1) << bits) - 1)) << total; - total += bits; - } - *valuep = value; - return 0; -} - -static const char* -ins_immu5b (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code) -{ - if (value < 32 || value > 63) - return "value must be between 32 and 63"; - return ins_immu (self, value - 32, code); -} - -static const char* -ext_immu5b (const struct ia64_operand *self, ia64_insn code, - ia64_insn *valuep) -{ - const char *result; - - result = ext_immu (self, code, valuep); - if (result) - return result; - - *valuep = *valuep + 32; - return 0; -} - -static const char* -ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - if (value & 0x7) - return "value not an integer multiple of 8"; - return ins_immu (self, value >> 3, code); -} - -static const char* -ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - const char *result; - - result = ext_immu (self, code, valuep); - if (result) - return result; - - *valuep = *valuep << 3; - return 0; -} - -static const char* -ins_imms_scaled (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code, int scale) -{ - int64_t svalue = value, sign_bit = 0; - ia64_insn new = 0; - int i; - - svalue >>= scale; - - for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1)) - << self->field[i].shift); - sign_bit = (svalue >> (self->field[i].bits - 1)) & 1; - svalue >>= self->field[i].bits; - } - if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1)) - return "integer operand out of range"; - - *code |= new; - return 0; -} - -static const char* -ext_imms_scaled (const struct ia64_operand *self, ia64_insn code, - ia64_insn *valuep, int scale) -{ - int i, bits = 0, total = 0; - int64_t val = 0, sign; - - for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - bits = self->field[i].bits; - val |= ((code >> self->field[i].shift) - & ((((uint64_t) 1) << bits) - 1)) << total; - total += bits; - } - /* sign extend: */ - sign = (int64_t) 1 << (total - 1); - val = (val ^ sign) - sign; - - *valuep = (val << scale); - return 0; -} - -static const char* -ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; - - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - return ext_imms_scaled (self, code, valuep, 0); -} - -static const char* -ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - --value; - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code) -{ - value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; - - --value; - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - const char *res = ext_imms_scaled (self, code, valuep, 0); - - ++*valuep; - return res; -} - -static const char* -ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - return ins_imms_scaled (self, value, code, 1); -} - -static const char* -ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - return ext_imms_scaled (self, code, valuep, 1); -} - -static const char* -ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - return ins_imms_scaled (self, value, code, 4); -} - -static const char* -ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - return ext_imms_scaled (self, code, valuep, 4); -} - -static const char* -ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - return ins_imms_scaled (self, value, code, 16); -} - -static const char* -ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - return ext_imms_scaled (self, code, valuep, 16); -} - -static const char* -ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1; - return ins_immu (self, value ^ mask, code); -} - -static const char* -ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - const char *result; - ia64_insn mask; - - mask = (((ia64_insn) 1) << self->field[0].bits) - 1; - result = ext_immu (self, code, valuep); - if (!result) - { - mask = (((ia64_insn) 1) << self->field[0].bits) - 1; - *valuep ^= mask; - } - return result; -} - -static const char* -ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - --value; - if (value >= ((uint64_t) 1) << self->field[0].bits) - return "count out of range"; - - *code |= value << self->field[0].shift; - return 0; -} - -static const char* -ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - *valuep = ((code >> self->field[0].shift) - & ((((uint64_t) 1) << self->field[0].bits) - 1)) + 1; - return 0; -} - -static const char* -ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - --value; - - if (value > 2) - return "count must be in range 1..3"; - - *code |= value << self->field[0].shift; - return 0; -} - -static const char* -ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - *valuep = ((code >> self->field[0].shift) & 0x3) + 1; - return 0; -} - -static const char* -ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - switch (value) - { - case 0: value = 0; break; - case 7: value = 1; break; - case 15: value = 2; break; - case 16: value = 3; break; - default: return "count must be 0, 7, 15, or 16"; - } - *code |= value << self->field[0].shift; - return 0; -} - -static const char* -ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - ia64_insn value; - - value = (code >> self->field[0].shift) & 0x3; - switch (value) - { - case 0: value = 0; break; - case 1: value = 7; break; - case 2: value = 15; break; - case 3: value = 16; break; - } - *valuep = value; - return 0; -} - -static const char* -ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - int64_t val = value; - uint64_t sign = 0; - - if (val < 0) - { - sign = 0x4; - value = -value; - } - switch (value) - { - case 1: value = 3; break; - case 4: value = 2; break; - case 8: value = 1; break; - case 16: value = 0; break; - default: return "count must be +/- 1, 4, 8, or 16"; - } - *code |= (sign | value) << self->field[0].shift; - return 0; -} - -static const char* -ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep) -{ - int64_t val; - int negate; - - val = (code >> self->field[0].shift) & 0x7; - negate = val & 0x4; - switch (val & 0x3) - { - case 0: val = 16; break; - case 1: val = 8; break; - case 2: val = 4; break; - case 3: val = 1; break; - } - if (negate) - val = -val; - - *valuep = val; - return 0; -} - -/* glib.h defines ABS so we must undefine it to avoid a clash */ -#undef ABS - -#define CST IA64_OPND_CLASS_CST -#define REG IA64_OPND_CLASS_REG -#define IND IA64_OPND_CLASS_IND -#define ABS IA64_OPND_CLASS_ABS -#define REL IA64_OPND_CLASS_REL - -#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED -#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED - -const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] = - { - /* constants: */ - { CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" }, - { CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" }, - { CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" }, - { CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" }, - { CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" }, - { CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" }, - { CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" }, - { CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" }, - { CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" }, - { CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" }, - { CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" }, - { CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" }, - { CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" }, - { CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" }, - - /* register operands: */ - { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */ - "an application register" }, - { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */ - "a branch register" }, - { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */ - "a branch register"}, - { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */ - "a control register"}, - { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */ - "a predicate register" }, - { REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */ - "a predicate register" }, - { REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */ - "a general register" }, - { REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */ - "a general register" }, - { REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */ - "a general register" }, - { REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */ - "a general register r0-r3" }, - - /* memory operands: */ - { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */ - "a memory address" }, - - /* indirect operands: */ - { IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */ - "a cpuid register" }, - { IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */ - "a dbr register" }, - { IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */ - "a dtr register" }, - { IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */ - "an itr register" }, - { IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */ - "an ibr register" }, - { IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */ - "an msr register" }, - { IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */ - "a pkr register" }, - { IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */ - "a pmc register" }, - { IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */ - "a pmd register" }, - { IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */ - "an rr register" }, - - /* immediate operands: */ - { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */ - "a 5-bit count (0-31)" }, - { ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */ - "a 2-bit count (1-4)" }, - { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */ - "a 2-bit count (1-3)" }, - { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */ - "a count (0, 7, 15, or 16)" }, - { ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */ - "a 5-bit count (0-31)" }, - { ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */ - "a 6-bit count (0-63)" }, - { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */ - "a 6-bit bit pos (0-63)" }, - { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */ - "a 6-bit bit pos (0-63)" }, - { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */ - "a 6-bit bit pos (0-63)" }, - { ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */ - "a 1-bit integer (-1, 0)" }, - { ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */ - "a 2-bit unsigned (0-3)" }, - { ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */ - "a 5-bit unsigned (32 + (0-31))" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */ - "a 7-bit unsigned (0-127)" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */ - "a 7-bit unsigned (0-127)" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */ - "a frame size (register count)" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */ - "a local register count" }, - { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */ - "a rotating register count (integer multiple of 8)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM8 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer (-128-127)" }, - { ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" }, - { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer (-127-128)" }, - { ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" }, - { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" }, - { ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */ - "a 9-bit unsigned (0-511)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM9a */ - {{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC, - "a 9-bit integer (-256-255)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM9b */ - {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC, - "a 9-bit integer (-256-255)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM14 */ - {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC, - "a 14-bit integer (-8192-8191)" }, - { ABS, ins_imms1, ext_imms1, 0, /* IMM17 */ - {{ 7, 6}, { 8, 24}, { 1, 36}}, 0, - "a 17-bit integer (-65536-65535)" }, - { ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */ - "a 21-bit unsigned" }, - { ABS, ins_imms, ext_imms, 0, /* IMM22 */ - {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC, - "a 22-bit signed integer" }, - { ABS, ins_immu, ext_immu, 0, /* IMMU24 */ - {{21, 6}, { 2, 31}, { 1, 36}}, 0, - "a 24-bit unsigned" }, - { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */ - "a 44-bit unsigned (least 16 bits ignored/zeroes)" }, - { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */ - "a 62-bit unsigned" }, - { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */ - "a 64-bit unsigned" }, - { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */ - "an increment (+/- 1, 4, 8, or 16)" }, - { ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */ - "a 4-bit length (1-16)" }, - { ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */ - "a 6-bit length (1-64)" }, - { ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */ - "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" }, - { ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */ - "an 8-bit mix type" }, - { ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */ - "a 6-bit bit pos (0-63)" }, - { REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */ - "a branch tag" }, - { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */ - "a branch tag" }, - { REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */ - "a branch target" }, - { REL, ins_imms4, ext_imms4, 0, /* TGT25b */ - {{ 7, 6}, {13, 20}, { 1, 36}}, 0, - "a branch target" }, - { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */ - "a branch target" }, - { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */ - "a branch target" }, - - { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */ - "ldxmov target" }, - }; - - -/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. - Copyright 1999, 2000 Free Software Foundation, Inc. - Contributed by Bob Manson of Cygnus Support <manson@cygnus.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, see - <http://www.gnu.org/licenses/>. */ - -/* The primary opcode table is made up of the following: */ -struct ia64_main_table -{ - /* The entry in the string table that corresponds to the name of this - opcode. */ - unsigned short name_index; - - /* The type of opcode; corresponds to the TYPE field in - struct ia64_opcode. */ - unsigned char opcode_type; - - /* The number of outputs for this opcode. */ - unsigned char num_outputs; - - /* The base insn value for this opcode. It may be modified by completers. */ - ia64_insn opcode; - - /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ - ia64_insn mask; - - /* The operands of this instruction. Corresponds to the OPERANDS field - in struct ia64_opcode. */ - unsigned char operands[5]; - - /* The flags for this instruction. Corresponds to the FLAGS field in - struct ia64_opcode. */ - short flags; - - /* The tree of completers for this instruction; this is an offset into - completer_table. */ - short completers; -}; - -/* Each instruction has a set of possible "completers", or additional - suffixes that can alter the instruction's behavior, and which has - potentially different dependencies. - - The completer entries modify certain bits in the instruction opcode. - Which bits are to be modified are marked by the BITS, MASK and - OFFSET fields. The completer entry may also note dependencies for the - opcode. - - These completers are arranged in a DAG; the pointers are indexes - into the completer_table array. The completer DAG is searched by - find_completer () and ia64_find_matching_opcode (). - - Note that each completer needs to be applied in turn, so that if we - have the instruction - cmp.lt.unc - the completer entries for both "lt" and "unc" would need to be applied - to the opcode's value. - - Some instructions do not require any completers; these contain an - empty completer entry. Instructions that require a completer do - not contain an empty entry. - - Terminal completers (those completers that validly complete an - instruction) are marked by having the TERMINAL_COMPLETER flag set. - - Only dependencies listed in the terminal completer for an opcode are - considered to apply to that opcode instance. */ - -struct ia64_completer_table -{ - /* The bit value that this completer sets. */ - unsigned int bits; - - /* And its mask. 1s are bits that are to be modified in the - instruction. */ - unsigned int mask; - - /* The entry in the string table that corresponds to the name of this - completer. */ - unsigned short name_index; - - /* An alternative completer, or -1 if this is the end of the chain. */ - short alternative; - - /* A pointer to the DAG of completers that can potentially follow - this one, or -1. */ - short subentries; - - /* The bit offset in the instruction where BITS and MASK should be - applied. */ - unsigned char offset : 7; - - unsigned char terminal_completer : 1; - - /* Index into the dependency list table */ - short dependencies; -}; - -/* This contains sufficient information for the disassembler to resolve - the complete name of the original instruction. */ -struct ia64_dis_names -{ - /* COMPLETER_INDEX represents the tree of completers that make up - the instruction. The LSB represents the top of the tree for the - specified instruction. - - A 0 bit indicates to go to the next alternate completer via the - alternative field; a 1 bit indicates that the current completer - is part of the instruction, and to go down the subentries index. - We know we've reached the final completer when we run out of 1 - bits. - - There is always at least one 1 bit. */ - unsigned int completer_index : 20; - - /* The index in the main_table[] array for the instruction. */ - unsigned short insn_index : 11; - - /* If set, the next entry in this table is an alternate possibility - for this instruction encoding. Which one to use is determined by - the instruction type and other factors (see opcode_verify ()). */ - unsigned int next_flag : 1; - - /* The disassembly priority of this entry among instructions. */ - unsigned short priority; -}; - -static const char * const ia64_strings[] = { - "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", - "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", - "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16", - "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", - "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", - "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", - "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", - "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", - "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", - "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", - "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", - "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", - "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", - "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia", - "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8", - "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le", - "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many", - "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", - "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", - "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1", - "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1", - "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", - "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", - "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", - "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", - "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig", - "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2", - "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1", - "sxt2", "sxt4", "sync", "tak", "tbit", "tf", "thash", "tnat", "tpa", - "trunc", "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4", - "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", "x", "xchg1", "xchg2", - "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", - "zxt4", -}; - -static const struct ia64_dependency -dependencies[] = { - { "ALAT", 0, 0, 0, -1, NULL, }, - { "AR[BSP]", 26, 0, 2, 17, NULL, }, - { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, }, - { "AR[CCV]", 26, 0, 2, 32, NULL, }, - { "AR[CFLG]", 26, 0, 2, 27, NULL, }, - { "AR[CSD]", 26, 0, 2, 25, NULL, }, - { "AR[EC]", 26, 0, 2, 66, NULL, }, - { "AR[EFLAG]", 26, 0, 2, 24, NULL, }, - { "AR[FCR]", 26, 0, 2, 21, NULL, }, - { "AR[FDR]", 26, 0, 2, 30, NULL, }, - { "AR[FIR]", 26, 0, 2, 29, NULL, }, - { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].traps", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].rv", 30, 0, 2, -1, NULL, }, - { "AR[FSR]", 26, 0, 2, 28, NULL, }, - { "AR[ITC]", 26, 0, 2, 44, NULL, }, - { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, - { "AR[LC]", 26, 0, 2, 65, NULL, }, - { "AR[PFS]", 26, 0, 2, 64, NULL, }, - { "AR[PFS]", 26, 0, 2, 64, NULL, }, - { "AR[PFS]", 26, 0, 0, 64, NULL, }, - { "AR[RNAT]", 26, 0, 2, 19, NULL, }, - { "AR[RSC]", 26, 0, 2, 16, NULL, }, - { "AR[SSD]", 26, 0, 2, 26, NULL, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, }, - { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 0, -1, NULL, }, - { "CPUID#", 7, 0, 5, -1, NULL, }, - { "CR[CMCV]", 27, 0, 3, 74, NULL, }, - { "CR[DCR]", 27, 0, 3, 0, NULL, }, - { "CR[EOI]", 27, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", }, - { "CR[GPTA]", 27, 0, 3, 9, NULL, }, - { "CR[IFA]", 27, 0, 1, 20, NULL, }, - { "CR[IFA]", 27, 0, 3, 20, NULL, }, - { "CR[IFS]", 27, 0, 3, 23, NULL, }, - { "CR[IFS]", 27, 0, 1, 23, NULL, }, - { "CR[IFS]", 27, 0, 1, 23, NULL, }, - { "CR[IHA]", 27, 0, 3, 25, NULL, }, - { "CR[IIM]", 27, 0, 3, 24, NULL, }, - { "CR[IIP]", 27, 0, 3, 19, NULL, }, - { "CR[IIP]", 27, 0, 1, 19, NULL, }, - { "CR[IIPA]", 27, 0, 3, 22, NULL, }, - { "CR[IPSR]", 27, 0, 3, 16, NULL, }, - { "CR[IPSR]", 27, 0, 1, 16, NULL, }, - { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, }, - { "CR[ISR]", 27, 0, 3, 17, NULL, }, - { "CR[ITIR]", 27, 0, 3, 21, NULL, }, - { "CR[ITIR]", 27, 0, 1, 21, NULL, }, - { "CR[ITM]", 27, 0, 3, 1, NULL, }, - { "CR[ITV]", 27, 0, 3, 72, NULL, }, - { "CR[IVA]", 27, 0, 4, 2, NULL, }, - { "CR[IVR]", 27, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vector Register (IVR Ð CR65)\" on page 2:118", }, - { "CR[LID]", 27, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID Ð CR64)\" on page 2:117", }, - { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, }, - { "CR[PMV]", 27, 0, 3, 73, NULL, }, - { "CR[PTA]", 27, 0, 3, 8, NULL, }, - { "CR[TPR]", 27, 0, 3, 66, NULL, }, - { "CR[TPR]", 27, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register (TPR Ð CR66)\" on page 2:119", }, - { "CR[TPR]", 27, 0, 1, 66, NULL, }, - { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, }, - { "DBR#", 11, 0, 2, -1, NULL, }, - { "DBR#", 11, 0, 3, -1, NULL, }, - { "DTC", 0, 0, 3, -1, NULL, }, - { "DTC", 0, 0, 2, -1, NULL, }, - { "DTC", 0, 0, 0, -1, NULL, }, - { "DTC", 0, 0, 2, -1, NULL, }, - { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, - { "DTR", 0, 0, 3, -1, NULL, }, - { "DTR", 0, 0, 2, -1, NULL, }, - { "DTR", 0, 0, 3, -1, NULL, }, - { "DTR", 0, 0, 0, -1, NULL, }, - { "DTR", 0, 0, 2, -1, NULL, }, - { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, }, - { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, }, - { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, }, - { "GR0", 14, 0, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, }, - { "IBR#", 16, 0, 2, -1, NULL, }, - { "InService*", 17, 0, 3, -1, NULL, }, - { "InService*", 17, 0, 2, -1, NULL, }, - { "InService*", 17, 0, 2, -1, NULL, }, - { "IP", 0, 0, 0, -1, NULL, }, - { "ITC", 0, 0, 4, -1, NULL, }, - { "ITC", 0, 0, 2, -1, NULL, }, - { "ITC", 0, 0, 0, -1, NULL, }, - { "ITC", 0, 0, 4, -1, NULL, }, - { "ITC", 0, 0, 2, -1, NULL, }, - { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 4, -1, NULL, }, - { "ITR", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 0, -1, NULL, }, - { "ITR", 0, 0, 4, -1, NULL, }, - { "memory", 0, 0, 0, -1, NULL, }, - { "MSR#", 18, 0, 5, -1, NULL, }, - { "PKR#", 19, 0, 3, -1, NULL, }, - { "PKR#", 19, 0, 0, -1, NULL, }, - { "PKR#", 19, 0, 2, -1, NULL, }, - { "PKR#", 19, 0, 2, -1, NULL, }, - { "PMC#", 20, 0, 2, -1, NULL, }, - { "PMC#", 20, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter Registers\" for PMC[0].fr on page 2:150", }, - { "PMD#", 21, 0, 2, -1, NULL, }, - { "PR0", 0, 0, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, }, - { "PR63", 24, 0, 2, -1, NULL, }, - { "PR63", 24, 0, 2, -1, NULL, }, - { "PR63", 24, 0, 0, -1, NULL, }, - { "PSR.ac", 28, 0, 1, 3, NULL, }, - { "PSR.ac", 28, 0, 3, 3, NULL, }, - { "PSR.ac", 28, 0, 2, 3, NULL, }, - { "PSR.ac", 28, 0, 2, 3, NULL, }, - { "PSR.be", 28, 0, 1, 1, NULL, }, - { "PSR.be", 28, 0, 3, 1, NULL, }, - { "PSR.be", 28, 0, 2, 1, NULL, }, - { "PSR.be", 28, 0, 2, 1, NULL, }, - { "PSR.bn", 28, 0, 2, 44, NULL, }, - { "PSR.cpl", 28, 0, 1, 32, NULL, }, - { "PSR.cpl", 28, 0, 2, 32, NULL, }, - { "PSR.da", 28, 0, 2, 38, NULL, }, - { "PSR.db", 28, 0, 3, 24, NULL, }, - { "PSR.db", 28, 0, 2, 24, NULL, }, - { "PSR.db", 28, 0, 2, 24, NULL, }, - { "PSR.dd", 28, 0, 2, 39, NULL, }, - { "PSR.dfh", 28, 0, 3, 19, NULL, }, - { "PSR.dfh", 28, 0, 2, 19, NULL, }, - { "PSR.dfh", 28, 0, 2, 19, NULL, }, - { "PSR.dfl", 28, 0, 3, 18, NULL, }, - { "PSR.dfl", 28, 0, 2, 18, NULL, }, - { "PSR.dfl", 28, 0, 2, 18, NULL, }, - { "PSR.di", 28, 0, 3, 22, NULL, }, - { "PSR.di", 28, 0, 2, 22, NULL, }, - { "PSR.di", 28, 0, 2, 22, NULL, }, - { "PSR.dt", 28, 0, 3, 17, NULL, }, - { "PSR.dt", 28, 0, 2, 17, NULL, }, - { "PSR.dt", 28, 0, 2, 17, NULL, }, - { "PSR.ed", 28, 0, 2, 43, NULL, }, - { "PSR.i", 28, 0, 2, 14, NULL, }, - { "PSR.ia", 28, 0, 0, 14, NULL, }, - { "PSR.ic", 28, 0, 2, 13, NULL, }, - { "PSR.ic", 28, 0, 3, 13, NULL, }, - { "PSR.ic", 28, 0, 2, 13, NULL, }, - { "PSR.id", 28, 0, 0, 14, NULL, }, - { "PSR.is", 28, 0, 0, 14, NULL, }, - { "PSR.it", 28, 0, 2, 14, NULL, }, - { "PSR.lp", 28, 0, 2, 25, NULL, }, - { "PSR.lp", 28, 0, 3, 25, NULL, }, - { "PSR.lp", 28, 0, 2, 25, NULL, }, - { "PSR.mc", 28, 0, 2, 35, NULL, }, - { "PSR.mfh", 28, 0, 2, 5, NULL, }, - { "PSR.mfl", 28, 0, 2, 4, NULL, }, - { "PSR.pk", 28, 0, 3, 15, NULL, }, - { "PSR.pk", 28, 0, 2, 15, NULL, }, - { "PSR.pk", 28, 0, 2, 15, NULL, }, - { "PSR.pp", 28, 0, 2, 21, NULL, }, - { "PSR.ri", 28, 0, 0, 41, NULL, }, - { "PSR.rt", 28, 0, 2, 27, NULL, }, - { "PSR.rt", 28, 0, 3, 27, NULL, }, - { "PSR.rt", 28, 0, 2, 27, NULL, }, - { "PSR.si", 28, 0, 2, 23, NULL, }, - { "PSR.si", 28, 0, 3, 23, NULL, }, - { "PSR.si", 28, 0, 2, 23, NULL, }, - { "PSR.sp", 28, 0, 2, 20, NULL, }, - { "PSR.sp", 28, 0, 3, 20, NULL, }, - { "PSR.sp", 28, 0, 2, 20, NULL, }, - { "PSR.ss", 28, 0, 2, 40, NULL, }, - { "PSR.tb", 28, 0, 3, 26, NULL, }, - { "PSR.tb", 28, 0, 2, 26, NULL, }, - { "PSR.tb", 28, 0, 2, 26, NULL, }, - { "PSR.up", 28, 0, 2, 2, NULL, }, - { "PSR.vm", 28, 0, 1, 46, NULL, }, - { "PSR.vm", 28, 0, 2, 46, NULL, }, - { "RR#", 25, 0, 3, -1, NULL, }, - { "RR#", 25, 0, 2, -1, NULL, }, - { "RSE", 29, 0, 2, -1, NULL, }, - { "ALAT", 0, 1, 0, -1, NULL, }, - { "AR[BSP]", 26, 1, 2, 17, NULL, }, - { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, }, - { "AR[CCV]", 26, 1, 2, 32, NULL, }, - { "AR[CFLG]", 26, 1, 2, 27, NULL, }, - { "AR[CSD]", 26, 1, 2, 25, NULL, }, - { "AR[EC]", 26, 1, 2, 66, NULL, }, - { "AR[EFLAG]", 26, 1, 2, 24, NULL, }, - { "AR[FCR]", 26, 1, 2, 21, NULL, }, - { "AR[FDR]", 26, 1, 2, 30, NULL, }, - { "AR[FIR]", 26, 1, 2, 29, NULL, }, - { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].rv", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].traps", 30, 1, 2, -1, NULL, }, - { "AR[FSR]", 26, 1, 2, 28, NULL, }, - { "AR[ITC]", 26, 1, 2, 44, NULL, }, - { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, - { "AR[LC]", 26, 1, 2, 65, NULL, }, - { "AR[PFS]", 26, 1, 0, 64, NULL, }, - { "AR[PFS]", 26, 1, 2, 64, NULL, }, - { "AR[PFS]", 26, 1, 2, 64, NULL, }, - { "AR[RNAT]", 26, 1, 2, 19, NULL, }, - { "AR[RSC]", 26, 1, 2, 16, NULL, }, - { "AR[SSD]", 26, 1, 2, 26, NULL, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, }, - { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, - { "CFM", 6, 1, 2, -1, NULL, }, - { "CPUID#", 7, 1, 0, -1, NULL, }, - { "CR[CMCV]", 27, 1, 2, 74, NULL, }, - { "CR[DCR]", 27, 1, 2, 0, NULL, }, - { "CR[EOI]", 27, 1, 7, 67, "SC Section 5.8.3.4, \"End of External Interrupt Register (EOI Ð CR67)\" on page 2:119", }, - { "CR[GPTA]", 27, 1, 2, 9, NULL, }, - { "CR[IFA]", 27, 1, 2, 20, NULL, }, - { "CR[IFS]", 27, 1, 2, 23, NULL, }, - { "CR[IHA]", 27, 1, 2, 25, NULL, }, - { "CR[IIM]", 27, 1, 2, 24, NULL, }, - { "CR[IIP]", 27, 1, 2, 19, NULL, }, - { "CR[IIPA]", 27, 1, 2, 22, NULL, }, - { "CR[IPSR]", 27, 1, 2, 16, NULL, }, - { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, }, - { "CR[ISR]", 27, 1, 2, 17, NULL, }, - { "CR[ITIR]", 27, 1, 2, 21, NULL, }, - { "CR[ITM]", 27, 1, 2, 1, NULL, }, - { "CR[ITV]", 27, 1, 2, 72, NULL, }, - { "CR[IVA]", 27, 1, 2, 2, NULL, }, - { "CR[IVR]", 27, 1, 7, 65, "SC", }, - { "CR[LID]", 27, 1, 7, 64, "SC", }, - { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, }, - { "CR[PMV]", 27, 1, 2, 73, NULL, }, - { "CR[PTA]", 27, 1, 2, 8, NULL, }, - { "CR[TPR]", 27, 1, 2, 66, NULL, }, - { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, }, - { "DBR#", 11, 1, 2, -1, NULL, }, - { "DTC", 0, 1, 0, -1, NULL, }, - { "DTC", 0, 1, 2, -1, NULL, }, - { "DTC", 0, 1, 2, -1, NULL, }, - { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 0, -1, NULL, }, - { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, }, - { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, }, - { "GR0", 14, 1, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, }, - { "IBR#", 16, 1, 2, -1, NULL, }, - { "InService*", 17, 1, 7, -1, "SC", }, - { "IP", 0, 1, 0, -1, NULL, }, - { "ITC", 0, 1, 0, -1, NULL, }, - { "ITC", 0, 1, 2, -1, NULL, }, - { "ITC", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 0, -1, NULL, }, - { "memory", 0, 1, 0, -1, NULL, }, - { "MSR#", 18, 1, 7, -1, "SC", }, - { "PKR#", 19, 1, 0, -1, NULL, }, - { "PKR#", 19, 1, 0, -1, NULL, }, - { "PKR#", 19, 1, 2, -1, NULL, }, - { "PMC#", 20, 1, 2, -1, NULL, }, - { "PMD#", 21, 1, 2, -1, NULL, }, - { "PR0", 0, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, - { "PR63", 24, 1, 0, -1, NULL, }, - { "PR63", 24, 1, 0, -1, NULL, }, - { "PR63", 24, 1, 2, -1, NULL, }, - { "PR63", 24, 1, 2, -1, NULL, }, - { "PSR.ac", 28, 1, 2, 3, NULL, }, - { "PSR.be", 28, 1, 2, 1, NULL, }, - { "PSR.bn", 28, 1, 2, 44, NULL, }, - { "PSR.cpl", 28, 1, 2, 32, NULL, }, - { "PSR.da", 28, 1, 2, 38, NULL, }, - { "PSR.db", 28, 1, 2, 24, NULL, }, - { "PSR.dd", 28, 1, 2, 39, NULL, }, - { "PSR.dfh", 28, 1, 2, 19, NULL, }, - { "PSR.dfl", 28, 1, 2, 18, NULL, }, - { "PSR.di", 28, 1, 2, 22, NULL, }, - { "PSR.dt", 28, 1, 2, 17, NULL, }, - { "PSR.ed", 28, 1, 2, 43, NULL, }, - { "PSR.i", 28, 1, 2, 14, NULL, }, - { "PSR.ia", 28, 1, 2, 14, NULL, }, - { "PSR.ic", 28, 1, 2, 13, NULL, }, - { "PSR.id", 28, 1, 2, 14, NULL, }, - { "PSR.is", 28, 1, 2, 14, NULL, }, - { "PSR.it", 28, 1, 2, 14, NULL, }, - { "PSR.lp", 28, 1, 2, 25, NULL, }, - { "PSR.mc", 28, 1, 2, 35, NULL, }, - { "PSR.mfh", 28, 1, 0, 5, NULL, }, - { "PSR.mfh", 28, 1, 2, 5, NULL, }, - { "PSR.mfh", 28, 1, 2, 5, NULL, }, - { "PSR.mfl", 28, 1, 0, 4, NULL, }, - { "PSR.mfl", 28, 1, 2, 4, NULL, }, - { "PSR.mfl", 28, 1, 2, 4, NULL, }, - { "PSR.pk", 28, 1, 2, 15, NULL, }, - { "PSR.pp", 28, 1, 2, 21, NULL, }, - { "PSR.ri", 28, 1, 2, 41, NULL, }, - { "PSR.rt", 28, 1, 2, 27, NULL, }, - { "PSR.si", 28, 1, 2, 23, NULL, }, - { "PSR.sp", 28, 1, 2, 20, NULL, }, - { "PSR.ss", 28, 1, 2, 40, NULL, }, - { "PSR.tb", 28, 1, 2, 26, NULL, }, - { "PSR.up", 28, 1, 2, 2, NULL, }, - { "PSR.vm", 28, 1, 2, 46, NULL, }, - { "RR#", 25, 1, 2, -1, NULL, }, - { "RSE", 29, 1, 2, -1, NULL, }, - { "PR63", 24, 2, 6, -1, NULL, }, -}; - -static const unsigned short dep0[] = { - 97, 282, 2140, 2327, -}; - -static const unsigned short dep1[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2327, 4135, 20616, -}; - -static const unsigned short dep2[] = { - 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2347, 2348, 2351, - 2352, 2355, 2356, -}; - -static const unsigned short dep3[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 20616, -}; - -static const unsigned short dep4[] = { - 97, 282, 22646, 22647, 22649, 22650, 22652, 22653, 22655, 22824, 22827, 22828, - 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep5[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 4135, 20616, 22824, 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep6[] = { - 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2347, 2349, - 2351, 2353, 2355, -}; - -static const unsigned short dep7[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2344, 2345, 2348, 2349, 2352, 2353, 2356, 4135, 20616, -}; - -static const unsigned short dep8[] = { - 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2346, 2348, 2350, - 2352, 2354, 2356, -}; - -static const unsigned short dep9[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2344, 2346, 2347, 2350, 2351, 2354, 2355, 4135, 20616, -}; - -static const unsigned short dep10[] = { - 97, 282, 2166, 2167, 2169, 2170, 2172, 2173, 2175, 2344, 2345, 2346, 2347, - 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, -}; - -static const unsigned short dep11[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2344, 2345, 2346, 2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, - 4135, 20616, -}; - -static const unsigned short dep12[] = { - 97, 282, 2395, -}; - -static const unsigned short dep13[] = { - 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2082, 2083, 2166, 2168, - 2169, 2171, 2172, 2174, 2175, 4135, -}; - -static const unsigned short dep14[] = { - 97, 163, 282, 325, 2395, 28866, 29018, -}; - -static const unsigned short dep15[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 40, 41, 97, 150, 152, 158, 162, - 164, 175, 185, 186, 188, 282, 325, 2082, 2083, 2166, 2168, 2169, 2171, 2172, - 2174, 2175, 4135, 28866, 29018, -}; - -static const unsigned short dep16[] = { - 1, 6, 40, 97, 137, 196, 201, 241, 282, 312, 2395, 28866, 29018, -}; - -static const unsigned short dep17[] = { - 1, 25, 27, 38, 40, 41, 97, 158, 162, 164, 166, 167, 175, 185, 186, 188, 196, - 201, 241, 282, 312, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175, - 4135, 28866, 29018, -}; - -static const unsigned short dep18[] = { - 1, 40, 51, 97, 196, 241, 248, 282, 28866, 29018, -}; - -static const unsigned short dep19[] = { - 1, 38, 40, 41, 97, 158, 160, 161, 162, 175, 185, 190, 191, 196, 241, 248, - 282, 4135, 28866, 29018, -}; - -static const unsigned short dep20[] = { - 40, 97, 241, 282, -}; - -static const unsigned short dep21[] = { - 97, 158, 162, 175, 185, 241, 282, -}; - -static const unsigned short dep22[] = { - 1, 40, 97, 131, 135, 136, 138, 139, 142, 143, 146, 149, 152, 155, 156, 157, - 158, 161, 162, 163, 164, 167, 168, 169, 170, 173, 174, 175, 178, 181, 184, - 185, 188, 189, 191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316, - 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333, - 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 28866, 29018, -}; - -static const unsigned short dep23[] = { - 1, 38, 40, 41, 50, 51, 55, 58, 73, 97, 137, 138, 158, 162, 175, 185, 190, - 191, 196, 241, 282, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, - 320, 321, 322, 323, 324, 325, 326, 327, 328, 330, 331, 333, 334, 335, 336, - 337, 338, 339, 340, 341, 342, 343, 344, 4135, 28866, 29018, -}; - -static const unsigned short dep24[] = { - 97, 136, 282, 311, -}; - -static const unsigned short dep25[] = { - 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 311, -}; - -static const unsigned short dep26[] = { - 97, 137, 282, 312, -}; - -static const unsigned short dep27[] = { - 25, 26, 97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 312, - -}; - -static const unsigned short dep28[] = { - 97, 190, 282, 344, -}; - -static const unsigned short dep29[] = { - 97, 98, 101, 105, 108, 137, 138, 158, 162, 164, 175, 185, 282, 344, -}; - -static const unsigned short dep30[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175, - 4135, -}; - -static const unsigned short dep31[] = { - 1, 25, 40, 97, 196, 228, 229, 241, 282, 2082, 2285, 2288, 2395, 28866, 29018, - -}; - -static const unsigned short dep32[] = { - 1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228, - 230, 241, 282, 2082, 2083, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286, - 2288, 4135, 28866, 29018, -}; - -static const unsigned short dep33[] = { - 97, 282, -}; - -static const unsigned short dep34[] = { - 97, 158, 162, 175, 185, 282, 2082, 2084, -}; - -static const unsigned short dep35[] = { - 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2168, 2169, 2171, - 2172, 2174, 2175, 4135, -}; - -static const unsigned short dep36[] = { - 6, 37, 38, 39, 97, 125, 126, 201, 241, 282, 307, 308, 2395, -}; - -static const unsigned short dep37[] = { - 6, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 241, 282, 307, - 308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135, -}; - -static const unsigned short dep38[] = { - 24, 97, 227, 282, 2395, -}; - -static const unsigned short dep39[] = { - 24, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 227, 282, 2166, 2168, 2169, - 2171, 2172, 2174, 2175, 4135, -}; - -static const unsigned short dep40[] = { - 6, 24, 37, 38, 39, 97, 125, 126, 201, 227, 241, 282, 307, 308, 2395, -}; - -static const unsigned short dep41[] = { - 6, 24, 37, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 201, 227, 241, 282, - 307, 308, 347, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 4135, -}; - -static const unsigned short dep42[] = { - 1, 6, 38, 40, 41, 97, 137, 138, 158, 162, 164, 175, 185, 186, 188, 196, 228, - 230, 241, 282, 2166, 2168, 2169, 2171, 2172, 2174, 2175, 2286, 2288, 4135, - 28866, 29018, -}; - -static const unsigned short dep43[] = { - 97, 158, 162, 175, 185, 282, -}; - -static const unsigned short dep44[] = { - 15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, - 22832, 22835, 22836, -}; - -static const unsigned short dep45[] = { - 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep46[] = { - 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325, - 18601, 18602, 18761, 18762, 18764, 18765, 22646, 22647, 22648, 22650, 22651, - 22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep47[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, - 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135, - 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 22824, 22827, 22828, - 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep48[] = { - 16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, - 22832, 22835, 22836, -}; - -static const unsigned short dep49[] = { - 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep50[] = { - 17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, - 22832, 22835, 22836, -}; - -static const unsigned short dep51[] = { - 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep52[] = { - 18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, - 22832, 22835, 22836, -}; - -static const unsigned short dep53[] = { - 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, 22824, 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep54[] = { - 15, 97, 210, 211, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - -}; - -static const unsigned short dep55[] = { - 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, -}; - -static const unsigned short dep56[] = { - 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2136, 2325, - 18601, 18602, 18761, 18762, 18764, 18765, -}; - -static const unsigned short dep57[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, - 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2325, 4135, - 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, -}; - -static const unsigned short dep58[] = { - 16, 97, 213, 214, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - -}; - -static const unsigned short dep59[] = { - 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, -}; - -static const unsigned short dep60[] = { - 17, 97, 216, 217, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - -}; - -static const unsigned short dep61[] = { - 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, -}; - -static const unsigned short dep62[] = { - 18, 97, 219, 220, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, - -}; - -static const unsigned short dep63[] = { - 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, - 18764, 18766, -}; - -static const unsigned short dep64[] = { - 97, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, -}; - -static const unsigned short dep65[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, - 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, -}; - -static const unsigned short dep66[] = { - 11, 97, 206, 282, -}; - -static const unsigned short dep67[] = { - 11, 40, 41, 97, 158, 162, 175, 185, 206, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep68[] = { - 11, 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep69[] = { - 12, 97, 207, 282, -}; - -static const unsigned short dep70[] = { - 11, 40, 41, 97, 158, 162, 175, 185, 207, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep71[] = { - 13, 97, 208, 282, -}; - -static const unsigned short dep72[] = { - 11, 40, 41, 97, 158, 162, 175, 185, 208, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep73[] = { - 14, 97, 209, 282, -}; - -static const unsigned short dep74[] = { - 11, 40, 41, 97, 158, 162, 175, 185, 209, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep75[] = { - 15, 97, 211, 212, 282, -}; - -static const unsigned short dep76[] = { - 40, 41, 97, 158, 162, 175, 185, 211, 212, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep77[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep78[] = { - 16, 97, 214, 215, 282, -}; - -static const unsigned short dep79[] = { - 40, 41, 97, 158, 162, 175, 185, 214, 215, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep80[] = { - 17, 97, 217, 218, 282, -}; - -static const unsigned short dep81[] = { - 40, 41, 97, 158, 162, 175, 185, 217, 218, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep82[] = { - 18, 97, 220, 221, 282, -}; - -static const unsigned short dep83[] = { - 40, 41, 97, 158, 162, 175, 185, 220, 221, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep84[] = { - 15, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167, - 2170, 2173, 4135, -}; - -static const unsigned short dep85[] = { - 15, 16, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, - 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep86[] = { - 15, 17, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, - 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep87[] = { - 15, 18, 19, 20, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, - 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep88[] = { - 15, 97, 210, 211, 282, -}; - -static const unsigned short dep89[] = { - 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2166, 2167, 2170, - 2173, 4135, -}; - -static const unsigned short dep90[] = { - 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, -}; - -static const unsigned short dep91[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, - 216, 218, 219, 221, 282, 2166, 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep92[] = { - 16, 97, 213, 214, 282, -}; - -static const unsigned short dep93[] = { - 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2166, 2167, 2170, - 2173, 4135, -}; - -static const unsigned short dep94[] = { - 17, 97, 216, 217, 282, -}; - -static const unsigned short dep95[] = { - 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2166, 2167, 2170, - 2173, 4135, -}; - -static const unsigned short dep96[] = { - 18, 97, 219, 220, 282, -}; - -static const unsigned short dep97[] = { - 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2166, 2167, 2170, - 2173, 4135, -}; - -static const unsigned short dep98[] = { - 15, 97, 210, 211, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, - 2348, 2351, 2352, 2355, 2356, -}; - -static const unsigned short dep99[] = { - 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, - 16530, 16531, 16533, -}; - -static const unsigned short dep100[] = { - 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 2166, 2167, - 2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351, 2352, 2355, 2356, -}; - -static const unsigned short dep101[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, - 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 2344, 2347, - 2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533, -}; - -static const unsigned short dep102[] = { - 16, 97, 213, 214, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, - 2348, 2351, 2352, 2355, 2356, -}; - -static const unsigned short dep103[] = { - 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, - 16530, 16531, 16533, -}; - -static const unsigned short dep104[] = { - 17, 97, 216, 217, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, - 2348, 2351, 2352, 2355, 2356, -}; - -static const unsigned short dep105[] = { - 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, - 16530, 16531, 16533, -}; - -static const unsigned short dep106[] = { - 18, 97, 219, 220, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, - 2348, 2351, 2352, 2355, 2356, -}; - -static const unsigned short dep107[] = { - 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, - 16530, 16531, 16533, -}; - -static const unsigned short dep108[] = { - 15, 97, 210, 211, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, - 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep109[] = { - 11, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, - 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep110[] = { - 15, 16, 17, 18, 97, 210, 211, 213, 214, 216, 217, 219, 220, 282, 22646, 22647, - 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, 22831, 22832, 22835, - 22836, -}; - -static const unsigned short dep111[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 210, 212, 213, 215, - 216, 218, 219, 221, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, 4135, 16528, - 16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep112[] = { - 16, 97, 213, 214, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, - 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep113[] = { - 12, 19, 20, 40, 41, 97, 158, 162, 175, 185, 213, 215, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, - 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep114[] = { - 17, 97, 216, 217, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, - 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep115[] = { - 13, 19, 20, 40, 41, 97, 158, 162, 175, 185, 216, 218, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, - 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep116[] = { - 18, 97, 219, 220, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, - 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep117[] = { - 14, 19, 20, 40, 41, 97, 158, 162, 175, 185, 219, 221, 282, 2135, 2136, 2137, - 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, - 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep118[] = { - 97, 282, 2166, 2167, 2168, 2170, 2171, 2173, 2174, 2344, 2347, 2348, 2351, - 2352, 2355, 2356, -}; - -static const unsigned short dep119[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, - 2344, 2347, 2348, 2351, 2352, 2355, 2356, 4135, 16528, 16530, 16531, 16533, - -}; - -static const unsigned short dep120[] = { - 97, 282, 22646, 22647, 22648, 22650, 22651, 22653, 22654, 22824, 22827, 22828, - 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep121[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, - 4135, 16528, 16530, 16531, 16533, 22824, 22827, 22828, 22831, 22832, 22835, - 22836, -}; - -static const unsigned short dep122[] = { - 19, 20, 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, - 2170, 2173, 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, - -}; - -static const unsigned short dep123[] = { - 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2138, 2139, 2140, 2166, - 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep124[] = { - 97, 282, 2083, 2084, 2286, 2287, -}; - -static const unsigned short dep125[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2285, 2287, 4135, 20616, -}; - -static const unsigned short dep126[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2082, 2084, 2166, 2167, 2170, 2173, 2327, - 4135, 20616, -}; - -static const unsigned short dep127[] = { - 97, 282, 14455, 14457, 14458, 14460, 14461, 14463, 14635, 14636, 14639, 14640, - 14643, 14644, -}; - -static const unsigned short dep128[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 4135, 14635, 14636, - 14639, 14640, 14643, 14644, 20616, 24694, 24695, 24698, 24701, -}; - -static const unsigned short dep129[] = { - 97, 122, 124, 125, 127, 282, 303, 304, 307, 308, -}; - -static const unsigned short dep130[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 303, 304, 307, 308, 4135, 24694, 24695, - 24698, 24701, -}; - -static const unsigned short dep131[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2327, 4135, 20616, - -}; - -static const unsigned short dep132[] = { - 40, 41, 97, 119, 122, 125, 158, 162, 175, 185, 282, 2327, 4135, 20616, 24694, - -}; - -static const unsigned short dep133[] = { - 6, 24, 26, 27, 97, 201, 227, 230, 282, 2081, 2284, -}; - -static const unsigned short dep134[] = { - 40, 41, 97, 158, 162, 175, 185, 201, 227, 229, 282, 2138, 2139, 2140, 2166, - 2167, 2170, 2173, 2284, 4135, 20616, -}; - -static const unsigned short dep135[] = { - 6, 24, 25, 26, 40, 41, 97, 158, 162, 175, 185, 282, 2081, 2166, 2167, 2170, - 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep136[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2347, 2348, - 2351, 2352, 2355, 2356, 4135, -}; - -static const unsigned short dep137[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 4135, 22824, - 22827, 22828, 22831, 22832, 22835, 22836, -}; - -static const unsigned short dep138[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2348, - 2349, 2352, 2353, 2356, 4135, -}; - -static const unsigned short dep139[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2346, 2347, - 2350, 2351, 2354, 2355, 4135, -}; - -static const unsigned short dep140[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2166, 2167, 2170, 2173, 2344, 2345, 2346, - 2347, 2348, 2349, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 4135, -}; - -static const unsigned short dep141[] = { - 0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2166, 2167, 2170, 2173, - 4135, -}; - -static const unsigned short dep142[] = { - 0, 97, 195, 282, -}; - -static const unsigned short dep143[] = { - 0, 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 195, 282, 2166, 2167, 2170, - 2173, 4135, -}; - -static const unsigned short dep144[] = { - 40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep145[] = { - 2, 28, 97, 197, 231, 282, 28866, 29018, -}; - -static const unsigned short dep146[] = { - 1, 2, 28, 29, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 28866, 29018, - -}; - -static const unsigned short dep147[] = { - 1, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231, 282, 4135, - 28866, 29018, -}; - -static const unsigned short dep148[] = { - 0, 40, 41, 97, 158, 162, 175, 185, 195, 282, 2166, 2167, 2170, 2173, 4135, - -}; - -static const unsigned short dep149[] = { - 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, - 28, 29, 30, 31, 97, 196, 197, 198, 199, 200, 202, 203, 204, 205, 206, 207, - 208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, 223, 224, 225, 231, - 232, 233, 234, 282, 2071, 2081, 2274, 2284, 28866, 29018, -}; - -static const unsigned short dep150[] = { - 29, 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 196, 197, 198, 199, - 200, 202, 203, 204, 205, 206, 207, 208, 209, 211, 212, 214, 215, 217, 218, - 220, 221, 222, 223, 224, 225, 231, 232, 233, 234, 282, 2138, 2139, 2140, 2166, - 2167, 2170, 2173, 2274, 2284, 4135, 20616, 28866, 29018, -}; - -static const unsigned short dep151[] = { - 97, 282, 14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666, - 14667, 14669, 14670, 14679, -}; - -static const unsigned short dep152[] = { - 40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 2166, 2167, 2170, 2173, 4135, - 14645, 14646, 14666, 14667, 14669, 14670, 14679, -}; - -static const unsigned short dep153[] = { - 14464, 14466, 14468, 14470, 14505, 14506, 14525, 14645, 14646, 14666, 14667, - 14669, 14670, 14679, -}; - -static const unsigned short dep154[] = { - 183, 184, 14645, 14646, 14666, 14667, 14669, 14670, 14679, -}; - -static const unsigned short dep155[] = { - 97, 282, 14465, 14466, 14469, 14470, 14480, 14481, 14483, 14484, 14486, 14487, - 14489, 14490, 14493, 14495, 14496, 14505, 14506, 14507, 14508, 14510, 14515, - 14516, 14518, 14519, 14525, 14645, 14646, 14652, 14653, 14654, 14655, 14657, - 14659, 14666, 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, -}; - -static const unsigned short dep156[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170, - 2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666, - 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, 34888, -}; - -static const unsigned short dep157[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2166, 2167, 2170, - 2173, 4135, 14645, 14646, 14652, 14653, 14654, 14655, 14657, 14659, 14666, - 14667, 14669, 14670, 14671, 14672, 14675, 14676, 14679, -}; - -static const unsigned short dep158[] = { - 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, - 28, 29, 30, 31, 40, 41, 97, 137, 138, 158, 162, 175, 180, 181, 185, 190, 191, - 282, 2071, 2081, 2166, 2167, 2170, 2173, 2327, 4135, 20616, 28866, -}; - -static const unsigned short dep159[] = { - 43, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 56, 57, 58, 60, 61, 62, 63, - 64, 65, 67, 69, 70, 71, 72, 73, 94, 96, 97, 243, 244, 245, 246, 247, 248, - 249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261, 263, 264, 265, 281, - 282, 2116, 2310, -}; - -static const unsigned short dep160[] = { - 40, 41, 96, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191, 243, 244, - 245, 246, 247, 248, 249, 250, 251, 252, 253, 255, 256, 257, 258, 259, 261, - 263, 264, 265, 281, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2310, 4135, - 20616, -}; - -static const unsigned short dep161[] = { - 59, 95, 97, 254, 281, 282, 2140, 2327, -}; - -static const unsigned short dep162[] = { - 40, 41, 43, 44, 46, 48, 49, 51, 52, 53, 54, 56, 57, 60, 61, 63, 64, 65, 66, - 67, 69, 70, 71, 94, 95, 97, 137, 138, 158, 160, 161, 162, 175, 185, 190, 191, - 254, 281, 282, 2107, 2116, 2166, 2167, 2170, 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep163[] = { - 2, 28, 41, 97, 197, 231, 241, 282, 2140, 2327, 28866, 29018, -}; - -static const unsigned short dep164[] = { - 2, 25, 26, 28, 29, 38, 40, 41, 97, 158, 162, 175, 177, 178, 185, 197, 231, - 241, 282, 2327, 4135, 20616, 28866, 29018, -}; - -static const unsigned short dep165[] = { - 97, 129, 130, 133, 134, 140, 141, 144, 145, 147, 148, 150, 151, 153, 154, - 157, 159, 160, 165, 166, 169, 170, 171, 172, 174, 176, 177, 179, 180, 182, - 183, 186, 187, 189, 282, 309, 310, 314, 316, 317, 318, 319, 321, 323, 327, - 330, 331, 333, 334, 335, 336, 338, 339, 340, 342, 343, -}; - -static const unsigned short dep166[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 309, 310, 314, 316, - 317, 318, 319, 321, 323, 327, 330, 331, 333, 334, 335, 336, 338, 339, 340, - 342, 343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, 34888, -}; - -static const unsigned short dep167[] = { - 97, 128, 130, 132, 134, 169, 170, 189, 282, 309, 310, 330, 331, 333, 334, - 343, -}; - -static const unsigned short dep168[] = { - 40, 41, 97, 158, 162, 175, 183, 184, 185, 282, 309, 310, 330, 331, 333, 334, - 343, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep169[] = { - 40, 41, 97, 130, 131, 134, 135, 137, 138, 141, 142, 145, 146, 148, 149, 151, - 152, 154, 155, 157, 158, 159, 161, 162, 164, 165, 167, 168, 169, 170, 172, - 173, 174, 175, 176, 178, 179, 181, 182, 184, 185, 187, 188, 189, 190, 191, - 282, 2166, 2167, 2170, 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep170[] = { - 40, 41, 97, 130, 131, 134, 135, 158, 162, 169, 170, 175, 185, 189, 282, 2166, - 2167, 2170, 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep171[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 153, 155, 158, 162, 171, 173, - 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, - 20616, -}; - -static const unsigned short dep172[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 111, 137, 138, 139, 140, 142, 143, 153, 155, - 158, 162, 171, 173, 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, - 2173, 4135, 20616, -}; - -static const unsigned short dep173[] = { - 77, 78, 97, 101, 102, 269, 270, 282, 284, 285, -}; - -static const unsigned short dep174[] = { - 40, 41, 47, 62, 78, 80, 86, 97, 99, 102, 137, 138, 158, 160, 161, 162, 175, - 185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166, 2167, - 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep175[] = { - 40, 41, 47, 62, 78, 80, 97, 99, 102, 104, 106, 137, 138, 158, 160, 161, 162, - 175, 185, 190, 191, 192, 269, 270, 282, 284, 285, 2138, 2139, 2140, 2166, - 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep176[] = { - 97, 282, 12480, 12481, 12633, -}; - -static const unsigned short dep177[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 12633, 20616, -}; - -static const unsigned short dep178[] = { - 97, 282, 6219, 6220, 6411, -}; - -static const unsigned short dep179[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 6411, 20616, -}; - -static const unsigned short dep180[] = { - 97, 282, 6237, 6424, -}; - -static const unsigned short dep181[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 6424, 20616, -}; - -static const unsigned short dep182[] = { - 97, 282, 6255, 6256, 6257, 6258, 6435, 6437, 8484, -}; - -static const unsigned short dep183[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 6258, 6436, 6437, 8304, 8483, 20616, -}; - -static const unsigned short dep184[] = { - 97, 282, 6259, 6260, 6438, -}; - -static const unsigned short dep185[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 6438, 20616, -}; - -static const unsigned short dep186[] = { - 97, 282, 6261, 6439, -}; - -static const unsigned short dep187[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 6439, 20616, -}; - -static const unsigned short dep188[] = { - 97, 282, 10350, 10530, -}; - -static const unsigned short dep189[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 10530, 20616, -}; - -static const unsigned short dep190[] = { - 77, 78, 82, 83, 97, 101, 102, 269, 270, 272, 273, 282, 284, 285, -}; - -static const unsigned short dep191[] = { - 40, 41, 47, 62, 78, 80, 83, 86, 97, 99, 102, 137, 138, 158, 160, 161, 162, - 175, 185, 190, 191, 192, 269, 270, 272, 274, 282, 284, 285, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep192[] = { - 77, 78, 97, 101, 102, 104, 105, 269, 270, 282, 284, 285, 286, 287, -}; - -static const unsigned short dep193[] = { - 40, 41, 47, 62, 78, 80, 97, 99, 102, 104, 106, 137, 138, 158, 160, 161, 162, - 175, 185, 190, 191, 192, 269, 270, 282, 284, 285, 286, 287, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep194[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 2327, 4135, 12481, 20616, -}; - -static const unsigned short dep195[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 2327, 4135, 6219, 20616, -}; - -static const unsigned short dep196[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 2327, 4135, 6237, 20616, -}; - -static const unsigned short dep197[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 2327, 4135, 6257, 8303, 20616, -}; - -static const unsigned short dep198[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 2327, 4135, 6259, 20616, -}; - -static const unsigned short dep199[] = { - 40, 41, 97, 137, 138, 158, 162, 175, 183, 184, 185, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 2327, 4135, 6260, 6261, 20616, -}; - -static const unsigned short dep200[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2327, 4135, 10350, 20616, -}; - -static const unsigned short dep201[] = { - 40, 41, 97, 158, 162, 175, 185, 190, 191, 282, 2138, 2139, 2140, 2166, 2167, - 2170, 2173, 2327, 4135, 6186, 20616, -}; - -static const unsigned short dep202[] = { - 77, 79, 80, 97, 98, 99, 100, 268, 269, 282, 283, 284, -}; - -static const unsigned short dep203[] = { - 40, 41, 78, 79, 83, 85, 97, 100, 102, 104, 107, 137, 138, 158, 162, 175, 185, - 190, 191, 192, 268, 270, 282, 283, 285, 2138, 2139, 2140, 2166, 2167, 2170, - 2173, 4135, 20616, -}; - -static const unsigned short dep204[] = { - 77, 79, 80, 81, 97, 98, 99, 100, 103, 268, 269, 271, 282, 283, 284, -}; - -static const unsigned short dep205[] = { - 40, 41, 78, 79, 81, 83, 85, 97, 100, 102, 103, 104, 107, 137, 138, 158, 162, - 175, 185, 190, 191, 192, 268, 270, 271, 282, 283, 285, 2138, 2139, 2140, 2166, - 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep206[] = { - 77, 79, 80, 84, 85, 86, 97, 98, 99, 100, 268, 269, 274, 275, 282, 283, 284, - -}; - -static const unsigned short dep207[] = { - 40, 41, 78, 79, 83, 85, 97, 100, 102, 137, 138, 158, 162, 175, 185, 190, 191, - 192, 268, 270, 273, 275, 282, 283, 285, 2138, 2139, 2140, 2166, 2167, 2170, - 2173, 4135, 20616, -}; - -static const unsigned short dep208[] = { - 77, 79, 80, 97, 98, 99, 100, 106, 107, 108, 268, 269, 282, 283, 284, 287, - 288, -}; - -static const unsigned short dep209[] = { - 40, 41, 78, 79, 97, 100, 102, 104, 107, 137, 138, 158, 162, 175, 185, 190, - 191, 192, 268, 270, 282, 283, 285, 286, 288, 2138, 2139, 2140, 2166, 2167, - 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep210[] = { - 40, 41, 46, 70, 97, 158, 162, 175, 185, 190, 191, 192, 282, 2138, 2139, 2140, - 2166, 2167, 2170, 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep211[] = { - 40, 41, 97, 158, 162, 175, 185, 190, 191, 192, 282, 2138, 2139, 2140, 2166, - 2167, 2170, 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep212[] = { - 40, 41, 70, 77, 82, 84, 97, 137, 138, 153, 155, 158, 162, 175, 185, 190, 191, - 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep213[] = { - 40, 41, 97, 158, 162, 164, 175, 185, 186, 188, 282, 2135, 2136, 2137, 2138, - 2139, 2140, 2166, 2167, 2170, 2173, 4135, 16528, 16530, 16531, 16533, 20616, - -}; - -static const unsigned short dep214[] = { - 40, 41, 70, 77, 82, 84, 97, 153, 155, 158, 162, 175, 185, 192, 282, 2138, - 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep215[] = { - 40, 41, 78, 79, 97, 100, 137, 138, 158, 162, 175, 185, 190, 191, 268, 270, - 282, 283, 285, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, -}; - -static const unsigned short dep216[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep217[] = { - 5, 97, 200, 282, 2140, 2327, -}; - -static const unsigned short dep218[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 200, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, - -}; - -static const unsigned short dep219[] = { - 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, 185, - 190, 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, - 20616, -}; - -static const unsigned short dep220[] = { - 0, 97, 195, 282, 2140, 2327, -}; - -static const unsigned short dep221[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, - 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, - 20616, -}; - -static const unsigned short dep222[] = { - 0, 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, - 135, 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, - 185, 190, 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, - 4135, 20616, -}; - -static const unsigned short dep223[] = { - 31, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, - 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, 20616, - -}; - -static const unsigned short dep224[] = { - 0, 97, 195, 282, 2327, 26715, -}; - -static const unsigned short dep225[] = { - 0, 97, 109, 195, 282, 289, -}; - -static const unsigned short dep226[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, - -}; - -static const unsigned short dep227[] = { - 0, 5, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, - -}; - -static const unsigned short dep228[] = { - 0, 31, 97, 109, 195, 234, 282, 289, -}; - -static const unsigned short dep229[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 195, 234, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 4135, 20616, - -}; - -static const unsigned short dep230[] = { - 0, 97, 109, 195, 282, 289, 2140, 2327, -}; - -static const unsigned short dep231[] = { - 0, 3, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, - 191, 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, - 20616, -}; - -static const unsigned short dep232[] = { - 0, 3, 5, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, - 135, 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, - 190, 191, 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, - 4135, 20616, -}; - -static const unsigned short dep233[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, - 191, 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, - 20616, -}; - -static const unsigned short dep234[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2135, 2136, 2137, 2166, 2167, 2170, 2173, - 2327, 4135, 16528, 16530, 16531, 16533, 20616, -}; - -static const unsigned short dep235[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 195, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, - 20616, -}; - -static const unsigned short dep236[] = { - 0, 31, 97, 109, 195, 234, 282, 289, 2140, 2327, -}; - -static const unsigned short dep237[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 195, 234, 282, 289, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2327, 4135, - 20616, -}; - -static const unsigned short dep238[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 4135, 16528, 16530, - 16531, 16533, 18761, 18763, 18764, 18766, 20616, -}; - -static const unsigned short dep239[] = { - 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, 185, - 190, 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 4135, - 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, -}; - -static const unsigned short dep240[] = { - 0, 97, 195, 282, 2136, 2325, 18601, 18602, 18761, 18762, 18764, 18765, -}; - -static const unsigned short dep241[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, - 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 4135, - 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, -}; - -static const unsigned short dep242[] = { - 0, 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, - 135, 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, - 185, 190, 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, - 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, -}; - -static const unsigned short dep243[] = { - 0, 97, 195, 282, 2137, 2325, 18601, 18602, 18761, 18762, 18764, 18765, -}; - -static const unsigned short dep244[] = { - 97, 282, 2136, 2140, 2325, 2327, 18601, 18602, 18761, 18762, 18764, 18765, - -}; - -static const unsigned short dep245[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 2327, 4135, 16528, - 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, -}; - -static const unsigned short dep246[] = { - 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, 185, - 190, 191, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 2327, - 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, -}; - -static const unsigned short dep247[] = { - 0, 97, 195, 282, 2136, 2140, 2325, 2327, 18601, 18602, 18761, 18762, 18764, - 18765, -}; - -static const unsigned short dep248[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, 135, - 137, 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, - 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, 2327, - 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, -}; - -static const unsigned short dep249[] = { - 0, 40, 41, 44, 70, 76, 77, 82, 84, 97, 109, 111, 128, 129, 131, 132, 133, - 135, 137, 138, 139, 140, 142, 143, 153, 155, 156, 158, 162, 171, 173, 175, - 185, 190, 191, 192, 195, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, 2325, - 2327, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, - -}; - -static const unsigned short dep250[] = { - 0, 97, 195, 282, 2137, 2140, 2325, 2327, 18601, 18602, 18761, 18762, 18764, - 18765, -}; - -static const unsigned short dep251[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 195, 282, 289, 2135, 2136, 2137, 2138, 2139, 2140, 2166, 2167, 2170, - 2173, 4135, 16528, 16530, 16531, 16533, 20616, -}; - -static const unsigned short dep252[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 137, 138, 139, 140, 142, 143, 153, 155, 156, - 158, 162, 171, 173, 175, 185, 192, 282, 2166, 2167, 2170, 2173, 4135, -}; - -static const unsigned short dep253[] = { - 40, 41, 70, 76, 77, 82, 84, 97, 137, 138, 139, 140, 142, 143, 153, 155, 156, - 158, 162, 171, 173, 175, 185, 192, 282, 2138, 2139, 2140, 2166, 2167, 2170, - 2173, 2327, 4135, 20616, -}; - -static const unsigned short dep254[] = { - 40, 41, 97, 158, 162, 175, 185, 282, 2138, 2139, 2140, 2166, 2167, 2170, 2173, - 2325, 4135, 16528, 16530, 16531, 16533, 18761, 18763, 18764, 18766, 20616, - -}; - -static const unsigned short dep255[] = { - 0, 40, 41, 70, 76, 77, 82, 84, 97, 111, 128, 129, 131, 132, 133, 135, 137, - 138, 139, 140, 142, 143, 153, 155, 158, 162, 171, 173, 175, 185, 190, 191, - 192, 195, 282, 289, 2135, 2136, 2137, 2138, 2139, 2140, 2166, 2167, 2170, - 2173, 2327, 4135, 16528, 16530, 16531, 16533, 20616, -}; - -static const unsigned short dep256[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 24, 26, 27, 28, 29, 30, 31, 97, 196, 197, 198, 199, 200, 201, 202, 203, - 204, 205, 206, 207, 208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, - 223, 224, 225, 227, 230, 231, 232, 233, 234, 282, 2071, 2081, 2140, 2274, - 2284, 2327, 28866, 29018, -}; - -static const unsigned short dep257[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 24, 25, 26, 28, 29, 30, 31, 40, 41, 97, 137, 138, 158, 162, 175, 180, - 181, 185, 190, 191, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, - 207, 208, 209, 211, 212, 214, 215, 217, 218, 220, 221, 222, 223, 224, 225, - 227, 229, 231, 232, 233, 234, 282, 2071, 2081, 2138, 2139, 2140, 2166, 2167, - 2170, 2173, 2274, 2284, 2327, 4135, 20616, 28866, 29018, -}; - -#define NELS(X) (sizeof(X)/sizeof(X[0])) -static const struct ia64_opcode_dependency -op_dependencies[] = { - { NELS(dep1), dep1, NELS(dep0), dep0, }, - { NELS(dep3), dep3, NELS(dep2), dep2, }, - { NELS(dep5), dep5, NELS(dep4), dep4, }, - { NELS(dep7), dep7, NELS(dep6), dep6, }, - { NELS(dep9), dep9, NELS(dep8), dep8, }, - { NELS(dep11), dep11, NELS(dep10), dep10, }, - { NELS(dep13), dep13, NELS(dep12), dep12, }, - { NELS(dep15), dep15, NELS(dep14), dep14, }, - { NELS(dep17), dep17, NELS(dep16), dep16, }, - { NELS(dep19), dep19, NELS(dep18), dep18, }, - { NELS(dep21), dep21, NELS(dep20), dep20, }, - { NELS(dep23), dep23, NELS(dep22), dep22, }, - { NELS(dep25), dep25, NELS(dep24), dep24, }, - { NELS(dep27), dep27, NELS(dep26), dep26, }, - { NELS(dep29), dep29, NELS(dep28), dep28, }, - { NELS(dep30), dep30, NELS(dep12), dep12, }, - { NELS(dep32), dep32, NELS(dep31), dep31, }, - { NELS(dep34), dep34, NELS(dep33), dep33, }, - { NELS(dep35), dep35, NELS(dep12), dep12, }, - { NELS(dep37), dep37, NELS(dep36), dep36, }, - { NELS(dep39), dep39, NELS(dep38), dep38, }, - { NELS(dep41), dep41, NELS(dep40), dep40, }, - { NELS(dep42), dep42, NELS(dep31), dep31, }, - { NELS(dep43), dep43, NELS(dep33), dep33, }, - { NELS(dep45), dep45, NELS(dep44), dep44, }, - { NELS(dep47), dep47, NELS(dep46), dep46, }, - { NELS(dep49), dep49, NELS(dep48), dep48, }, - { NELS(dep51), dep51, NELS(dep50), dep50, }, - { NELS(dep53), dep53, NELS(dep52), dep52, }, - { NELS(dep55), dep55, NELS(dep54), dep54, }, - { NELS(dep57), dep57, NELS(dep56), dep56, }, - { NELS(dep59), dep59, NELS(dep58), dep58, }, - { NELS(dep61), dep61, NELS(dep60), dep60, }, - { NELS(dep63), dep63, NELS(dep62), dep62, }, - { NELS(dep65), dep65, NELS(dep64), dep64, }, - { NELS(dep67), dep67, NELS(dep66), dep66, }, - { NELS(dep68), dep68, NELS(dep33), dep33, }, - { NELS(dep70), dep70, NELS(dep69), dep69, }, - { NELS(dep72), dep72, NELS(dep71), dep71, }, - { NELS(dep74), dep74, NELS(dep73), dep73, }, - { NELS(dep76), dep76, NELS(dep75), dep75, }, - { NELS(dep77), dep77, NELS(dep33), dep33, }, - { NELS(dep79), dep79, NELS(dep78), dep78, }, - { NELS(dep81), dep81, NELS(dep80), dep80, }, - { NELS(dep83), dep83, NELS(dep82), dep82, }, - { NELS(dep84), dep84, NELS(dep33), dep33, }, - { NELS(dep85), dep85, NELS(dep33), dep33, }, - { NELS(dep86), dep86, NELS(dep33), dep33, }, - { NELS(dep87), dep87, NELS(dep33), dep33, }, - { NELS(dep89), dep89, NELS(dep88), dep88, }, - { NELS(dep91), dep91, NELS(dep90), dep90, }, - { NELS(dep93), dep93, NELS(dep92), dep92, }, - { NELS(dep95), dep95, NELS(dep94), dep94, }, - { NELS(dep97), dep97, NELS(dep96), dep96, }, - { NELS(dep99), dep99, NELS(dep98), dep98, }, - { NELS(dep101), dep101, NELS(dep100), dep100, }, - { NELS(dep103), dep103, NELS(dep102), dep102, }, - { NELS(dep105), dep105, NELS(dep104), dep104, }, - { NELS(dep107), dep107, NELS(dep106), dep106, }, - { NELS(dep109), dep109, NELS(dep108), dep108, }, - { NELS(dep111), dep111, NELS(dep110), dep110, }, - { NELS(dep113), dep113, NELS(dep112), dep112, }, - { NELS(dep115), dep115, NELS(dep114), dep114, }, - { NELS(dep117), dep117, NELS(dep116), dep116, }, - { NELS(dep119), dep119, NELS(dep118), dep118, }, - { NELS(dep121), dep121, NELS(dep120), dep120, }, - { NELS(dep122), dep122, NELS(dep64), dep64, }, - { NELS(dep123), dep123, NELS(dep33), dep33, }, - { NELS(dep125), dep125, NELS(dep124), dep124, }, - { NELS(dep126), dep126, NELS(dep0), dep0, }, - { NELS(dep128), dep128, NELS(dep127), dep127, }, - { NELS(dep130), dep130, NELS(dep129), dep129, }, - { NELS(dep131), dep131, NELS(dep0), dep0, }, - { NELS(dep132), dep132, NELS(dep0), dep0, }, - { NELS(dep134), dep134, NELS(dep133), dep133, }, - { NELS(dep135), dep135, NELS(dep0), dep0, }, - { NELS(dep136), dep136, NELS(dep2), dep2, }, - { NELS(dep137), dep137, NELS(dep4), dep4, }, - { NELS(dep138), dep138, NELS(dep6), dep6, }, - { NELS(dep139), dep139, NELS(dep8), dep8, }, - { NELS(dep140), dep140, NELS(dep10), dep10, }, - { NELS(dep141), dep141, NELS(dep33), dep33, }, - { NELS(dep143), dep143, NELS(dep142), dep142, }, - { NELS(dep144), dep144, NELS(dep142), dep142, }, - { NELS(dep146), dep146, NELS(dep145), dep145, }, - { NELS(dep147), dep147, NELS(dep145), dep145, }, - { NELS(dep148), dep148, NELS(dep142), dep142, }, - { NELS(dep150), dep150, NELS(dep149), dep149, }, - { NELS(dep152), dep152, NELS(dep151), dep151, }, - { NELS(dep154), dep154, NELS(dep153), dep153, }, - { NELS(dep156), dep156, NELS(dep155), dep155, }, - { NELS(dep157), dep157, NELS(dep155), dep155, }, - { NELS(dep158), dep158, NELS(dep0), dep0, }, - { NELS(dep160), dep160, NELS(dep159), dep159, }, - { NELS(dep162), dep162, NELS(dep161), dep161, }, - { NELS(dep164), dep164, NELS(dep163), dep163, }, - { NELS(dep166), dep166, NELS(dep165), dep165, }, - { NELS(dep168), dep168, NELS(dep167), dep167, }, - { NELS(dep169), dep169, NELS(dep0), dep0, }, - { NELS(dep170), dep170, NELS(dep0), dep0, }, - { NELS(dep171), dep171, NELS(dep0), dep0, }, - { NELS(dep172), dep172, NELS(dep33), dep33, }, - { NELS(dep174), dep174, NELS(dep173), dep173, }, - { NELS(dep175), dep175, NELS(dep173), dep173, }, - { NELS(dep177), dep177, NELS(dep176), dep176, }, - { NELS(dep179), dep179, NELS(dep178), dep178, }, - { NELS(dep181), dep181, NELS(dep180), dep180, }, - { NELS(dep183), dep183, NELS(dep182), dep182, }, - { NELS(dep185), dep185, NELS(dep184), dep184, }, - { NELS(dep187), dep187, NELS(dep186), dep186, }, - { NELS(dep189), dep189, NELS(dep188), dep188, }, - { NELS(dep191), dep191, NELS(dep190), dep190, }, - { NELS(dep193), dep193, NELS(dep192), dep192, }, - { NELS(dep194), dep194, NELS(dep0), dep0, }, - { NELS(dep195), dep195, NELS(dep0), dep0, }, - { NELS(dep196), dep196, NELS(dep0), dep0, }, - { NELS(dep197), dep197, NELS(dep0), dep0, }, - { NELS(dep198), dep198, NELS(dep0), dep0, }, - { NELS(dep199), dep199, NELS(dep0), dep0, }, - { NELS(dep200), dep200, NELS(dep0), dep0, }, - { NELS(dep201), dep201, NELS(dep0), dep0, }, - { NELS(dep203), dep203, NELS(dep202), dep202, }, - { NELS(dep205), dep205, NELS(dep204), dep204, }, - { NELS(dep207), dep207, NELS(dep206), dep206, }, - { NELS(dep209), dep209, NELS(dep208), dep208, }, - { NELS(dep210), dep210, NELS(dep0), dep0, }, - { NELS(dep211), dep211, NELS(dep0), dep0, }, - { NELS(dep212), dep212, NELS(dep0), dep0, }, - { NELS(dep213), dep213, NELS(dep33), dep33, }, - { NELS(dep214), dep214, NELS(dep33), dep33, }, - { NELS(dep215), dep215, NELS(dep202), dep202, }, - { NELS(dep216), dep216, NELS(dep0), dep0, }, - { NELS(dep218), dep218, NELS(dep217), dep217, }, - { NELS(dep219), dep219, NELS(dep0), dep0, }, - { NELS(dep221), dep221, NELS(dep220), dep220, }, - { NELS(dep222), dep222, NELS(dep220), dep220, }, - { NELS(dep223), dep223, NELS(dep0), dep0, }, - { NELS(dep221), dep221, NELS(dep224), dep224, }, - { NELS(dep226), dep226, NELS(dep225), dep225, }, - { NELS(dep227), dep227, NELS(dep225), dep225, }, - { NELS(dep229), dep229, NELS(dep228), dep228, }, - { NELS(dep231), dep231, NELS(dep230), dep230, }, - { NELS(dep232), dep232, NELS(dep230), dep230, }, - { NELS(dep233), dep233, NELS(dep230), dep230, }, - { NELS(dep234), dep234, NELS(dep0), dep0, }, - { NELS(dep235), dep235, NELS(dep230), dep230, }, - { NELS(dep237), dep237, NELS(dep236), dep236, }, - { NELS(dep238), dep238, NELS(dep64), dep64, }, - { NELS(dep239), dep239, NELS(dep64), dep64, }, - { NELS(dep241), dep241, NELS(dep240), dep240, }, - { NELS(dep242), dep242, NELS(dep240), dep240, }, - { NELS(dep241), dep241, NELS(dep243), dep243, }, - { NELS(dep245), dep245, NELS(dep244), dep244, }, - { NELS(dep246), dep246, NELS(dep244), dep244, }, - { NELS(dep248), dep248, NELS(dep247), dep247, }, - { NELS(dep249), dep249, NELS(dep247), dep247, }, - { NELS(dep248), dep248, NELS(dep250), dep250, }, - { NELS(dep251), dep251, NELS(dep225), dep225, }, - { NELS(dep252), dep252, NELS(dep33), dep33, }, - { NELS(dep253), dep253, NELS(dep0), dep0, }, - { NELS(dep254), dep254, NELS(dep64), dep64, }, - { NELS(dep255), dep255, NELS(dep230), dep230, }, - { 0, NULL, 0, NULL, }, - { NELS(dep257), dep257, NELS(dep256), dep256, }, -}; - -static const struct ia64_completer_table -completer_table[] = { - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 95 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 95 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 594, -1, 0, 1, 6 }, - { 0x0, 0x0, 0, 657, -1, 0, 1, 18 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 162 }, - { 0x0, 0x0, 0, 756, -1, 0, 1, 18 }, - { 0x0, 0x0, 0, 2198, -1, 0, 1, 10 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, - { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, 2406, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, 1140, -1, 0, 1, 129 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 45 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 84 }, - { 0x0, 0x0, 0, 2246, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 2473, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 2250, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, 2252, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 2482, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 2485, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 2507, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 2510, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 36 }, - { 0x0, 0x0, 0, 2518, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 1409, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 162 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 83 }, - { 0x0, 0x0, 0, 1457, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1466, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1475, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1477, -1, 0, 1, 132 }, - { 0x0, 0x0, 0, 1479, -1, 0, 1, 132 }, - { 0x0, 0x0, 0, 1488, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1497, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1506, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1515, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1524, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1533, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1543, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1553, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1563, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, 1572, -1, 0, 1, 147 }, - { 0x0, 0x0, 0, 1578, -1, 0, 1, 152 }, - { 0x0, 0x0, 0, 1584, -1, 0, 1, 152 }, - { 0x0, 0x0, 0, 1590, -1, 0, 1, 147 }, - { 0x0, 0x0, 0, 1596, -1, 0, 1, 152 }, - { 0x0, 0x0, 0, 1602, -1, 0, 1, 152 }, - { 0x0, 0x0, 0, 1608, -1, 0, 1, 147 }, - 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220, 2432, -1, 0, 1, 54 }, - { 0x0, 0x0, 220, 2433, -1, 0, 1, 59 }, - { 0x0, 0x0, 220, 2434, -1, 0, 1, 54 }, - { 0x1, 0x1, 220, 2435, -1, 12, 1, 59 }, - { 0x0, 0x0, 220, 2436, -1, 0, 1, 54 }, - { 0x1000001, 0x1000001, 220, 2437, -1, 12, 1, 59 }, - { 0x1, 0x1, 220, 2438, -1, 36, 1, 54 }, - { 0x200001, 0x200001, 220, 2439, -1, 12, 1, 59 }, - { 0x1, 0x1, 220, 2440, -1, 33, 1, 54 }, - { 0x1200001, 0x1200001, 220, 2441, -1, 12, 1, 49 }, - { 0x9, 0x9, 220, 2442, -1, 33, 1, 49 }, - { 0x0, 0x0, 220, 2443, -1, 0, 1, 59 }, - { 0x0, 0x0, 220, 2444, -1, 0, 1, 54 }, - { 0x0, 0x0, 220, 2445, -1, 0, 1, 59 }, - { 0x0, 0x0, 220, 2446, -1, 0, 1, 54 }, - { 0x0, 0x0, 220, 2447, -1, 0, 1, 59 }, - { 0x0, 0x0, 220, 2448, -1, 0, 1, 54 }, - { 0x0, 0x0, 220, 2449, -1, 0, 1, 49 }, - { 0x0, 0x0, 220, 2450, -1, 0, 1, 49 }, - { 0x1, 0x1, 220, 2451, -1, 12, 1, 59 }, - { 0x0, 0x0, 220, 2452, -1, 0, 1, 54 }, - { 0x200001, 0x1200001, 220, 2453, -1, 12, 1, 59 }, - { 0x1, 0x9, 220, 2454, -1, 33, 1, 54 }, - { 0x0, 0x0, 220, 2455, -1, 0, 1, 59 }, - { 0x0, 0x0, 220, 2456, -1, 0, 1, 54 }, - { 0x0, 0x0, 220, 2457, -1, 0, 1, 59 }, - { 0x0, 0x0, 220, 2458, -1, 0, 1, 54 }, - { 0x1, 0x1, 220, 2459, -1, 28, 1, 29 }, - { 0x0, 0x0, 220, 2460, -1, 0, 1, 29 }, - { 0x3, 0x3, 220, 2461, -1, 27, 1, 29 }, - { 0x1, 0x1, 220, 2462, -1, 27, 1, 29 }, - { 0x0, 0x0, 220, 2463, -1, 0, 1, 66 }, - { 0x0, 0x0, 220, 2464, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2465, -1, 0, 1, 29 }, - { 0x1, 0x1, 220, 2466, -1, 36, 1, 66 }, - { 0x1, 0x1, 220, 2467, -1, 37, 1, 29 }, - { 0x0, 0x0, 220, 2468, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2469, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2470, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2471, -1, 0, 1, 66 }, - { 0x0, 0x0, 220, 2472, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 37, -1, 0, 1, 29 }, - { 0x1, 0x1, 220, 2474, -1, 36, 1, 66 }, - { 0x1, 0x1, 220, 2475, -1, 37, 1, 29 }, - { 0x0, 0x0, 220, 2476, -1, 0, 1, 29 }, - { 0x1, 0x1, 220, 2477, -1, 36, 1, 66 }, - { 0x1, 0x1, 220, 2478, -1, 37, 1, 29 }, - { 0x0, 0x0, 220, 2479, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2480, -1, 0, 1, 66 }, - { 0x0, 0x0, 220, 2481, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 42, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2483, -1, 0, 1, 66 }, - { 0x0, 0x0, 220, 2484, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 43, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2486, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2487, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2488, -1, 0, 1, 49 }, - { 0x1, 0x1, 220, 2489, -1, 27, 1, 49 }, - { 0x1, 0x1, 220, 2490, -1, 28, 1, 49 }, - { 0x3, 0x3, 220, 2491, -1, 27, 1, 49 }, - { 0x1, 0x1, 220, 2492, -1, 29, 1, 49 }, - { 0x5, 0x5, 220, 2493, -1, 27, 1, 49 }, - { 0x3, 0x3, 220, 2494, -1, 28, 1, 49 }, - { 0x7, 0x7, 220, 2495, -1, 27, 1, 49 }, - { 0x0, 0x0, 220, 2496, -1, 0, 1, 49 }, - { 0x0, 0x0, 220, 2497, -1, 0, 1, 49 }, - { 0x0, 0x0, 220, 2498, -1, 0, 1, 49 }, - { 0x0, 0x0, 220, 2499, -1, 0, 1, 49 }, - { 0x1, 0x1, 220, 2500, -1, 28, 1, 29 }, - { 0x0, 0x0, 220, 2501, -1, 0, 1, 29 }, - { 0x3, 0x3, 220, 2502, -1, 27, 1, 29 }, - { 0x1, 0x1, 220, 2503, -1, 27, 1, 29 }, - { 0x0, 0x0, 220, 2504, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2505, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2506, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 52, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2508, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2509, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 57, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 2511, -1, 0, 1, 24 }, - { 0x0, 0x0, 220, 2512, -1, 0, 1, 24 }, - { 0x0, 0x0, 220, 2513, -1, 0, 1, 24 }, - { 0x0, 0x0, 220, 2514, -1, 0, 1, 24 }, - { 0x0, 0x0, 220, 2515, -1, 0, 1, 35 }, - { 0x0, 0x0, 220, 2516, -1, 0, 1, 66 }, - { 0x0, 0x0, 220, 2517, -1, 0, 1, 29 }, - { 0x0, 0x0, 220, 64, -1, 0, 1, 29 }, - { 0x1, 0x1, 221, 2519, -1, 34, 1, 66 }, - { 0x1, 0x1, 221, 2520, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2521, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2522, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2523, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2524, -1, 34, 1, 46 }, - { 0x1, 0x1, 221, 2525, -1, 34, 1, 42 }, - { 0x400001, 0x400001, 221, 2526, -1, 12, 1, 61 }, - { 0x1, 0x1, 221, 2527, -1, 34, 1, 56 }, - { 0x1400001, 0x1400001, 221, 2528, -1, 12, 1, 61 }, - { 0x5, 0x5, 221, 2529, -1, 34, 1, 56 }, - { 0x600001, 0x600001, 221, 2530, -1, 12, 1, 61 }, - { 0x3, 0x3, 221, 2531, -1, 33, 1, 56 }, - { 0x1600001, 0x1600001, 221, 2532, -1, 12, 1, 51 }, - { 0xb, 0xb, 221, 2533, -1, 33, 1, 51 }, - { 0x1, 0x1, 221, 2534, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2535, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2536, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2537, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2538, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2539, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2540, -1, 34, 1, 51 }, - { 0x1, 0x1, 221, 2541, -1, 34, 1, 51 }, - { 0x400001, 0x400001, 221, 2542, -1, 12, 1, 61 }, - { 0x1, 0x1, 221, 2543, -1, 34, 1, 56 }, - { 0x600001, 0x1600001, 221, 2544, -1, 12, 1, 61 }, - { 0x3, 0xb, 221, 2545, -1, 33, 1, 56 }, - { 0x1, 0x1, 221, 2546, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2547, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2548, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2549, -1, 34, 1, 56 }, - { 0x400001, 0x400001, 221, 2550, -1, 12, 1, 61 }, - { 0x1, 0x1, 221, 2551, -1, 34, 1, 56 }, - { 0x1400001, 0x1400001, 221, 2552, -1, 12, 1, 61 }, - { 0x5, 0x5, 221, 2553, -1, 34, 1, 56 }, - { 0x600001, 0x600001, 221, 2554, -1, 12, 1, 61 }, - { 0x3, 0x3, 221, 2555, -1, 33, 1, 56 }, - { 0x1600001, 0x1600001, 221, 2556, -1, 12, 1, 51 }, - { 0xb, 0xb, 221, 2557, -1, 33, 1, 51 }, - { 0x1, 0x1, 221, 2558, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2559, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2560, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2561, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2562, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2563, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2564, -1, 34, 1, 51 }, - { 0x1, 0x1, 221, 2565, -1, 34, 1, 51 }, - { 0x400001, 0x400001, 221, 2566, -1, 12, 1, 61 }, - { 0x1, 0x1, 221, 2567, -1, 34, 1, 56 }, - { 0x600001, 0x1600001, 221, 2568, -1, 12, 1, 61 }, - { 0x3, 0xb, 221, 2569, -1, 33, 1, 56 }, - { 0x1, 0x1, 221, 2570, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2571, -1, 34, 1, 56 }, - { 0x1, 0x1, 221, 2572, -1, 34, 1, 61 }, - { 0x1, 0x1, 221, 2573, -1, 34, 1, 56 }, - { 0x41, 0x41, 221, 2574, -1, 28, 1, 31 }, - { 0x1, 0x1, 221, 2575, -1, 34, 1, 31 }, - { 0x83, 0x83, 221, 2576, -1, 27, 1, 31 }, - { 0x81, 0x81, 221, 2577, -1, 27, 1, 31 }, - { 0x1, 0x1, 221, 2578, -1, 34, 1, 66 }, - { 0x1, 0x1, 221, 2579, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2580, -1, 34, 1, 31 }, - { 0x5, 0x5, 221, 2581, -1, 34, 1, 66 }, - { 0x9, 0x9, 221, 2582, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2583, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2584, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2585, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2586, -1, 34, 1, 66 }, - { 0x1, 0x1, 221, 2587, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2588, -1, 34, 1, 31 }, - { 0x5, 0x5, 221, 2589, -1, 34, 1, 66 }, - { 0x9, 0x9, 221, 2590, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2591, -1, 34, 1, 31 }, - { 0x5, 0x5, 221, 2592, -1, 34, 1, 66 }, - { 0x9, 0x9, 221, 2593, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2594, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2595, -1, 34, 1, 66 }, - { 0x1, 0x1, 221, 2596, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2597, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2598, -1, 34, 1, 66 }, - { 0x1, 0x1, 221, 2599, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2600, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2601, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2602, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2603, -1, 34, 1, 51 }, - { 0x81, 0x81, 221, 2604, -1, 27, 1, 51 }, - { 0x41, 0x41, 221, 2605, -1, 28, 1, 51 }, - { 0x83, 0x83, 221, 2606, -1, 27, 1, 51 }, - { 0x21, 0x21, 221, 2607, -1, 29, 1, 51 }, - { 0x85, 0x85, 221, 2608, -1, 27, 1, 51 }, - { 0x43, 0x43, 221, 2609, -1, 28, 1, 51 }, - { 0x87, 0x87, 221, 2610, -1, 27, 1, 51 }, - { 0x1, 0x1, 221, 2611, -1, 34, 1, 51 }, - { 0x1, 0x1, 221, 2612, -1, 34, 1, 51 }, - { 0x1, 0x1, 221, 2613, -1, 34, 1, 51 }, - { 0x1, 0x1, 221, 2614, -1, 34, 1, 51 }, - { 0x41, 0x41, 221, 2615, -1, 28, 1, 31 }, - { 0x1, 0x1, 221, 2616, -1, 34, 1, 31 }, - { 0x83, 0x83, 221, 2617, -1, 27, 1, 31 }, - { 0x81, 0x81, 221, 2618, -1, 27, 1, 31 }, - { 0x1, 0x1, 221, 2619, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2620, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2621, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2622, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2623, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2624, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2625, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2626, -1, 34, 1, 26 }, - { 0x1, 0x1, 221, 2627, -1, 34, 1, 26 }, - { 0x1, 0x1, 221, 2628, -1, 34, 1, 26 }, - { 0x1, 0x1, 221, 2629, -1, 34, 1, 26 }, - { 0x1, 0x1, 221, 2630, -1, 34, 1, 37 }, - { 0x1, 0x1, 221, 2631, -1, 34, 1, 66 }, - { 0x1, 0x1, 221, 2632, -1, 34, 1, 31 }, - { 0x1, 0x1, 221, 2633, -1, 34, 1, 31 }, - { 0x1, 0x1, 222, 2634, -1, 35, 1, 66 }, - { 0x1, 0x1, 222, 2635, -1, 35, 1, 32 }, - { 0x1, 0x1, 222, 2636, -1, 35, 1, 32 }, - { 0x1, 0x1, 222, 2637, -1, 35, 1, 32 }, - { 0x1, 0x1, 222, 2638, -1, 35, 1, 32 }, - { 0x1, 0x1, 222, 2639, -1, 35, 1, 47 }, - { 0x1, 0x1, 222, 2640, -1, 35, 1, 43 }, - { 0x800001, 0x800001, 222, 2641, -1, 12, 1, 62 }, - { 0x1, 0x1, 222, 2642, -1, 35, 1, 57 }, - { 0x1800001, 0x1800001, 222, 2643, -1, 12, 1, 62 }, - { 0x3, 0x3, 222, 2644, -1, 35, 1, 57 }, - { 0xa00001, 0xa00001, 222, 2645, -1, 12, 1, 62 }, - { 0x5, 0x5, 222, 2646, -1, 33, 1, 57 }, - { 0x1a00001, 0x1a00001, 222, 2647, -1, 12, 1, 52 }, - { 0xd, 0xd, 222, 2648, -1, 33, 1, 52 }, - { 0x1, 0x1, 222, 2649, -1, 35, 1, 62 }, - { 0x1, 0x1, 222, 2650, -1, 35, 1, 57 }, - { 0x1, 0x1, 222, 2651, -1, 35, 1, 62 }, - { 0x1, 0x1, 222, 2652, -1, 35, 1, 57 }, - { 0x1, 0x1, 222, 2653, -1, 35, 1, 62 }, - { 0x1, 0x1, 222, 2654, -1, 35, 1, 57 }, - { 0x1, 0x1, 222, 2655, -1, 35, 1, 52 }, - { 0x1, 0x1, 222, 2656, -1, 35, 1, 52 }, - { 0x800001, 0x800001, 222, 2657, -1, 12, 1, 62 }, - { 0x1, 0x1, 222, 2658, -1, 35, 1, 57 }, - { 0xa00001, 0x1a00001, 222, 2659, -1, 12, 1, 62 }, - { 0x5, 0xd, 222, 2660, -1, 33, 1, 57 }, - { 0x1, 0x1, 222, 2661, -1, 35, 1, 62 }, - { 0x1, 0x1, 222, 2662, -1, 35, 1, 57 }, - { 0x1, 0x1, 222, 2663, -1, 35, 1, 62 }, - { 0x1, 0x1, 222, 2664, -1, 35, 1, 57 }, - { 0x800001, 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0x0, 235, 2799, 674, 0, 1, 18 }, - { 0x0, 0x0, 235, 2800, 678, 0, 1, 18 }, - { 0x0, 0x0, 235, 2801, 999, 0, 0, -1 }, - { 0x0, 0x0, 235, 2802, 1003, 0, 0, -1 }, - { 0x0, 0x0, 235, 2803, 698, 0, 1, 19 }, - { 0x1, 0x1, 235, 2804, 702, 6, 1, 19 }, - { 0x0, 0x0, 235, 2805, 1007, 0, 0, -1 }, - { 0x0, 0x0, 235, 2806, 714, 0, 1, 20 }, - { 0x0, 0x0, 235, 2807, 1011, 0, 0, -1 }, - { 0x0, 0x0, 235, 2808, 1015, 0, 0, -1 }, - { 0x0, 0x0, 235, 2809, 734, 0, 1, 21 }, - { 0x1, 0x1, 235, 2810, 738, 6, 1, 21 }, - { 0x0, 0x0, 235, 2811, 1019, 0, 0, -1 }, - { 0x0, 0x0, 235, 2812, 750, 0, 1, 22 }, - { 0x0, 0x0, 235, 2813, 1024, 0, 0, -1 }, - { 0x0, 0x0, 235, 2814, 1028, 0, 0, -1 }, - { 0x0, 0x0, 235, 2815, 773, 0, 1, 18 }, - { 0x0, 0x0, 235, 2816, 777, 0, 1, 18 }, - { 0x0, 0x0, 235, 2817, 1032, 0, 0, -1 }, - { 0x0, 0x0, 235, 2818, 789, 0, 1, 22 }, - { 0x1, 0x1, 235, 915, 1155, 27, 1, 17 }, - { 0x0, 0x0, 235, 916, 1153, 0, 1, 17 }, - { 0x0, 0x0, 235, 1220, 1157, 0, 1, 23 }, - { 0x0, 0x1, 235, 1165, 1163, 20, 1, 68 }, - { 0x0, 0x0, 235, 111, 1161, 0, 1, 68 }, - { 0x1, 0x1, 238, -1, -1, 29, 1, 0 }, - { 0x0, 0x0, 238, -1, -1, 0, 1, 0 }, - { 0x1, 0x1, 238, 3022, -1, 27, 1, 0 }, - { 0x1, 0x1, 238, 3023, -1, 27, 1, 0 }, - { 0x1, 0x1, 238, 3024, -1, 27, 1, 0 }, - { 0x1, 0x1, 238, 3025, -1, 27, 1, 0 }, - { 0x0, 0x0, 261, -1, 2344, 0, 0, -1 }, - { 0x0, 0x0, 261, -1, 2346, 0, 0, -1 }, - { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, - { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, - { 0x0, 0x0, 261, -1, 2385, 0, 0, -1 }, - { 0x0, 0x0, 261, -1, 2387, 0, 0, -1 }, - { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, - { 0x1, 0x1, 261, -1, -1, 28, 1, 30 }, - { 0x0, 0x0, 263, 23, -1, 0, 1, 0 }, - { 0x0, 0x0, 263, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 263, -1, -1, 0, 1, 0 }, - { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, - { 0x0, 0x0, 263, 180, -1, 0, 1, 0 }, - { 0x0, 0x1, 263, -1, -1, 29, 1, 0 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 301, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 323, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 349, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 371, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 65 }, - { 0x0, 0x0, 264, -1, 2296, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2298, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2300, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2302, 0, 0, -1 }, - { 0x1, 0x1, 264, -1, 2304, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2306, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2308, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2310, 12, 1, 50 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 50 }, - { 0x0, 0x0, 264, -1, 2312, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2314, 0, 0, -1 }, - { 0x1, 0x1, 264, -1, 2316, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2318, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x0, 0x0, 264, -1, 2320, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2322, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2324, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2326, 0, 0, -1 }, - { 0x1, 0x1, 264, -1, 2328, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2330, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2332, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2334, 12, 1, 50 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 50 }, - { 0x0, 0x0, 264, -1, 2336, 0, 0, -1 }, - { 0x0, 0x0, 264, -1, 2338, 0, 0, -1 }, - { 0x1, 0x1, 264, -1, 2340, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, 2342, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 264, 393, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 395, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 517, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 519, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 401, -1, 12, 1, 77 }, - { 0x1, 0x1, 264, 403, -1, 12, 1, 77 }, - { 0x1, 0x1, 264, 525, -1, 12, 1, 77 }, - { 0x1, 0x1, 264, 527, -1, 12, 1, 77 }, - { 0x1, 0x1, 264, 409, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 411, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 533, -1, 12, 1, 2 }, - { 0x1, 0x1, 264, 535, -1, 12, 1, 2 }, - { 0x0, 0x0, 265, -1, 2303, 0, 0, -1 }, - { 0x9, 0x9, 265, -1, 2311, 33, 1, 50 }, - { 0x9, 0x9, 265, -1, 2975, 33, 1, 50 }, - { 0x0, 0x0, 265, 1399, 2376, 0, 0, -1 }, - { 0x3, 0x3, 265, 1400, -1, 27, 1, 50 }, - { 0x0, 0x0, 269, 2856, -1, 0, 1, 0 }, - { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 270, -1, -1, 27, 1, 0 }, - { 0x1, 0x1, 271, 3018, -1, 28, 1, 0 }, - { 0x1, 0x1, 271, 3019, -1, 28, 1, 0 }, - { 0x1, 0x1, 271, 3020, -1, 28, 1, 0 }, - { 0x1, 0x1, 271, 3021, -1, 28, 1, 0 }, - { 0x1, 0x1, 273, -1, -1, 27, 1, 100 }, - { 0x1, 0x1, 273, -1, -1, 27, 1, 100 }, - { 0x0, 0x0, 273, -1, 968, 0, 0, -1 }, - { 0x0, 0x0, 274, 3031, 2833, 0, 0, -1 }, - { 0x0, 0x0, 274, 3032, 2835, 0, 0, -1 }, - { 0x0, 0x0, 275, -1, 2834, 0, 0, -1 }, - { 0x0, 0x0, 275, -1, 2836, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 276, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 281, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 285, -1, 2350, 0, 1, 30 }, - { 0x0, 0x0, 286, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 286, -1, -1, 0, 1, 72 }, - { 0x0, 0x0, 286, 2001, 3000, 0, 1, 1 }, - { 0x0, 0x0, 286, 2002, 3001, 0, 1, 1 }, - { 0x0, 0x0, 286, -1, 518, 0, 0, -1 }, - { 0x0, 0x0, 286, -1, 520, 0, 0, -1 }, - { 0x0, 0x0, 286, 2005, 3004, 0, 1, 76 }, - { 0x0, 0x0, 286, 2006, 3005, 0, 1, 76 }, - { 0x0, 0x0, 286, -1, 526, 0, 0, -1 }, - { 0x0, 0x0, 286, -1, 528, 0, 0, -1 }, - { 0x0, 0x0, 286, 2009, 3008, 0, 1, 1 }, - { 0x0, 0x0, 286, 2010, 3009, 0, 1, 1 }, - { 0x0, 0x0, 286, -1, 534, 0, 0, -1 }, - { 0x0, 0x0, 286, -1, 536, 0, 0, -1 }, -}; - -static const struct ia64_main_table -main_table[] = { - { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 0, }, - { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 1, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 67, 27, 0, 0 }, 0x0, 2, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 64, 26, 0, 0 }, 0x0, 3, }, - { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 24, 67, 27, 0, 0 }, 0x0, 4, }, - { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 5, }, - { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 24, 64, 26, 0, 0 }, 0x0, 6, }, - { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 24, 64, 26, 0, 0 }, 0x0, 7, }, - { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 3, 53, 54, 55 }, 0x221, 8, }, - { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 53, 54, 55, 0 }, 0x261, 9, }, - { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 10, }, - { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 11, }, - { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 12, }, - { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 13, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 16, 0, 0, 0, 0 }, 0x40, 969, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x0, 825, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x40, 826, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x200, 2234, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x240, 2235, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x0, 582, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x40, 583, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 82, 0, 0, 0, 0 }, 0x40, 990, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x0, 827, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x40, 828, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x210, 3029, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x250, 3030, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x30, 590, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x70, 591, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x230, 588, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x270, 589, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x0, 584, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x40, 585, }, - { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 537, }, - { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 960, }, - { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 66, 0, 0, 0, 0 }, 0x2, 1138, }, - { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 66, 0, 0, 0, 0 }, 0x0, 1263, }, - { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 70, 0, 0, 0, 0 }, 0x0, 3033, }, - { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 66, 0, 0, 0, 0 }, 0x0, 16, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 83, 0, 0, 0, 0 }, 0x40, 1023, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 83, 0, 0, 0, 0 }, 0x0, 829, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 83, 0, 0, 0, 0 }, 0x40, 830, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 83, 0, 0, 0 }, 0x0, 586, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 83, 0, 0, 0 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0x000001ee00002000ull, { 24, 26, 77, 0, 0 }, 0x140, 2878, }, - { 230, 2, 1, 0x000000f220000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 181, }, - { 231, 2, 1, 0x000000ac00000000ull, 0x000001ee00000000ull, { 24, 25, 26, 44, 0 }, 0x0, 182, }, - { 236, 3, 0, 0x0000000180000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 850, }, - { 237, 3, 0, 0x0000000030000000ull, 0x000001ee78000000ull, { 68, 0, 0, 0, 0 }, 0x8, 183, }, - { 239, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 184, }, - { 239, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 185, }, - { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 28, 25, 1, 0, 0 }, 0x0, 186, }, - { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x40, 187, }, - { 241, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 188, }, - { 241, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 189, }, - { 242, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 190, }, - { 242, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 191, }, - { 243, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 28, 25, 0, 0, 0 }, 0x0, 192, }, - { 243, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 28, 25, 62, 0, 0 }, 0x400, 193, }, - { 244, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 2785, }, - { 244, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 2786, }, - { 245, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 194, }, - { 245, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 195, }, - { 246, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 196, }, - { 246, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 197, }, - { 247, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 198, }, - { 247, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 199, }, - { 248, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 28, 19, 0, 0, 0 }, 0x0, 200, }, - { 248, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 28, 19, 62, 0, 0 }, 0x400, 201, }, - { 249, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 202, }, - { 249, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 203, }, - { 249, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 204, }, - { 250, 3, 0, 0x0000000020000000ull, 0x000001ee78000000ull, { 68, 0, 0, 0, 0 }, 0x0, 205, }, - { 251, 2, 1, 0x00000000a0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 206, }, - { 252, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 207, }, - { 253, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 208, }, - { 254, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 1150, }, - { 255, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 209, }, - { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 23, 26, 77, 0 }, 0x0, 3040, }, - { 256, 2, 1, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 26, 77, 0, 0 }, 0x40, 3041, }, - { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 22, 26, 77, 0 }, 0x40, 2003, }, - { 256, 2, 1, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 26, 77, 0, 0 }, 0x40, 2004, }, - { 257, 2, 2, 0x000000a000082000ull, 0x000001fe00083000ull, { 22, 23, 50, 0, 0 }, 0x0, 3044, }, - { 257, 2, 1, 0x000000a000082000ull, 0x000001fe00083000ull, { 22, 50, 0, 0, 0 }, 0x40, 3045, }, - { 257, 2, 2, 0x000000a000082000ull, 0x000001fe00083000ull, { 23, 22, 50, 0, 0 }, 0x40, 2007, }, - { 257, 2, 1, 0x000000a000082000ull, 0x000001fe00083000ull, { 23, 50, 0, 0, 0 }, 0x40, 2008, }, - { 258, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 210, }, - { 259, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 23, 26, 0, 0 }, 0x0, 3048, }, - { 259, 2, 1, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 26, 0, 0, 0 }, 0x40, 3049, }, - { 259, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 22, 26, 0, 0 }, 0x40, 2011, }, - { 259, 2, 1, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 26, 0, 0, 0 }, 0x40, 2012, }, - { 260, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 211, }, - { 262, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 212, }, - { 266, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1131, }, - { 267, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1132, }, - { 268, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1133, }, - { 272, 4, 0, 0x00000000c0000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x28, 223, }, - { 277, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 213, }, - { 278, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 214, }, - { 279, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 215, }, - { 280, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 28, 25, 0, 0 }, 0x0, 216, }, - { 282, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x0, 1179, }, - { 282, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x40, 1261, }, - { 283, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 18, 20, 21, 0, 0 }, 0x40, 1180, }, - { 284, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 217, }, - { 284, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 24, 56, 26, 0, 0 }, 0x0, 218, }, - { 287, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 219, }, - { 288, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 220, }, - { 289, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 221, }, -}; - -static const char dis_table[] = { -0xa0, 0xc7, 0xc8, 0xa0, 0x2e, 0xd8, 0xa0, 0x2c, 0xc0, 0xa0, 0x1c, 0x00, -0x98, 0xb0, 0x02, 0x50, 0x90, 0x50, 0x90, 0x28, 0x24, 0x39, 0x28, 0x24, -0x39, 0x20, 0x90, 0x28, 0x24, 0x39, 0x18, 0x24, 0x39, 0x10, 0x91, 0x60, -0x90, 0x28, 0x24, 0x39, 0x00, 0x10, 0x10, 0x58, 0x41, 0x61, 0xc7, 0xc0, -0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, -0x10, 0x10, 0x52, 0xc0, 0xc0, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, -0x10, 0x10, 0x10, 0x24, 0x24, 0x70, 0x90, 0x28, 0x24, 0x38, 0xf0, 0x24, -0x38, 0xe8, 0xa8, 0x0b, 0x48, 0x15, 0x20, 0x97, 0x20, 0x95, 0xc8, 0x9a, -0xb8, 0x05, 0x38, 0x91, 0x18, 0x90, 0xa0, 0x90, 0x60, 0x80, 0x90, 0x20, -0x34, 0xa6, 0xa4, 0x25, 0x00, 0x34, 0xa3, 0x80, 0xa4, 0x36, 0xa0, 0x36, -0xd9, 0x90, 0x50, 0x90, 0x28, 0x80, 0x36, 0xcf, 0x80, 0x34, 0x86, 0x81, -0x33, 0xe2, 0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x24, 0x10, 0x34, -0x83, 0xa4, 0x1f, 0x08, 0x34, 0x80, 0x90, 0x38, 0xa4, 0x38, 0xa0, 0x37, -0x1a, 0xa4, 0x38, 0x48, 0x37, 0x0e, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x37, -0x20, 0x36, 0xef, 0xa4, 0x36, 0xf8, 0x36, 0xea, 0x80, 0xa4, 0x23, 0xf0, -0x34, 0x7f, 0x92, 0x18, 0x91, 0xc0, 0x80, 0x91, 0x80, 0x90, 0xf8, 0xdb, -0x84, 0x60, 0xf9, 0x40, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x68, 0x8c, 0x43, -0xc8, 0x84, 0x38, 0x83, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x58, 0x8c, 0x43, -0xa8, 0x84, 0x38, 0x81, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, -0x35, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x33, 0xa4, 0x1f, 0x18, 0x33, 0xe4, -0x80, 0x90, 0x28, 0x80, 0x33, 0xe0, 0x80, 0x34, 0x88, 0x81, 0x90, 0x38, -0xa4, 0x24, 0x80, 0x34, 0x8b, 0xa4, 0x24, 0x48, 0x34, 0x85, 0xc0, 0x40, -0x10, 0x10, 0x90, 0x38, 0xa4, 0x1e, 0xf0, 0x33, 0xdf, 0xa4, 0x1e, 0xe0, -0x33, 0xdd, 0x18, 0x24, 0x24, 0xf8, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, -0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x38, 0x38, 0x6d, 0xc0, 0xc0, 0x80, 0xa4, -0x42, 0x28, 0x38, 0x69, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, -0x2f, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x2d, 0x92, 0xb8, 0x99, 0x84, 0x24, -0x68, 0x90, 0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x36, 0x98, 0x36, -0xd8, 0x82, 0x36, 0xce, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x38, -0x98, 0x37, 0x19, 0xa4, 0x38, 0x40, 0x37, 0x0d, 0x80, 0x90, 0x38, 0xa4, -0x37, 0x18, 0x36, 0xee, 0xa4, 0x36, 0xf0, 0x36, 0xe9, 0x83, 0x90, 0xa8, -0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x08, 0x38, 0x61, 0xc0, -0xc0, 0x80, 0xa4, 0x41, 0xf8, 0x38, 0x5d, 0xd3, 0x82, 0x40, 0x50, 0xc0, -0xc0, 0x81, 0x38, 0x29, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x27, 0x18, 0x24, -0x24, 0x78, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, -0x41, 0xd8, 0x38, 0x55, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0xc8, 0x38, 0x51, -0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x23, 0x50, 0xc0, 0xc0, -0x81, 0x38, 0x21, 0x94, 0x50, 0x92, 0xf8, 0x99, 0x84, 0x1f, 0x48, 0x90, -0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x36, 0x90, 0x36, 0xd7, 0x82, -0x36, 0xcd, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, 0xa4, 0x38, 0x90, 0x37, -0x18, 0xa4, 0x38, 0x38, 0x37, 0x0c, 0x80, 0x90, 0x38, 0xa4, 0x37, 0x10, -0x36, 0xed, 0xa4, 0x36, 0xe8, 0x36, 0xe8, 0x83, 0x90, 0xe8, 0xd3, 0x83, -0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x78, 0x8c, 0x43, 0xe8, 0x84, 0x38, -0x85, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x60, 0x8c, 0x43, 0xb8, 0x84, 0x38, -0x82, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x37, 0x50, 0xc0, -0xc0, 0x81, 0x38, 0x34, 0x18, 0x24, 0x1f, 0x40, 0x83, 0x90, 0xa8, 0xd3, -0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x48, 0x38, 0x71, 0xc0, 0xc0, -0x80, 0xa4, 0x42, 0x30, 0x38, 0x6b, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, -0x81, 0x38, 0x31, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x2e, 0x92, 0xb8, 0x99, -0x84, 0x1f, 0x38, 0x90, 0x78, 0x90, 0x50, 0x10, 0x10, 0x80, 0xa4, 0x36, -0x88, 0x36, 0xd6, 0x82, 0x36, 0xcc, 0x90, 0x80, 0x10, 0x10, 0x90, 0x38, -0xa4, 0x38, 0x88, 0x37, 0x17, 0xa4, 0x38, 0x30, 0x37, 0x0b, 0x80, 0x90, -0x38, 0xa4, 0x37, 0x08, 0x36, 0xec, 0xa4, 0x36, 0xe0, 0x36, 0xe7, 0x83, -0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x18, 0x38, -0x65, 0xc0, 0xc0, 0x80, 0xa4, 0x42, 0x00, 0x38, 0x5f, 0xd3, 0x82, 0x40, -0x50, 0xc0, 0xc0, 0x81, 0x38, 0x2b, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x28, -0x18, 0x20, 0x01, 0x48, 0x83, 0x90, 0xa8, 0xd3, 0x82, 0xc0, 0xc0, 0xc0, -0x80, 0xa4, 0x41, 0xe8, 0x38, 0x59, 0xc0, 0xc0, 0x80, 0xa4, 0x41, 0xd0, -0x38, 0x53, 0xd3, 0x82, 0x40, 0x50, 0xc0, 0xc0, 0x81, 0x38, 0x25, 0x50, -0xc0, 0xc0, 0x81, 0x38, 0x22, 0xda, 0x06, 0xe0, 0xf9, 0x80, 0x90, 0x60, -0x90, 0x38, 0xa4, 0x24, 0xe8, 0x34, 0x9b, 0x80, 0x34, 0x98, 0x90, 0x38, -0xa4, 0x24, 0x90, 0x34, 0x96, 0x80, 0x34, 0x93, 0x90, 0x60, 0x90, 0x38, -0xa4, 0x24, 0xd0, 0x34, 0x9c, 0x80, 0x34, 0x99, 0x90, 0x38, 0xa4, 0x24, -0xa8, 0x34, 0x97, 0x80, 0x34, 0x94, 0xc8, 0x40, 0x19, 0x00, 0x91, 0x58, -0x90, 0x60, 0x82, 0x90, 0x20, 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0x28, 0xc0, 0x81, 0x30, 0x0e, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, -0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x86, 0xc0, 0x3a, 0x13, -0xe5, 0x22, 0x88, 0xc0, 0x3a, 0x37, 0xcb, 0x61, 0x2f, 0xc0, 0x85, 0x34, -0xce, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x76, 0xc0, 0x39, 0xd3, 0xe5, -0x22, 0x78, 0xc0, 0x39, 0xf7, 0xcb, 0x61, 0x2f, 0x80, 0x85, 0x34, 0xcd, -0x90, 0x48, 0xcb, 0xa1, 0x2f, 0x40, 0x85, 0x34, 0xcc, 0xcb, 0xa1, 0x2f, -0x00, 0x85, 0x34, 0xcb, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, -0xe5, 0x22, 0x68, 0xc0, 0x39, 0xbb, 0xe5, 0x22, 0x5c, 0xc0, 0x39, 0x8b, -0xcb, 0x61, 0x2d, 0x40, 0x85, 0x34, 0xba, 0x98, 0x50, 0x00, 0x80, 0xe5, -0x22, 0x50, 0xc0, 0x39, 0x5b, 0xe5, 0x22, 0x44, 0xc0, 0x39, 0x2b, 0xcb, -0x61, 0x2d, 0x00, 0x85, 0x34, 0xb9, 0x90, 0x48, 0xcb, 0xa1, 0x2c, 0xc0, -0x85, 0x34, 0xb8, 0xcb, 0xa1, 0x2c, 0x80, 0x85, 0x34, 0xb7, 0x91, 0x00, -0x90, 0x80, 0x90, 0x40, 0xe5, 0x20, 0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, -0x01, 0x80, 0x30, 0x07, 0x90, 0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, -0xe5, 0x20, 0x00, 0x00, 0x30, 0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, -0x35, 0xc0, 0x38, 0xcd, 0xe5, 0x22, 0x38, 0x00, 0x38, 0xf5, 0x90, 0x40, -0xe5, 0x22, 0x24, 0x40, 0x38, 0x87, 0xe5, 0x22, 0x26, 0x80, 0x38, 0xaf, -0x80, 0x99, 0x28, 0x02, 0xf0, 0x8c, 0x25, 0x48, 0x90, 0x80, 0x90, 0x40, -0xe5, 0x22, 0x8c, 0xc0, 0x3a, 0x2f, 0xe5, 0x22, 0x89, 0xc0, 0x3a, 0x3b, -0x90, 0x40, 0xe5, 0x22, 0x7c, 0xc0, 0x39, 0xef, 0xe5, 0x22, 0x79, 0xc0, -0x39, 0xfb, 0x91, 0x48, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, -0x6a, 0xc0, 0x39, 0xc3, 0xe5, 0x22, 0x5e, 0xc0, 0x39, 0x93, 0xcb, 0x61, -0x2b, 0x00, 0x85, 0x34, 0xb0, 0x90, 0x40, 0xe5, 0x22, 0x52, 0xc0, 0x39, -0x63, 0xe5, 0x22, 0x46, 0xc0, 0x39, 0x33, 0x90, 0x48, 0xcb, 0xa1, 0x2a, -0x80, 0x85, 0x34, 0xae, 0xcb, 0xa1, 0x2a, 0xc0, 0x85, 0x34, 0xaf, 0x10, -0x10, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0x3c, 0x40, 0x38, 0xed, 0xe5, -0x22, 0x39, 0x40, 0x38, 0xfb, 0x90, 0x40, 0xe5, 0x22, 0x2a, 0xc0, 0x38, -0xa7, 0xe5, 0x22, 0x27, 0xc0, 0x38, 0xb5, -}; - -static const struct ia64_dis_names ia64_dis_names[] = { -{ 0x51, 41, 0, 10 }, -{ 0x31, 41, 1, 20 }, -{ 0x11, 42, 0, 19 }, -{ 0x29, 41, 0, 12 }, -{ 0x19, 41, 1, 24 }, -{ 0x9, 42, 0, 23 }, -{ 0x15, 41, 0, 14 }, -{ 0xd, 41, 1, 28 }, -{ 0x5, 42, 0, 27 }, -{ 0xb, 41, 0, 16 }, -{ 0x7, 41, 1, 32 }, -{ 0x3, 42, 0, 31 }, -{ 0x51, 39, 1, 58 }, -{ 0x50, 39, 0, 34 }, -{ 0xd1, 39, 1, 57 }, -{ 0xd0, 39, 0, 33 }, -{ 0x31, 39, 1, 68 }, -{ 0x30, 39, 1, 44 }, -{ 0x11, 40, 1, 67 }, -{ 0x10, 40, 0, 43 }, -{ 0x71, 39, 1, 66 }, -{ 0x70, 39, 1, 42 }, -{ 0x31, 40, 1, 65 }, -{ 0x30, 40, 0, 41 }, -{ 0x29, 39, 1, 60 }, -{ 0x28, 39, 0, 36 }, -{ 0x69, 39, 1, 59 }, -{ 0x68, 39, 0, 35 }, -{ 0x19, 39, 1, 72 }, -{ 0x18, 39, 1, 48 }, -{ 0x9, 40, 1, 71 }, -{ 0x8, 40, 0, 47 }, -{ 0x39, 39, 1, 70 }, -{ 0x38, 39, 1, 46 }, -{ 0x19, 40, 1, 69 }, -{ 0x18, 40, 0, 45 }, -{ 0x15, 39, 1, 62 }, -{ 0x14, 39, 0, 38 }, -{ 0x35, 39, 1, 61 }, -{ 0x34, 39, 0, 37 }, -{ 0xd, 39, 1, 76 }, -{ 0xc, 39, 1, 52 }, -{ 0x5, 40, 1, 75 }, -{ 0x4, 40, 0, 51 }, -{ 0x1d, 39, 1, 74 }, -{ 0x1c, 39, 1, 50 }, -{ 0xd, 40, 1, 73 }, -{ 0xc, 40, 0, 49 }, -{ 0xb, 39, 1, 64 }, -{ 0xa, 39, 0, 40 }, -{ 0x1b, 39, 1, 63 }, -{ 0x1a, 39, 0, 39 }, -{ 0x7, 39, 1, 80 }, -{ 0x6, 39, 1, 56 }, -{ 0x3, 40, 1, 79 }, -{ 0x2, 40, 0, 55 }, -{ 0xf, 39, 1, 78 }, -{ 0xe, 39, 1, 54 }, -{ 0x7, 40, 1, 77 }, -{ 0x6, 40, 0, 53 }, -{ 0x8, 38, 0, 82 }, -{ 0x18, 38, 0, 81 }, -{ 0x1, 38, 1, 86 }, -{ 0x2, 38, 0, 85 }, -{ 0x3, 38, 1, 84 }, -{ 0x4, 38, 0, 83 }, -{ 0x1, 336, 0, 87 }, -{ 0x20, 289, 0, 98 }, -{ 0x220, 289, 0, 94 }, -{ 0x1220, 289, 0, 91 }, -{ 0xa20, 289, 0, 92 }, -{ 0x620, 289, 0, 93 }, -{ 0x120, 289, 0, 95 }, -{ 0xa0, 289, 0, 96 }, -{ 0x60, 289, 0, 97 }, -{ 0x10, 289, 0, 102 }, -{ 0x90, 289, 0, 99 }, -{ 0x50, 289, 0, 100 }, -{ 0x30, 289, 0, 101 }, -{ 0x8, 289, 0, 103 }, -{ 0x4, 289, 0, 104 }, -{ 0x2, 289, 0, 105 }, -{ 0x1, 289, 0, 106 }, -{ 0x1, 411, 0, 108 }, -{ 0x3, 411, 0, 107 }, -{ 0x2, 417, 0, 109 }, -{ 0x1, 417, 0, 110 }, -{ 0x2, 413, 0, 111 }, -{ 0x1, 413, 0, 112 }, -{ 0x2, 415, 0, 113 }, -{ 0x1, 415, 0, 114 }, -{ 0x2, 419, 0, 115 }, -{ 0x1, 419, 0, 116 }, -{ 0x1, 268, 0, 143 }, -{ 0x5, 268, 0, 141 }, -{ 0x3, 268, 0, 142 }, -{ 0x140, 277, 0, 119 }, -{ 0x540, 277, 0, 117 }, -{ 0x340, 277, 0, 118 }, -{ 0xc0, 277, 0, 131 }, -{ 0x2c0, 277, 0, 129 }, -{ 0x1c0, 277, 0, 130 }, -{ 0x20, 277, 0, 146 }, -{ 0xa0, 277, 0, 144 }, -{ 0x60, 277, 0, 145 }, -{ 0x10, 277, 0, 158 }, -{ 0x50, 277, 0, 156 }, -{ 0x30, 277, 0, 157 }, -{ 0x8, 277, 0, 170 }, -{ 0x28, 277, 0, 168 }, -{ 0x18, 277, 0, 169 }, -{ 0x4, 277, 0, 180 }, -{ 0x2, 277, 0, 181 }, -{ 0x1, 277, 0, 182 }, -{ 0x140, 271, 0, 122 }, -{ 0x540, 271, 0, 120 }, -{ 0x340, 271, 0, 121 }, -{ 0xc0, 271, 0, 134 }, -{ 0x2c0, 271, 0, 132 }, -{ 0x1c0, 271, 0, 133 }, -{ 0x20, 271, 0, 149 }, -{ 0xa0, 271, 0, 147 }, -{ 0x60, 271, 0, 148 }, -{ 0x10, 271, 0, 161 }, -{ 0x50, 271, 0, 159 }, -{ 0x30, 271, 0, 160 }, -{ 0x8, 271, 0, 173 }, -{ 0x28, 271, 0, 171 }, -{ 0x18, 271, 0, 172 }, -{ 0x4, 271, 0, 183 }, -{ 0x2, 271, 0, 184 }, -{ 0x1, 271, 0, 185 }, -{ 0x140, 274, 0, 125 }, -{ 0x540, 274, 0, 123 }, -{ 0x340, 274, 0, 124 }, -{ 0xc0, 274, 0, 137 }, -{ 0x2c0, 274, 0, 135 }, -{ 0x1c0, 274, 0, 136 }, -{ 0x20, 274, 0, 152 }, -{ 0xa0, 274, 0, 150 }, -{ 0x60, 274, 0, 151 }, -{ 0x10, 274, 0, 164 }, -{ 0x50, 274, 0, 162 }, -{ 0x30, 274, 0, 163 }, -{ 0x8, 274, 0, 176 }, -{ 0x28, 274, 0, 174 }, -{ 0x18, 274, 0, 175 }, -{ 0x4, 274, 0, 186 }, -{ 0x2, 274, 0, 187 }, -{ 0x1, 274, 0, 188 }, -{ 0x140, 286, 0, 128 }, -{ 0x540, 286, 0, 126 }, -{ 0x340, 286, 0, 127 }, -{ 0xc0, 286, 0, 140 }, -{ 0x2c0, 286, 0, 138 }, -{ 0x1c0, 286, 0, 139 }, -{ 0x20, 286, 0, 155 }, -{ 0xa0, 286, 0, 153 }, -{ 0x60, 286, 0, 154 }, -{ 0x10, 286, 0, 167 }, -{ 0x50, 286, 0, 165 }, -{ 0x30, 286, 0, 166 }, -{ 0x8, 286, 0, 179 }, -{ 0x28, 286, 0, 177 }, -{ 0x18, 286, 0, 178 }, -{ 0x4, 286, 0, 189 }, -{ 0x2, 286, 0, 190 }, -{ 0x1, 286, 0, 191 }, -{ 0x8, 390, 0, 192 }, -{ 0x4, 390, 0, 193 }, -{ 0x2, 390, 0, 194 }, -{ 0x1, 390, 0, 195 }, -{ 0x20, 288, 0, 203 }, -{ 0x220, 288, 0, 199 }, -{ 0x1220, 288, 0, 196 }, -{ 0xa20, 288, 0, 197 }, -{ 0x620, 288, 0, 198 }, -{ 0x120, 288, 0, 200 }, -{ 0xa0, 288, 0, 201 }, -{ 0x60, 288, 0, 202 }, -{ 0x10, 288, 0, 207 }, -{ 0x90, 288, 0, 204 }, -{ 0x50, 288, 0, 205 }, -{ 0x30, 288, 0, 206 }, -{ 0x8, 288, 0, 208 }, -{ 0x4, 288, 0, 209 }, -{ 0x2, 288, 0, 210 }, -{ 0x1, 288, 0, 211 }, -{ 0x20, 287, 0, 219 }, -{ 0x220, 287, 0, 215 }, -{ 0x1220, 287, 0, 212 }, -{ 0xa20, 287, 0, 213 }, -{ 0x620, 287, 0, 214 }, -{ 0x120, 287, 0, 216 }, -{ 0xa0, 287, 0, 217 }, -{ 0x60, 287, 0, 218 }, -{ 0x10, 287, 0, 223 }, -{ 0x90, 287, 0, 220 }, -{ 0x50, 287, 0, 221 }, -{ 0x30, 287, 0, 222 }, -{ 0x8, 287, 0, 224 }, -{ 0x4, 287, 0, 225 }, -{ 0x2, 287, 0, 226 }, -{ 0x1, 287, 0, 227 }, -{ 0x140, 279, 0, 230 }, -{ 0x540, 279, 0, 228 }, -{ 0x340, 279, 0, 229 }, -{ 0xc0, 279, 0, 239 }, -{ 0x2c0, 279, 0, 237 }, -{ 0x1c0, 279, 0, 238 }, -{ 0x20, 279, 0, 248 }, -{ 0xa0, 279, 0, 246 }, -{ 0x60, 279, 0, 247 }, -{ 0x10, 279, 0, 257 }, -{ 0x50, 279, 0, 255 }, -{ 0x30, 279, 0, 256 }, -{ 0x8, 279, 0, 266 }, -{ 0x28, 279, 0, 264 }, -{ 0x18, 279, 0, 265 }, -{ 0x4, 279, 0, 273 }, -{ 0x2, 279, 0, 274 }, -{ 0x1, 279, 0, 275 }, -{ 0x140, 281, 0, 233 }, -{ 0x540, 281, 0, 231 }, -{ 0x340, 281, 0, 232 }, -{ 0xc0, 281, 0, 242 }, -{ 0x2c0, 281, 0, 240 }, -{ 0x1c0, 281, 0, 241 }, -{ 0x20, 281, 0, 251 }, -{ 0xa0, 281, 0, 249 }, -{ 0x60, 281, 0, 250 }, -{ 0x10, 281, 0, 260 }, -{ 0x50, 281, 0, 258 }, -{ 0x30, 281, 0, 259 }, -{ 0x8, 281, 0, 269 }, -{ 0x28, 281, 0, 267 }, -{ 0x18, 281, 0, 268 }, -{ 0x4, 281, 0, 276 }, -{ 0x2, 281, 0, 277 }, -{ 0x1, 281, 0, 278 }, -{ 0x140, 283, 0, 236 }, -{ 0x540, 283, 0, 234 }, -{ 0x340, 283, 0, 235 }, -{ 0xc0, 283, 0, 245 }, -{ 0x2c0, 283, 0, 243 }, -{ 0x1c0, 283, 0, 244 }, -{ 0x20, 283, 0, 254 }, -{ 0xa0, 283, 0, 252 }, -{ 0x60, 283, 0, 253 }, -{ 0x10, 283, 0, 263 }, -{ 0x50, 283, 0, 261 }, -{ 0x30, 283, 0, 262 }, -{ 0x8, 283, 0, 272 }, -{ 0x28, 283, 0, 270 }, -{ 0x18, 283, 0, 271 }, -{ 0x4, 283, 0, 279 }, -{ 0x2, 283, 0, 280 }, -{ 0x1, 283, 0, 281 }, -{ 0x140, 278, 0, 284 }, -{ 0x540, 278, 0, 282 }, -{ 0x340, 278, 0, 283 }, -{ 0xc0, 278, 0, 293 }, -{ 0x2c0, 278, 0, 291 }, -{ 0x1c0, 278, 0, 292 }, -{ 0x20, 278, 0, 302 }, -{ 0xa0, 278, 0, 300 }, -{ 0x60, 278, 0, 301 }, -{ 0x10, 278, 0, 311 }, -{ 0x50, 278, 0, 309 }, -{ 0x30, 278, 0, 310 }, -{ 0x8, 278, 0, 320 }, -{ 0x28, 278, 0, 318 }, -{ 0x18, 278, 0, 319 }, -{ 0x4, 278, 0, 327 }, -{ 0x2, 278, 0, 328 }, -{ 0x1, 278, 0, 329 }, -{ 0x140, 280, 0, 287 }, -{ 0x540, 280, 0, 285 }, -{ 0x340, 280, 0, 286 }, -{ 0xc0, 280, 0, 296 }, -{ 0x2c0, 280, 0, 294 }, -{ 0x1c0, 280, 0, 295 }, -{ 0x20, 280, 0, 305 }, -{ 0xa0, 280, 0, 303 }, -{ 0x60, 280, 0, 304 }, -{ 0x10, 280, 0, 314 }, -{ 0x50, 280, 0, 312 }, -{ 0x30, 280, 0, 313 }, -{ 0x8, 280, 0, 323 }, -{ 0x28, 280, 0, 321 }, -{ 0x18, 280, 0, 322 }, -{ 0x4, 280, 0, 330 }, -{ 0x2, 280, 0, 331 }, -{ 0x1, 280, 0, 332 }, -{ 0x140, 282, 0, 290 }, -{ 0x540, 282, 0, 288 }, -{ 0x340, 282, 0, 289 }, -{ 0xc0, 282, 0, 299 }, -{ 0x2c0, 282, 0, 297 }, -{ 0x1c0, 282, 0, 298 }, -{ 0x20, 282, 0, 308 }, -{ 0xa0, 282, 0, 306 }, -{ 0x60, 282, 0, 307 }, -{ 0x10, 282, 0, 317 }, -{ 0x50, 282, 0, 315 }, -{ 0x30, 282, 0, 316 }, -{ 0x8, 282, 0, 326 }, -{ 0x28, 282, 0, 324 }, -{ 0x18, 282, 0, 325 }, -{ 0x4, 282, 0, 333 }, -{ 0x2, 282, 0, 334 }, -{ 0x1, 282, 0, 335 }, -{ 0x1, 410, 0, 337 }, -{ 0x3, 410, 0, 336 }, -{ 0x2, 416, 0, 338 }, -{ 0x1, 416, 0, 339 }, -{ 0x2, 412, 0, 340 }, -{ 0x1, 412, 0, 341 }, -{ 0x2, 414, 0, 342 }, -{ 0x1, 414, 0, 343 }, -{ 0x2, 418, 0, 344 }, -{ 0x1, 418, 0, 345 }, -{ 0x1, 267, 0, 372 }, -{ 0x5, 267, 0, 370 }, -{ 0x3, 267, 0, 371 }, -{ 0x140, 276, 0, 348 }, -{ 0x540, 276, 0, 346 }, -{ 0x340, 276, 0, 347 }, -{ 0xc0, 276, 0, 360 }, -{ 0x2c0, 276, 0, 358 }, -{ 0x1c0, 276, 0, 359 }, -{ 0x20, 276, 0, 375 }, -{ 0xa0, 276, 0, 373 }, -{ 0x60, 276, 0, 374 }, -{ 0x10, 276, 0, 387 }, -{ 0x50, 276, 0, 385 }, -{ 0x30, 276, 0, 386 }, -{ 0x8, 276, 0, 399 }, -{ 0x28, 276, 0, 397 }, -{ 0x18, 276, 0, 398 }, -{ 0x4, 276, 0, 409 }, -{ 0x2, 276, 0, 410 }, -{ 0x1, 276, 0, 411 }, -{ 0x140, 270, 0, 351 }, -{ 0x540, 270, 0, 349 }, -{ 0x340, 270, 0, 350 }, -{ 0xc0, 270, 0, 363 }, -{ 0x2c0, 270, 0, 361 }, -{ 0x1c0, 270, 0, 362 }, -{ 0x20, 270, 0, 378 }, -{ 0xa0, 270, 0, 376 }, -{ 0x60, 270, 0, 377 }, -{ 0x10, 270, 0, 390 }, -{ 0x50, 270, 0, 388 }, -{ 0x30, 270, 0, 389 }, -{ 0x8, 270, 0, 402 }, -{ 0x28, 270, 0, 400 }, -{ 0x18, 270, 0, 401 }, -{ 0x4, 270, 0, 412 }, -{ 0x2, 270, 0, 413 }, -{ 0x1, 270, 0, 414 }, -{ 0x140, 273, 0, 354 }, -{ 0x540, 273, 0, 352 }, -{ 0x340, 273, 0, 353 }, -{ 0xc0, 273, 0, 366 }, -{ 0x2c0, 273, 0, 364 }, -{ 0x1c0, 273, 0, 365 }, -{ 0x20, 273, 0, 381 }, -{ 0xa0, 273, 0, 379 }, -{ 0x60, 273, 0, 380 }, -{ 0x10, 273, 0, 393 }, -{ 0x50, 273, 0, 391 }, -{ 0x30, 273, 0, 392 }, -{ 0x8, 273, 0, 405 }, -{ 0x28, 273, 0, 403 }, -{ 0x18, 273, 0, 404 }, -{ 0x4, 273, 0, 415 }, -{ 0x2, 273, 0, 416 }, -{ 0x1, 273, 0, 417 }, -{ 0x140, 285, 0, 357 }, -{ 0x540, 285, 0, 355 }, -{ 0x340, 285, 0, 356 }, -{ 0xc0, 285, 0, 369 }, -{ 0x2c0, 285, 0, 367 }, -{ 0x1c0, 285, 0, 368 }, -{ 0x20, 285, 0, 384 }, -{ 0xa0, 285, 0, 382 }, -{ 0x60, 285, 0, 383 }, -{ 0x10, 285, 0, 396 }, -{ 0x50, 285, 0, 394 }, -{ 0x30, 285, 0, 395 }, -{ 0x8, 285, 0, 408 }, -{ 0x28, 285, 0, 406 }, -{ 0x18, 285, 0, 407 }, -{ 0x4, 285, 0, 418 }, -{ 0x2, 285, 0, 419 }, -{ 0x1, 285, 0, 420 }, -{ 0x1, 266, 0, 447 }, -{ 0x5, 266, 0, 445 }, -{ 0x3, 266, 0, 446 }, -{ 0x140, 275, 0, 423 }, -{ 0x540, 275, 0, 421 }, -{ 0x340, 275, 0, 422 }, -{ 0xc0, 275, 0, 435 }, -{ 0x2c0, 275, 0, 433 }, -{ 0x1c0, 275, 0, 434 }, -{ 0x20, 275, 0, 450 }, -{ 0xa0, 275, 0, 448 }, -{ 0x60, 275, 0, 449 }, -{ 0x10, 275, 0, 462 }, -{ 0x50, 275, 0, 460 }, -{ 0x30, 275, 0, 461 }, -{ 0x8, 275, 0, 474 }, -{ 0x28, 275, 0, 472 }, -{ 0x18, 275, 0, 473 }, -{ 0x4, 275, 0, 484 }, -{ 0x2, 275, 0, 485 }, -{ 0x1, 275, 0, 486 }, -{ 0x140, 269, 0, 426 }, -{ 0x540, 269, 0, 424 }, -{ 0x340, 269, 0, 425 }, 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0x12, 63, 1, 2439 }, -{ 0x9, 64, 1, 2442 }, -{ 0x12, 64, 1, 2438 }, -{ 0x9, 65, 1, 2441 }, -{ 0x12, 65, 1, 2437 }, -{ 0x5, 66, 0, 2440 }, -{ 0xd, 62, 1, 2300 }, -{ 0x19, 63, 1, 2299 }, -{ 0x19, 64, 1, 2298 }, -{ 0x19, 65, 1, 2297 }, -{ 0x7, 81, 1, 2296 }, -{ 0x7, 82, 1, 2295 }, -{ 0x7, 83, 1, 2294 }, -{ 0x7, 84, 0, 2293 }, -{ 0x3, 62, 1, 2604 }, -{ 0x3, 63, 1, 2603 }, -{ 0x6, 63, 1, 2599 }, -{ 0x3, 64, 1, 2602 }, -{ 0x6, 64, 1, 2598 }, -{ 0x3, 65, 1, 2601 }, -{ 0x6, 65, 1, 2597 }, -{ 0x3, 66, 0, 2600 }, -{ 0x8, 86, 1, 2468 }, -{ 0x8, 87, 1, 2467 }, -{ 0x2, 88, 1, 2466 }, -{ 0x2, 89, 1, 2465 }, -{ 0x2, 90, 1, 2464 }, -{ 0x2, 91, 1, 2463 }, -{ 0x2, 92, 1, 2462 }, -{ 0x2, 93, 0, 2461 }, -{ 0x18, 86, 1, 2460 }, -{ 0x18, 87, 1, 2459 }, -{ 0x6, 88, 1, 2458 }, -{ 0x6, 89, 1, 2457 }, -{ 0x6, 90, 1, 2456 }, -{ 0x6, 91, 1, 2455 }, -{ 0x6, 92, 1, 2454 }, -{ 0x6, 93, 0, 2453 }, -{ 0x14, 86, 1, 2448 }, -{ 0x22, 87, 1, 2445 }, -{ 0x44, 87, 1, 2447 }, -{ 0xa, 94, 0, 2446 }, -{ 0x34, 86, 1, 2304 }, -{ 0xc4, 87, 1, 2303 }, -{ 0x38, 93, 1, 2301 }, -{ 0xe, 117, 0, 2302 }, -{ 0xc, 86, 1, 2608 }, -{ 0xa, 87, 1, 2605 }, -{ 0x14, 87, 1, 2607 }, -{ 0x6, 94, 0, 2606 }, -{ 0x2, 86, 1, 2316 }, -{ 0x2, 87, 1, 2315 }, -{ 0x4, 92, 1, 2314 }, -{ 0x4, 93, 0, 2313 }, -{ 0x12, 86, 1, 2312 }, -{ 0x42, 87, 1, 2311 }, -{ 0xc, 92, 1, 2310 }, -{ 0xc, 93, 0, 2309 }, -{ 0xa, 86, 1, 2452 }, -{ 0x12, 87, 1, 2451 }, -{ 0x24, 87, 1, 2449 }, -{ 0x5, 94, 0, 2450 }, -{ 0x1a, 86, 1, 2308 }, -{ 0x32, 87, 1, 2307 }, -{ 0x34, 93, 1, 2305 }, -{ 0x7, 117, 0, 2306 }, -{ 0x6, 86, 1, 2612 }, -{ 0x6, 87, 1, 2611 }, -{ 0xc, 87, 1, 2609 }, -{ 0x3, 94, 0, 2610 }, -{ 0x1, 86, 1, 2628 }, -{ 0x1, 87, 1, 2627 }, -{ 0x1, 88, 1, 2626 }, -{ 0x1, 89, 1, 2625 }, -{ 0x1, 90, 1, 2624 }, -{ 0x1, 91, 1, 2623 }, -{ 0x1, 92, 1, 2622 }, -{ 0x1, 93, 0, 2621 }, -{ 0x3, 86, 1, 2620 }, -{ 0x3, 87, 1, 2619 }, -{ 0x3, 88, 1, 2618 }, -{ 0x3, 89, 1, 2617 }, -{ 0x3, 90, 1, 2616 }, -{ 0x3, 91, 1, 2615 }, -{ 0x3, 92, 1, 2614 }, -{ 0x3, 93, 0, 2613 }, -{ 0x8, 53, 1, 2492 }, -{ 0x8, 54, 1, 2491 }, -{ 0x2, 55, 1, 2490 }, -{ 0x2, 56, 1, 2489 }, -{ 0x2, 57, 1, 2488 }, -{ 0x2, 58, 1, 2487 }, -{ 0x2, 59, 1, 2486 }, -{ 0x2, 60, 0, 2485 }, -{ 0x18, 53, 1, 2484 }, -{ 0x18, 54, 1, 2483 }, -{ 0x6, 55, 1, 2482 }, -{ 0x6, 56, 1, 2481 }, -{ 0x6, 57, 1, 2480 }, -{ 0x6, 58, 1, 2479 }, -{ 0x6, 59, 1, 2478 }, -{ 0x6, 60, 0, 2477 }, -{ 0x14, 53, 1, 2472 }, -{ 0x22, 54, 1, 2469 }, -{ 0x44, 54, 1, 2471 }, -{ 0xa, 61, 0, 2470 }, -{ 0x34, 53, 1, 2320 }, -{ 0xc4, 54, 1, 2319 }, -{ 0x38, 60, 1, 2317 }, -{ 0xe, 80, 0, 2318 }, -{ 0xc, 53, 1, 2632 }, -{ 0xa, 54, 1, 2629 }, -{ 0x14, 54, 1, 2631 }, -{ 0x6, 61, 0, 2630 }, -{ 0x2, 53, 1, 2332 }, -{ 0x2, 54, 1, 2331 }, -{ 0x4, 59, 1, 2330 }, -{ 0x4, 60, 0, 2329 }, -{ 0x12, 53, 1, 2328 }, -{ 0x42, 54, 1, 2327 }, -{ 0xc, 59, 1, 2326 }, -{ 0xc, 60, 0, 2325 }, -{ 0xa, 53, 1, 2476 }, -{ 0x12, 54, 1, 2475 }, -{ 0x24, 54, 1, 2473 }, -{ 0x5, 61, 0, 2474 }, -{ 0x1a, 53, 1, 2324 }, -{ 0x32, 54, 1, 2323 }, -{ 0x34, 60, 1, 2321 }, -{ 0x7, 80, 0, 2322 }, -{ 0x6, 53, 1, 2636 }, -{ 0x6, 54, 1, 2635 }, -{ 0xc, 54, 1, 2633 }, -{ 0x3, 61, 0, 2634 }, -{ 0x1, 53, 1, 2652 }, -{ 0x1, 54, 1, 2651 }, -{ 0x1, 55, 1, 2650 }, -{ 0x1, 56, 1, 2649 }, -{ 0x1, 57, 1, 2648 }, -{ 0x1, 58, 1, 2647 }, -{ 0x1, 59, 1, 2646 }, -{ 0x1, 60, 0, 2645 }, -{ 0x3, 53, 1, 2644 }, -{ 0x3, 54, 1, 2643 }, -{ 0x3, 55, 1, 2642 }, -{ 0x3, 56, 1, 2641 }, -{ 0x3, 57, 1, 2640 }, -{ 0x3, 58, 1, 2639 }, -{ 0x3, 59, 1, 2638 }, -{ 0x3, 60, 0, 2637 }, -{ 0x1, 4, 0, 2653 }, -{ 0x1, 296, 0, 2654 }, -{ 0x1, 379, 0, 2655 }, -{ 0x1, 374, 0, 2656 }, -{ 0x2, 358, 0, 2657 }, -{ 0x1, 358, 0, 2660 }, -{ 0x2, 357, 0, 2658 }, -{ 0x1, 357, 0, 2661 }, -{ 0x2, 356, 0, 2659 }, -{ 0x1, 356, 0, 2662 }, -{ 0x1, 355, 0, 2663 }, -{ 0x1, 354, 0, 2664 }, -{ 0x2, 353, 0, 2665 }, -{ 0x1, 353, 0, 2667 }, -{ 0x2, 352, 0, 2666 }, -{ 0x1, 352, 0, 2668 }, -{ 0x1, 382, 0, 2675 }, -{ 0x8, 381, 0, 2669 }, -{ 0x4, 381, 0, 2671 }, -{ 0x2, 381, 0, 2673 }, -{ 0x1, 381, 0, 2676 }, -{ 0x8, 380, 0, 2670 }, -{ 0x4, 380, 0, 2672 }, -{ 0x2, 380, 0, 2674 }, -{ 0x1, 380, 0, 2677 }, -{ 0x1, 351, 0, 2684 }, -{ 0x8, 350, 0, 2678 }, -{ 0x4, 350, 0, 2680 }, -{ 0x2, 350, 0, 2682 }, -{ 0x1, 350, 0, 2685 }, -{ 0x8, 349, 0, 2679 }, -{ 0x4, 349, 0, 2681 }, -{ 0x2, 349, 1, 2683 }, -{ 0x4, 143, 0, 1377 }, -{ 0x1, 349, 0, 2686 }, -{ 0x1, 6, 0, 2687 }, -{ 0x1, 7, 0, 2688 }, -{ 0x1, 295, 0, 2689 }, -{ 0x1, 456, 0, 2690 }, -{ 0x1, 346, 0, 2691 }, -{ 0x1, 13, 0, 2692 }, -{ 0x1, 11, 0, 2693 }, -{ 0x1, 422, 0, 2694 }, -{ 0x1, 394, 0, 2695 }, -{ 0x1, 393, 0, 2696 }, -{ 0x1, 455, 0, 2697 }, -{ 0x1, 345, 0, 2698 }, -{ 0x1, 12, 0, 2699 }, -{ 0x1, 10, 0, 2700 }, -{ 0x1, 5, 0, 2701 }, -{ 0x1, 421, 0, 2702 }, -{ 0x1, 420, 0, 2703 }, -{ 0x1, 1, 0, 2704 }, -{ 0x1, 0, 0, 2705 }, -}; - - -/* ia64-opc.c -- Functions to access the compacted opcode table - Copyright 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc. - Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, see - <http://www.gnu.org/licenses/>. */ - -static const struct ia64_templ_desc ia64_templ_desc[16] = - { - { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ - { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, - { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, - { 0, { 0, }, "-3-" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ - { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, - { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, - { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ - { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, - { 0, { 0, }, "-a-" }, - { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ - { 0, { 0, }, "-d-" }, - { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, - { 0, { 0, }, "-f-" }, - }; - -/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and - return the result. */ - -static ia64_insn -apply_completer (ia64_insn opcode, int completer_index) -{ - ia64_insn mask = completer_table[completer_index].mask; - ia64_insn bits = completer_table[completer_index].bits; - int shiftamt = (completer_table[completer_index].offset & 63); - - mask = mask << shiftamt; - bits = bits << shiftamt; - opcode = (opcode & ~mask) | bits; - return opcode; -} - -/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in - the dis_table array, and return its value. (BITOFFSET is numbered - starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the - first byte in OP_POINTER.) */ - -static int -extract_op_bits (int op_pointer, int bitoffset, int bits) -{ - int res = 0; - - op_pointer += (bitoffset / 8); - - if (bitoffset % 8) - { - unsigned int op = dis_table[op_pointer++]; - int numb = 8 - (bitoffset % 8); - int mask = (1 << numb) - 1; - int bata = (bits < numb) ? bits : numb; - int delta = numb - bata; - - res = (res << bata) | ((op & mask) >> delta); - bitoffset += bata; - bits -= bata; - } - while (bits >= 8) - { - res = (res << 8) | (dis_table[op_pointer++] & 255); - bits -= 8; - } - if (bits > 0) - { - unsigned int op = (dis_table[op_pointer++] & 255); - res = (res << bits) | (op >> (8 - bits)); - } - return res; -} - -/* Examine the state machine entry at OP_POINTER in the dis_table - array, and extract its values into OPVAL and OP. The length of the - state entry in bits is returned. */ - -static int -extract_op (int op_pointer, int *opval, unsigned int *op) -{ - int oplen = 5; - - *op = dis_table[op_pointer]; - - if ((*op) & 0x40) - { - opval[0] = extract_op_bits (op_pointer, oplen, 5); - oplen += 5; - } - switch ((*op) & 0x30) - { - case 0x10: - { - opval[1] = extract_op_bits (op_pointer, oplen, 8); - oplen += 8; - opval[1] += op_pointer; - break; - } - case 0x20: - { - opval[1] = extract_op_bits (op_pointer, oplen, 16); - if (! (opval[1] & 32768)) - { - opval[1] += op_pointer; - } - oplen += 16; - break; - } - case 0x30: - { - oplen--; - opval[2] = extract_op_bits (op_pointer, oplen, 12); - oplen += 12; - opval[2] |= 32768; - break; - } - } - if (((*op) & 0x08) && (((*op) & 0x30) != 0x30)) - { - opval[2] = extract_op_bits (op_pointer, oplen, 16); - oplen += 16; - if (! (opval[2] & 32768)) - { - opval[2] += op_pointer; - } - } - return oplen; -} - -/* Returns a non-zero value if the opcode in the main_table list at - PLACE matches OPCODE and is of type TYPE. */ - -static int -opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type) -{ - if (main_table[place].opcode_type != type) - { - return 0; - } - if (main_table[place].flags - & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) - { - const struct ia64_operand *o1, *o2; - ia64_insn f2, f3; - - if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) - { - o1 = elf64_ia64_operands + IA64_OPND_F2; - o2 = elf64_ia64_operands + IA64_OPND_F3; - (*o1->extract) (o1, opcode, &f2); - (*o2->extract) (o2, opcode, &f3); - if (f2 != f3) - return 0; - } - else - { - ia64_insn len, count; - - /* length must equal 64-count: */ - o1 = elf64_ia64_operands + IA64_OPND_LEN6; - o2 = elf64_ia64_operands + main_table[place].operands[2]; - (*o1->extract) (o1, opcode, &len); - (*o2->extract) (o2, opcode, &count); - if (len != 64 - count) - return 0; - } - } - return 1; -} - -/* Find an instruction entry in the ia64_dis_names array that matches - opcode OPCODE and is of type TYPE. Returns either a positive index - into the array, or a negative value if an entry for OPCODE could - not be found. Checks all matches and returns the one with the highest - priority. */ - -static int -locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type) -{ - int currtest[41]; - int bitpos[41]; - int op_ptr[41]; - int currstatenum = 0; - short found_disent = -1; - short found_priority = -1; - - currtest[currstatenum] = 0; - op_ptr[currstatenum] = 0; - bitpos[currstatenum] = 40; - - while (1) - { - int op_pointer = op_ptr[currstatenum]; - unsigned int op; - int currbitnum = bitpos[currstatenum]; - int oplen; - int opval[3] = {0}; - int next_op; - int currbit; - - oplen = extract_op (op_pointer, opval, &op); - - bitpos[currstatenum] = currbitnum; - - /* Skip opval[0] bits in the instruction. */ - if (op & 0x40) - { - currbitnum -= opval[0]; - } - - /* The value of the current bit being tested. */ - currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; - next_op = -1; - - /* We always perform the tests specified in the current state in - a particular order, falling through to the next test if the - previous one failed. */ - switch (currtest[currstatenum]) - { - case 0: - currtest[currstatenum]++; - if (currbit == 0 && (op & 0x80)) - { - /* Check for a zero bit. If this test solely checks for - a zero bit, we can check for up to 8 consecutive zero - bits (the number to check is specified by the lower 3 - bits in the state code.) - - If the state instruction matches, we go to the very - next state instruction; otherwise, try the next test. */ - - if ((op & 0xf8) == 0x80) - { - int count = op & 0x7; - int x; - - for (x = 0; x <= count; x++) - { - int i = - opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; - if (i) - { - break; - } - } - if (x > count) - { - next_op = op_pointer + ((oplen + 7) / 8); - currbitnum -= count; - break; - } - } - else if (! currbit) - { - next_op = op_pointer + ((oplen + 7) / 8); - break; - } - } - /* FALLTHROUGH */ - case 1: - /* If the bit in the instruction is one, go to the state - instruction specified by opval[1]. */ - currtest[currstatenum]++; - if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30)) - { - next_op = opval[1]; - break; - } - /* FALLTHROUGH */ - case 2: - /* Don't care. Skip the current bit and go to the state - instruction specified by opval[2]. - - An encoding of 0x30 is special; this means that a 12-bit - offset into the ia64_dis_names[] array is specified. */ - currtest[currstatenum]++; - if ((op & 0x08) || ((op & 0x30) == 0x30)) - { - next_op = opval[2]; - break; - } - } - - /* If bit 15 is set in the address of the next state, an offset - in the ia64_dis_names array was specified instead. We then - check to see if an entry in the list of opcodes matches the - opcode we were given; if so, we have succeeded. */ - - if ((next_op >= 0) && (next_op & 32768)) - { - short disent = next_op & 32767; - short priority = -1; - - if (next_op > 65535) - { - abort (); - } - - /* Run through the list of opcodes to check, trying to find - one that matches. */ - while (disent >= 0) - { - int place = ia64_dis_names[disent].insn_index; - - priority = ia64_dis_names[disent].priority; - - if (opcode_verify (opcode, place, type) - && priority > found_priority) - { - break; - } - if (ia64_dis_names[disent].next_flag) - { - disent++; - } - else - { - disent = -1; - } - } - - if (disent >= 0) - { - found_disent = disent; - found_priority = priority; - } - /* Try the next test in this state, regardless of whether a match - was found. */ - next_op = -2; - } - - /* next_op == -1 is "back up to the previous state". - next_op == -2 is "stay in this state and try the next test". - Otherwise, transition to the state indicated by next_op. */ - - if (next_op == -1) - { - currstatenum--; - if (currstatenum < 0) - { - return found_disent; - } - } - else if (next_op >= 0) - { - currstatenum++; - bitpos[currstatenum] = currbitnum - 1; - op_ptr[currstatenum] = next_op; - currtest[currstatenum] = 0; - } - } -} - -/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ - -static struct ia64_opcode * -make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind) -{ - struct ia64_opcode *res = - (struct ia64_opcode *) malloc (sizeof (struct ia64_opcode)); - res->name = strdup (name); - res->type = main_table[place].opcode_type; - res->num_outputs = main_table[place].num_outputs; - res->opcode = opcode; - res->mask = main_table[place].mask; - res->operands[0] = main_table[place].operands[0]; - res->operands[1] = main_table[place].operands[1]; - res->operands[2] = main_table[place].operands[2]; - res->operands[3] = main_table[place].operands[3]; - res->operands[4] = main_table[place].operands[4]; - res->flags = main_table[place].flags; - res->ent_index = place; - res->dependencies = &op_dependencies[depind]; - return res; -} - -/* Determine the ia64_opcode entry for the opcode specified by INSN - and TYPE. If a valid entry is not found, return NULL. */ -static struct ia64_opcode * -ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type) -{ - int disent = locate_opcode_ent (insn, type); - - if (disent < 0) - { - return NULL; - } - else - { - unsigned int cb = ia64_dis_names[disent].completer_index; - static char name[128]; - int place = ia64_dis_names[disent].insn_index; - int ci = main_table[place].completers; - ia64_insn tinsn = main_table[place].opcode; - - strcpy (name, ia64_strings [main_table[place].name_index]); - - while (cb) - { - if (cb & 1) - { - int cname = completer_table[ci].name_index; - - tinsn = apply_completer (tinsn, ci); - - if (ia64_strings[cname][0] != '\0') - { - strcat (name, "."); - strcat (name, ia64_strings[cname]); - } - if (cb != 1) - { - ci = completer_table[ci].subentries; - } - } - else - { - ci = completer_table[ci].alternative; - } - if (ci < 0) - { - abort (); - } - cb = cb >> 1; - } - if (tinsn != (insn & main_table[place].mask)) - { - abort (); - } - return make_ia64_opcode (insn, name, place, - completer_table[ci].dependencies); - } -} - -/* Free any resources used by ENT. */ -static void -ia64_free_opcode (struct ia64_opcode *ent) -{ - free ((void *)ent->name); - free (ent); -} - -/* Disassemble ia64 instruction. */ - -/* Return the instruction type for OPCODE found in unit UNIT. */ - -static enum ia64_insn_type -unit_to_type (ia64_insn opcode, enum ia64_unit unit) -{ - enum ia64_insn_type type; - int op; - - op = IA64_OP (opcode); - - if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M)) - { - type = IA64_TYPE_A; - } - else - { - switch (unit) - { - case IA64_UNIT_I: - type = IA64_TYPE_I; break; - case IA64_UNIT_M: - type = IA64_TYPE_M; break; - case IA64_UNIT_B: - type = IA64_TYPE_B; break; - case IA64_UNIT_F: - type = IA64_TYPE_F; break; - case IA64_UNIT_L: - case IA64_UNIT_X: - type = IA64_TYPE_X; break; - default: - type = -1; - } - } - return type; -} - -int -print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) -{ - ia64_insn t0, t1, slot[3], template, s_bit, insn; - int slotnum, j, status, need_comma, retval, slot_multiplier; - const struct ia64_operand *odesc; - const struct ia64_opcode *idesc; - const char *err, *str, *tname; - uint64_t value; - bfd_byte bundle[16]; - enum ia64_unit unit; - char regname[16]; - - if (info->bytes_per_line == 0) - info->bytes_per_line = 6; - info->display_endian = info->endian; - - slot_multiplier = info->bytes_per_line; - retval = slot_multiplier; - - slotnum = (((long) memaddr) & 0xf) / slot_multiplier; - if (slotnum > 2) - return -1; - - memaddr -= (memaddr & 0xf); - status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - /* bundles are always in little-endian byte order */ - t0 = bfd_getl64 (bundle); - t1 = bfd_getl64 (bundle + 8); - s_bit = t0 & 1; - template = (t0 >> 1) & 0xf; - slot[0] = (t0 >> 5) & 0x1ffffffffffLL; - slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); - slot[2] = (t1 >> 23) & 0x1ffffffffffLL; - - tname = ia64_templ_desc[template].name; - if (slotnum == 0) - (*info->fprintf_func) (info->stream, "[%s] ", tname); - else - (*info->fprintf_func) (info->stream, " "); - - unit = ia64_templ_desc[template].exec_unit[slotnum]; - - if (template == 2 && slotnum == 1) - { - /* skip L slot in MLI template: */ - slotnum = 2; - retval += slot_multiplier; - } - - insn = slot[slotnum]; - - if (unit == IA64_UNIT_NIL) - goto decoding_failed; - - idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); - if (idesc == NULL) - goto decoding_failed; - - /* print predicate, if any: */ - - if ((idesc->flags & IA64_OPCODE_NO_PRED) - || (insn & 0x3f) == 0) - (*info->fprintf_func) (info->stream, " "); - else - (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); - - /* now the actual instruction: */ - - (*info->fprintf_func) (info->stream, "%s", idesc->name); - if (idesc->operands[0]) - (*info->fprintf_func) (info->stream, " "); - - need_comma = 0; - for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) - { - odesc = elf64_ia64_operands + idesc->operands[j]; - - if (need_comma) - (*info->fprintf_func) (info->stream, ","); - - if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) - { - /* special case of 64 bit immediate load: */ - value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) - | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) - | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); - } - else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) - { - /* 62-bit immediate for nop.x/break.x */ - value = ((slot[1] & 0x1ffffffffffLL) << 21) - | (((insn >> 36) & 0x1) << 20) - | ((insn >> 6) & 0xfffff); - } - else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) - { - /* 60-bit immediate for long branches. */ - value = (((insn >> 13) & 0xfffff) - | (((insn >> 36) & 1) << 59) - | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4; - } - else - { - err = (*odesc->extract) (odesc, insn, &value); - if (err) - { - (*info->fprintf_func) (info->stream, "%s", err); - goto done; - } - } - - switch (odesc->class) - { - case IA64_OPND_CLASS_CST: - (*info->fprintf_func) (info->stream, "%s", odesc->str); - break; - - case IA64_OPND_CLASS_REG: - if (odesc->str[0] == 'a' && odesc->str[1] == 'r') - { - switch (value) - { - case 0: case 1: case 2: case 3: - case 4: case 5: case 6: case 7: - sprintf (regname, "ar.k%u", (unsigned int) value); - break; - case 16: strcpy (regname, "ar.rsc"); break; - case 17: strcpy (regname, "ar.bsp"); break; - case 18: strcpy (regname, "ar.bspstore"); break; - case 19: strcpy (regname, "ar.rnat"); break; - case 32: strcpy (regname, "ar.ccv"); break; - case 36: strcpy (regname, "ar.unat"); break; - case 40: strcpy (regname, "ar.fpsr"); break; - case 44: strcpy (regname, "ar.itc"); break; - case 64: strcpy (regname, "ar.pfs"); break; - case 65: strcpy (regname, "ar.lc"); break; - case 66: strcpy (regname, "ar.ec"); break; - default: - sprintf (regname, "ar%u", (unsigned int) value); - break; - } - (*info->fprintf_func) (info->stream, "%s", regname); - } - else - (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value); - break; - - case IA64_OPND_CLASS_IND: - (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value); - break; - - case IA64_OPND_CLASS_ABS: - str = 0; - if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4) - switch (value) - { - case 0x0: str = "@brcst"; break; - case 0x8: str = "@mix"; break; - case 0x9: str = "@shuf"; break; - case 0xa: str = "@alt"; break; - case 0xb: str = "@rev"; break; - } - - if (str) - (*info->fprintf_func) (info->stream, "%s", str); - else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) - (*info->fprintf_func) (info->stream, "%" PRId64, - (int64_t) value); - else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) - (*info->fprintf_func) (info->stream, "%" PRIu64, - (uint64_t) value); - else - (*info->fprintf_func) (info->stream, "0x%" PRIx64, - (uint64_t) value); - break; - - case IA64_OPND_CLASS_REL: - (*info->print_address_func) (memaddr + value, info); - break; - } - - need_comma = 1; - if (j + 1 == idesc->num_outputs) - { - (*info->fprintf_func) (info->stream, "="); - need_comma = 0; - } - } - if (slotnum + 1 == ia64_templ_desc[template].group_boundary - || ((slotnum == 2) && s_bit)) - (*info->fprintf_func) (info->stream, ";;"); - - done: - ia64_free_opcode ((struct ia64_opcode *)idesc); - failed: - if (slotnum == 2) - retval += 16 - 3*slot_multiplier; - return retval; - - decoding_failed: - (*info->fprintf_func) (info->stream, " data8 %#011llx", (long long) insn); - goto failed; -} diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 440fc31b37..ff8fbe423d 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -35,35 +35,6 @@ typedef abi_ulong tb_page_addr_t; typedef ram_addr_t tb_page_addr_t; #endif -/* DisasContext is_jmp field values - * - * is_jmp starts as DISAS_NEXT. The translator will keep processing - * instructions until an exit condition is reached. If we reach the - * exit condition and is_jmp is still DISAS_NEXT (because of some - * other condition) we simply "jump" to the next address. - * The remaining exit cases are: - * - * DISAS_JUMP - Only the PC was modified dynamically (e.g computed) - * DISAS_TB_JUMP - Only the PC was modified statically (e.g. branch) - * - * In these cases as long as the PC is updated we can chain to the - * next TB either by exiting the loop or looking up the next TB via - * the loookup helper. - * - * DISAS_UPDATE - CPU State was modified dynamically - * - * This covers any other CPU state which necessities us exiting the - * TCG code to the main run-loop. Typically this includes anything - * that might change the interrupt state. - * - * Individual translators may define additional exit cases to deal - * with per-target special conditions. - */ -#define DISAS_NEXT 0 /* next instruction can be analyzed */ -#define DISAS_JUMP 1 /* only pc was modified dynamically */ -#define DISAS_TB_JUMP 2 /* only pc was modified statically */ -#define DISAS_UPDATE 3 /* cpu state was modified dynamically */ - #include "qemu/log.h" void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); diff --git a/include/exec/translator.h b/include/exec/translator.h new file mode 100644 index 0000000000..e2dc2a04ae --- /dev/null +++ b/include/exec/translator.h @@ -0,0 +1,144 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef EXEC__TRANSLATOR_H +#define EXEC__TRANSLATOR_H + +/* + * Include this header from a target-specific file, and add a + * + * DisasContextBase base; + * + * member in your target-specific DisasContext. + */ + + +#include "exec/exec-all.h" +#include "tcg/tcg.h" + + +/** + * DisasJumpType: + * @DISAS_NEXT: Next instruction in program order. + * @DISAS_TOO_MANY: Too many instructions translated. + * @DISAS_NORETURN: Following code is dead. + * @DISAS_TARGET_*: Start of target-specific conditions. + * + * What instruction to disassemble next. + */ +typedef enum DisasJumpType { + DISAS_NEXT, + DISAS_TOO_MANY, + DISAS_NORETURN, + DISAS_TARGET_0, + DISAS_TARGET_1, + DISAS_TARGET_2, + DISAS_TARGET_3, + DISAS_TARGET_4, + DISAS_TARGET_5, + DISAS_TARGET_6, + DISAS_TARGET_7, + DISAS_TARGET_8, + DISAS_TARGET_9, + DISAS_TARGET_10, + DISAS_TARGET_11, +} DisasJumpType; + +/** + * DisasContextBase: + * @tb: Translation block for this disassembly. + * @pc_first: Address of first guest instruction in this TB. + * @pc_next: Address of next guest instruction in this TB (current during + * disassembly). + * @is_jmp: What instruction to disassemble next. + * @num_insns: Number of translated instructions (including current). + * @singlestep_enabled: "Hardware" single stepping enabled. + * + * Architecture-agnostic disassembly context. + */ +typedef struct DisasContextBase { + TranslationBlock *tb; + target_ulong pc_first; + target_ulong pc_next; + DisasJumpType is_jmp; + unsigned int num_insns; + bool singlestep_enabled; +} DisasContextBase; + +/** + * TranslatorOps: + * @init_disas_context: + * Initialize the target-specific portions of DisasContext struct. + * The generic DisasContextBase has already been initialized. + * Return max_insns, modified as necessary by db->tb->flags. + * + * @tb_start: + * Emit any code required before the start of the main loop, + * after the generic gen_tb_start(). + * + * @insn_start: + * Emit the tcg_gen_insn_start opcode. + * + * @breakpoint_check: + * When called, the breakpoint has already been checked to match the PC, + * but the target may decide the breakpoint missed the address + * (e.g., due to conditions encoded in their flags). Return true to + * indicate that the breakpoint did hit, in which case no more breakpoints + * are checked. If the breakpoint did hit, emit any code required to + * signal the exception, and set db->is_jmp as necessary to terminate + * the main loop. + * + * @translate_insn: + * Disassemble one instruction and set db->pc_next for the start + * of the following instruction. Set db->is_jmp as necessary to + * terminate the main loop. + * + * @tb_stop: + * Emit any opcodes required to exit the TB, based on db->is_jmp. + * + * @disas_log: + * Print instruction disassembly to log. + */ +typedef struct TranslatorOps { + int (*init_disas_context)(DisasContextBase *db, CPUState *cpu, + int max_insns); + void (*tb_start)(DisasContextBase *db, CPUState *cpu); + void (*insn_start)(DisasContextBase *db, CPUState *cpu); + bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, + const CPUBreakpoint *bp); + void (*translate_insn)(DisasContextBase *db, CPUState *cpu); + void (*tb_stop)(DisasContextBase *db, CPUState *cpu); + void (*disas_log)(const DisasContextBase *db, CPUState *cpu); +} TranslatorOps; + +/** + * translator_loop: + * @ops: Target-specific operations. + * @db: Disassembly context. + * @cpu: Target vCPU. + * @tb: Translation block. + * + * Generic translator loop. + * + * Translation will stop in the following cases (in order): + * - When is_jmp set by #TranslatorOps::breakpoint_check. + * - set to DISAS_TOO_MANY exits after translating one more insn + * - set to any other value than DISAS_NEXT exits immediately. + * - When is_jmp set by #TranslatorOps::translate_insn. + * - set to any value other than DISAS_NEXT exits immediately. + * - When the TCG operation buffer is full. + * - When single-stepping is enabled (system-wide or on the current vCPU). + * - When too many instructions have been translated. + */ +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb); + +void translator_loop_temp_check(DisasContextBase *db); + +#endif /* EXEC__TRANSLATOR_H */ diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 95cf4f4163..5ac621cf1f 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -369,27 +369,35 @@ static inline bool is_power_of_2(uint64_t value) return !(value & (value - 1)); } -/* round down to the nearest power of 2*/ -static inline int64_t pow2floor(int64_t value) +/** + * Return @value rounded down to the nearest power of two or zero. + */ +static inline uint64_t pow2floor(uint64_t value) { - if (!is_power_of_2(value)) { - value = 0x8000000000000000ULL >> clz64(value); + if (!value) { + /* Avoid undefined shift by 64 */ + return 0; } - return value; + return 0x8000000000000000ull >> clz64(value); } -/* round up to the nearest power of 2 (0 if overflow) */ +/* + * Return @value rounded up to the nearest power of two modulo 2^64. + * This is *zero* for @value > 2^63, so be careful. + */ static inline uint64_t pow2ceil(uint64_t value) { - uint8_t nlz = clz64(value); - - if (is_power_of_2(value)) { - return value; - } - if (!nlz) { - return 0; + int n = clz64(value - 1); + + if (!n) { + /* + * @value - 1 has no leading zeroes, thus @value - 1 >= 2^63 + * Therefore, either @value == 0 or @value > 2^63. + * If it's 0, return 1, else return 0. + */ + return !value; } - return 1ULL << (64 - nlz); + return 0x8000000000000000ull >> (n - 1); } /** diff --git a/migration/migration.c b/migration/migration.c index 1a2b3ebd1a..959e8ec88e 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -166,7 +166,7 @@ void migration_incoming_state_destroy(void) mis->from_src_file = NULL; } - qemu_event_destroy(&mis->main_thread_load_event); + qemu_event_reset(&mis->main_thread_load_event); } static void migrate_generate_event(int new_state) @@ -913,8 +913,9 @@ void qmp_migrate_start_postcopy(Error **errp) void migrate_set_state(int *state, int old_state, int new_state) { + assert(new_state < MIGRATION_STATUS__MAX); if (atomic_cmpxchg(state, old_state, new_state) == old_state) { - trace_migrate_set_state(new_state); + trace_migrate_set_state(MigrationStatus_str(new_state)); migrate_generate_event(new_state); } } diff --git a/migration/page_cache.c b/migration/page_cache.c index 5f8578736e..ba984c4858 100644 --- a/migration/page_cache.c +++ b/migration/page_cache.c @@ -178,59 +178,3 @@ int cache_insert(PageCache *cache, uint64_t addr, const uint8_t *pdata, return 0; } - -int64_t cache_resize(PageCache *cache, int64_t new_num_pages) -{ - PageCache *new_cache; - int64_t i; - - CacheItem *old_it, *new_it; - - g_assert(cache); - - /* cache was not inited */ - if (cache->page_cache == NULL) { - return -1; - } - - /* same size */ - if (pow2floor(new_num_pages) == cache->max_num_items) { - return cache->max_num_items; - } - - new_cache = cache_init(new_num_pages, cache->page_size); - if (!(new_cache)) { - DPRINTF("Error creating new cache\n"); - return -1; - } - - /* move all data from old cache */ - for (i = 0; i < cache->max_num_items; i++) { - old_it = &cache->page_cache[i]; - if (old_it->it_addr != -1) { - /* check for collision, if there is, keep MRU page */ - new_it = cache_get_by_addr(new_cache, old_it->it_addr); - if (new_it->it_data && new_it->it_age >= old_it->it_age) { - /* keep the MRU page */ - g_free(old_it->it_data); - } else { - if (!new_it->it_data) { - new_cache->num_items++; - } - g_free(new_it->it_data); - new_it->it_data = old_it->it_data; - new_it->it_age = old_it->it_age; - new_it->it_addr = old_it->it_addr; - } - } - } - - g_free(cache->page_cache); - cache->page_cache = new_cache->page_cache; - cache->max_num_items = new_cache->max_num_items; - cache->num_items = new_cache->num_items; - - g_free(new_cache); - - return cache->max_num_items; -} diff --git a/migration/page_cache.h b/migration/page_cache.h index 10ed53274c..4fadd0c501 100644 --- a/migration/page_cache.h +++ b/migration/page_cache.h @@ -72,15 +72,4 @@ uint8_t *get_cached_data(const PageCache *cache, uint64_t addr); int cache_insert(PageCache *cache, uint64_t addr, const uint8_t *pdata, uint64_t current_age); -/** - * cache_resize: resize the page cache. In case of size reduction the extra - * pages will be freed - * - * Returns -1 on error new cache size on success - * - * @cache pointer to the PageCache struct - * @num_pages: new page cache size (in pages) - */ -int64_t cache_resize(PageCache *cache, int64_t num_pages); - #endif diff --git a/migration/savevm.c b/migration/savevm.c index fdd15fa0a7..7a55023d1a 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -1157,6 +1157,8 @@ int qemu_savevm_state_complete_precopy(QEMUFile *f, bool iterable_only, * bdrv_invalidate_cache_all() on the other end won't fail. */ ret = bdrv_inactivate_all(); if (ret) { + error_report("%s: bdrv_inactivate_all() failed (%d)", + __func__, ret); qemu_file_set_error(f, ret); return ret; } diff --git a/migration/trace-events b/migration/trace-events index 7a3b5144ff..d2910a6e7b 100644 --- a/migration/trace-events +++ b/migration/trace-events @@ -80,7 +80,7 @@ ram_save_queue_pages(const char *rbname, size_t start, size_t len) "%s: start: 0 # migration/migration.c await_return_path_close_on_source_close(void) "" await_return_path_close_on_source_joining(void) "" -migrate_set_state(int new_state) "new state %d" +migrate_set_state(const char *new_state) "new state %s" migrate_fd_cleanup(void) "" migrate_fd_error(const char *error_desc) "error=%s" migrate_fd_cancel(void) "" diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cb44632d16..9017e30510 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp = DISAS_EXC; + s->base.is_jmp = DISAS_NORETURN; } static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp = DISAS_EXC; + s->base.is_jmp = DISAS_NORETURN; } static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp = DISAS_EXC; + s->base.is_jmp = DISAS_NORETURN; } static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -348,13 +348,13 @@ static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) { + if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags & CF_LAST_IO)) { return false; } #ifndef CONFIG_USER_ONLY /* Only link tbs from inside the same guest page */ - if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { + if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { return false; } #endif @@ -366,21 +366,21 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) { TranslationBlock *tb; - tb = s->tb; + tb = s->base.tb; if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { gen_step_complete_exception(s); - } else if (s->singlestep_enabled) { + } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } } } @@ -1331,16 +1331,16 @@ static void handle_hint(DisasContext *s, uint32_t insn, case 0: /* NOP */ return; case 3: /* WFI */ - s->is_jmp = DISAS_WFI; + s->base.is_jmp = DISAS_WFI; return; case 1: /* YIELD */ if (!parallel_cpus) { - s->is_jmp = DISAS_YIELD; + s->base.is_jmp = DISAS_YIELD; } return; case 2: /* WFE */ if (!parallel_cpus) { - s->is_jmp = DISAS_WFE; + s->base.is_jmp = DISAS_WFE; } return; case 4: /* SEV */ @@ -1424,7 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, tcg_temp_free_i32(tcg_op); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ gen_a64_set_pc_im(s->pc); - s->is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); + s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); break; } default: @@ -1559,7 +1559,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, break; } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -1590,16 +1590,16 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, } } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } } @@ -1789,7 +1789,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } gen_helper_exception_return(cpu_env); /* Must exit loop to check un-masked IRQs */ - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; return; case 5: /* DRPS */ if (rn != 0x1f) { @@ -1803,7 +1803,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) return; } - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; } /* C3.2 Branches, exception generating and system instructions */ @@ -11200,23 +11200,15 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) +static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUARMState *env = cs->env_ptr; - ARMCPU *cpu = arm_env_get_cpu(env); - DisasContext dc1, *dc = &dc1; - target_ulong pc_start; - target_ulong next_page_start; - int num_insns; - int max_insns; + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); + int bound; - pc_start = tb->pc; - - dc->tb = tb; - - dc->is_jmp = DISAS_NEXT; - dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->pc = dc->base.pc_first; dc->condjmp = 0; dc->aarch64 = 1; @@ -11227,20 +11219,20 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; + dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); - dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags); - dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags); + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); + dc->tbi0 = ARM_TBFLAG_TBI0(dc->base.tb->flags); + dc->tbi1 = ARM_TBFLAG_TBI1(dc->base.tb->flags); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags); + dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; - dc->cp_regs = cpu->cp_regs; + dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -11258,127 +11250,131 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); - init_tmp_a64_array(dc); + /* Bound the number of insns to execute to those left on the page. */ + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; - next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; + /* If architectural single step active, limit to 1. */ + if (dc->ss_active) { + bound = 1; } + max_insns = MIN(max_insns, bound); - gen_tb_start(tb); + init_tmp_a64_array(dc); + return max_insns; +} + +static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ tcg_clear_temp_count(); +} - do { - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); - num_insns++; - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->is_jmp = DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - dc->pc += 4; - goto done_generating; - } - break; - } - } - } +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debugged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->is_jmp = DISAS_EXC; - break; - } +static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); - disas_a64_insn(env, dc); + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp = DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc += 4; + dc->base.is_jmp = DISAS_NORETURN; + } - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } + return true; +} + +static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. */ - } while (!dc->is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - num_insns < max_insns); - - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); + assert(dc->base.num_insns == 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp = DISAS_NORETURN; + } else { + disas_a64_insn(env, dc); } - if (unlikely(cs->singlestep_enabled || dc->ss_active) - && dc->is_jmp != DISAS_EXC) { + dc->base.pc_next = dc->pc; + translator_loop_temp_check(&dc->base); +} + +static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { /* Note that this means single stepping WFI doesn't halt the CPU. * For conditional branch insns this is harmless unreachable code as * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - assert(dc->is_jmp != DISAS_TB_JUMP); - if (dc->is_jmp != DISAS_JUMP) { + switch (dc->base.is_jmp) { + default: gen_a64_set_pc_im(dc->pc); - } - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); + /* fall through */ + case DISAS_JUMP: + if (dc->base.singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; } } else { - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; + default: + case DISAS_UPDATE: + gen_a64_set_pc_im(dc->pc); + /* fall through */ case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(cpu_pc); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_EXIT: + tcg_gen_exit_tb(0); + break; + case DISAS_NORETURN: case DISAS_SWI: break; case DISAS_WFE: @@ -11400,31 +11396,29 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) */ tcg_gen_exit_tb(0); break; - case DISAS_UPDATE: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_EXIT: - default: - tcg_gen_exit_tb(0); - break; } } -done_generating: - gen_tb_end(tb, num_insns); + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next = dc->pc; +} -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, - 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif - tb->size = dc->pc - pc_start; - tb->icount = num_insns; +static void aarch64_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } + +const TranslatorOps aarch64_translator_ops = { + .init_disas_context = aarch64_tr_init_disas_context, + .tb_start = aarch64_tr_tb_start, + .insn_start = aarch64_tr_insn_start, + .breakpoint_check = aarch64_tr_breakpoint_check, + .translate_insn = aarch64_tr_translate_insn, + .tb_stop = aarch64_tr_tb_stop, + .disas_log = aarch64_tr_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index 57899fa55b..ab1a12a1b8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -224,7 +224,7 @@ static void store_reg(DisasContext *s, int reg, TCGv_i32 var) * We choose to ignore [1:0] in ARM mode for all architecture versions. */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; } tcg_gen_mov_i32(cpu_R[reg], var); tcg_temp_free_i32(var); @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp = DISAS_EXC; + s->base.is_jmp = DISAS_NORETURN; } static void gen_singlestep_exception(DisasContext *s) @@ -321,7 +321,7 @@ static inline bool is_singlestepping(DisasContext *s) * misnamed as it only means "one instruction per TB" and doesn't * affect the code we generate. */ - return s->singlestep_enabled || s->ss_active; + return s->base.singlestep_enabled || s->ss_active; } static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) @@ -930,7 +930,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr) { TCGv_i32 tmp; - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; if (s->thumb != (addr & 1)) { tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, addr & 1); @@ -943,7 +943,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr) /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); @@ -957,11 +957,11 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { /* Generate the same code here as for a simple bx, but flag via - * s->is_jmp that we need to do the rest of the work later. + * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) { - s->is_jmp = DISAS_BX_EXCRET; + s->base.is_jmp = DISAS_BX_EXCRET; } } @@ -1010,7 +1010,7 @@ static inline void gen_bxns(DisasContext *s, int rm) */ gen_helper_v7m_bxns(cpu_env, var); tcg_temp_free_i32(var); - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; } /* Variant of store_reg which uses branch&exchange logic when storing @@ -1180,7 +1180,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) */ s->svc_imm = imm16; gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_HVC; + s->base.is_jmp = DISAS_HVC; } static inline void gen_smc(DisasContext *s) @@ -1195,7 +1195,7 @@ static inline void gen_smc(DisasContext *s) gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_SMC; + s->base.is_jmp = DISAS_SMC; } static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) @@ -1203,7 +1203,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp = DISAS_EXC; + s->base.is_jmp = DISAS_NORETURN; } static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1212,14 +1212,14 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp = DISAS_EXC; + s->base.is_jmp = DISAS_NORETURN; } /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; } static inline void gen_hlt(DisasContext *s, int imm) @@ -4164,7 +4164,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || + return (s->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || ((s->pc - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); #else return true; @@ -4188,12 +4188,12 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); - tcg_gen_exit_tb((uintptr_t)s->tb + n); + tcg_gen_exit_tb((uintptr_t)s->base.tb + n); } else { gen_set_pc_im(s, dest); gen_goto_ptr(); } - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } static inline void gen_jmp (DisasContext *s, uint32_t dest) @@ -4455,7 +4455,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_reg); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) @@ -4477,7 +4477,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); store_reg(s, rn, tcg_reg); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } /* Store value to PC as for an exception return (ie don't @@ -4501,7 +4501,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); /* Must exit loop to check un-masked IRQs */ - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; } /* Generate an old-style exception return. Marks pc as dead. */ @@ -4524,17 +4524,17 @@ static void gen_nop_hint(DisasContext *s, int val) case 1: /* yield */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_YIELD; + s->base.is_jmp = DISAS_YIELD; } break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_WFI; + s->base.is_jmp = DISAS_WFI; break; case 2: /* wfe */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_WFE; + s->base.is_jmp = DISAS_WFE; } break; case 4: /* sev */ @@ -7673,13 +7673,13 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) return 1; } gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_WFI; + s->base.is_jmp = DISAS_WFI; return 0; default: break; } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -7770,7 +7770,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); gen_lookup_tb(s); @@ -8084,7 +8084,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -8172,7 +8172,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* setend */ if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } return; } else if ((insn & 0x0fffff00) == 0x057ff000) { @@ -9546,7 +9546,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); /* Must exit loop to check un-masked IRQs */ - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; } } break; @@ -9584,7 +9584,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm = extract32(insn, 0, 24); - s->is_jmp = DISAS_SWI; + s->base.is_jmp = DISAS_SWI; break; default: illegal_op: @@ -11695,7 +11695,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) ARCH(6); if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } break; case 3: @@ -11789,7 +11789,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm = extract32(insn, 0, 8); - s->is_jmp = DISAS_SWI; + s->base.is_jmp = DISAS_SWI; break; } /* generate a conditional jump to next instruction */ @@ -11862,35 +11862,14 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) return false; } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int arm_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; ARMCPU *cpu = arm_env_get_cpu(env); - DisasContext dc1, *dc = &dc1; - target_ulong pc_start; - target_ulong next_page_start; - int num_insns; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cs, tb); - return; - } - pc_start = tb->pc; - - dc->tb = tb; - - dc->is_jmp = DISAS_NEXT; - dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->pc = dc->base.pc_first; dc->condjmp = 0; dc->aarch64 = 0; @@ -11899,23 +11878,23 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) */ dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb = ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb = ARM_TBFLAG_THUMB(dc->base.tb->flags); + dc->sctlr_b = ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); + dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) << 1; + dc->condexec_cond = ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->ns = ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags); + dc->ns = ARM_TBFLAG_NS(dc->base.tb->flags); + dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->vfp_enabled = ARM_TBFLAG_VFPEN(dc->base.tb->flags); + dc->vec_len = ARM_TBFLAG_VECLEN(dc->base.tb->flags); + dc->vec_stride = ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); + dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); + dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(dc->base.tb->flags); dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); dc->cp_regs = cpu->cp_regs; @@ -11936,11 +11915,26 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ + dc->next_page_start = + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + + /* If architectural single step active, limit to 1. */ + if (is_singlestepping(dc)) { + max_insns = 1; + } + + /* ARM is a fixed-length ISA. Bound the number of insns to execute + to those left on the page. */ + if (!dc->thumb) { + int bound = (dc->next_page_start - dc->base.pc_first) / 4; + max_insns = MIN(max_insns, bound); + } + cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); @@ -11949,19 +11943,13 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) cpu_V1 = cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 = tcg_temp_new_i64(); - next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - gen_tb_start(tb); + return max_insns; +} - tcg_clear_temp_count(); +static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); /* A note on handling of the condexec (IT) bits: * @@ -11995,141 +11983,173 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) /* Reset the conditional execution bits immediately. This avoids complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { + if (dc->condexec_mask || dc->condexec_cond) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, 0); store_cpu_field(tmp, condexec_bits); - } - do { - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); - num_insns++; + } + tcg_clear_temp_count(); +} + +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} +static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp = DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc += 2; + dc->base.is_jmp = DISAS_NORETURN; + } + + return true; +} + +static bool arm_pre_translate_insn(DisasContext *dc) +{ #ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >= 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp = DISAS_EXC; - break; - } + /* Intercept jump to the magic kernel page. */ + if (dc->pc >= 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp = DISAS_NORETURN; + return true; + } #endif - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be executed */ - dc->is_jmp = DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length to - * avoid disassembler error messages */ - dc->pc += 2; - goto done_generating; - } - break; - } - } - } + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns == 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp = DISAS_NORETURN; + return true; + } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } + return false; +} - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debugged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - goto done_generating; - } +static void arm_post_translate_insn(DisasContext *dc) +{ + if (dc->condjmp && !dc->base.is_jmp) { + gen_set_label(dc->condlabel); + dc->condjmp = 0; + } + dc->base.pc_next = dc->pc; + translator_loop_temp_check(&dc->base); +} - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond = (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask == 0) { - dc->condexec_cond = 0; - } - } - } else { - unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc += 4; - disas_arm_insn(dc, insn); - } +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + unsigned int insn; - if (dc->condjmp && !dc->is_jmp) { - gen_set_label(dc->condlabel); - dc->condjmp = 0; - } + if (arm_pre_translate_insn(dc)) { + return; + } - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } + insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc += 4; + disas_arm_insn(dc, insn); - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ + arm_post_translate_insn(dc); - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - end_of_page = (dc->pc >= next_page_start) || - ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc)); + /* ARM is a fixed-length ISA. We performed the cross-page check + in init_disas_context by adjusting max_insns. */ +} - } while (!dc->is_jmp && !tcg_op_buf_full() && - !is_singlestepping(dc) && - !singlestep && - !end_of_page && - num_insns < max_insns); +static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); + if (arm_pre_translate_insn(dc)) { + return; + } + + disas_thumb_insn(env, dc); + + /* Advance the Thumb condexec condition. */ + if (dc->condexec_mask) { + dc->condexec_cond = ((dc->condexec_cond & 0xe) | + ((dc->condexec_mask >> 4) & 1)); + dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask == 0) { + dc->condexec_cond = 0; } - gen_io_end(); + } + + arm_post_translate_insn(dc); + + /* Thumb is a variable-length ISA. Stop translation when the next insn + * will touch a new page. This ensures that prefetch aborts occur at + * the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp == DISAS_NEXT + && (dc->pc >= dc->next_page_start + || (dc->pc >= dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp = DISAS_TOO_MANY; + } +} + +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. */ + cpu_abort(cpu, "IO on conditional branch instruction"); } /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ gen_set_condexec(dc); - if (dc->is_jmp == DISAS_BX_EXCRET) { + if (dc->base.is_jmp == DISAS_BX_EXCRET) { /* Exception return branches need some special case code at the * end of the TB, which is complex enough that it has to * handle the single-step vs not and the condition-failed @@ -12138,7 +12158,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_bx_excret_final_code(dc); } else if (unlikely(is_singlestepping(dc))) { /* Unconditional and "condition passed" instruction codepath. */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), @@ -12153,12 +12173,16 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_exception(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: + case DISAS_TOO_MANY: case DISAS_UPDATE: gen_set_pc_im(dc, dc->pc); /* fall through */ default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ gen_singlestep_exception(dc); + break; + case DISAS_NORETURN: + break; } } else { /* While branches must always occur at the end of an IT block, @@ -12169,8 +12193,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) - Hardware watchpoints. Hardware breakpoints have already been handled and skip this code. */ - switch(dc->is_jmp) { + switch(dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -12183,8 +12208,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) /* indicate that the hash table must be used to find the next TB */ tcg_gen_exit_tb(0); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: /* nothing more to generate */ break; case DISAS_WFI: @@ -12225,23 +12249,55 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) } } -done_generating: - gen_tb_end(tb, num_insns); + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next = dc->pc; +} + +static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, - dc->thumb | (dc->sctlr_b << 1)); - qemu_log("\n"); - qemu_log_unlock(); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + dc->thumb | (dc->sctlr_b << 1)); +} + +static const TranslatorOps arm_translator_ops = { + .init_disas_context = arm_tr_init_disas_context, + .tb_start = arm_tr_tb_start, + .insn_start = arm_tr_insn_start, + .breakpoint_check = arm_tr_breakpoint_check, + .translate_insn = arm_tr_translate_insn, + .tb_stop = arm_tr_tb_stop, + .disas_log = arm_tr_disas_log, +}; + +static const TranslatorOps thumb_translator_ops = { + .init_disas_context = arm_tr_init_disas_context, + .tb_start = arm_tr_tb_start, + .insn_start = arm_tr_insn_start, + .breakpoint_check = arm_tr_breakpoint_check, + .translate_insn = thumb_tr_translate_insn, + .tb_stop = arm_tr_tb_stop, + .disas_log = arm_tr_disas_log, +}; + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; + const TranslatorOps *ops = &arm_translator_ops; + + if (ARM_TBFLAG_THUMB(tb->flags)) { + ops = &thumb_translator_ops; + } +#ifdef TARGET_AARCH64 + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + ops = &aarch64_translator_ops; } #endif - tb->size = dc->pc - pc_start; - tb->icount = num_insns; + + translator_loop(ops, &dc.base, cpu, tb); } static const char *cpu_mode_names[16] = { diff --git a/target/arm/translate.h b/target/arm/translate.h index ef625adaa2..3c96aec956 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -1,11 +1,16 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H +#include "exec/translator.h" + + /* internal defines */ typedef struct DisasContext { + DisasContextBase base; + target_ulong pc; + target_ulong next_page_start; uint32_t insn; - int is_jmp; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; /* The label that will be jumped to when the instruction is skipped. */ @@ -13,8 +18,6 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; int thumb; int sctlr_b; TCGMemOp be_data; @@ -120,49 +123,43 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) s->insn_start_idx = 0; } -/* target-specific extra values for is_jmp */ +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 4 -#define DISAS_SWI 5 -/* For instructions which unconditionally cause an exception we can skip - * emitting unreachable code at the end of the TB in the A64 decoder - */ -#define DISAS_EXC 6 +#define DISAS_WFI DISAS_TARGET_2 +#define DISAS_SWI DISAS_TARGET_3 /* WFE */ -#define DISAS_WFE 7 -#define DISAS_HVC 8 -#define DISAS_SMC 9 -#define DISAS_YIELD 10 +#define DISAS_WFE DISAS_TARGET_4 +#define DISAS_HVC DISAS_TARGET_5 +#define DISAS_SMC DISAS_TARGET_6 +#define DISAS_YIELD DISAS_TARGET_7 /* M profile branch which might be an exception return (and so needs * custom end-of-TB code) */ -#define DISAS_BX_EXCRET 11 +#define DISAS_BX_EXCRET DISAS_TARGET_8 /* For instructions which want an immediate exit to the main loop, * as opposed to attempting to use lookup_and_goto_ptr. Unlike * DISAS_UPDATE this doesn't write the PC on exiting the translation * loop so you need to ensure something (gen_a64_set_pc_im or runtime * helper) has done so before we reach return from cpu_tb_exec. */ -#define DISAS_EXIT 12 +#define DISAS_EXIT DISAS_TARGET_9 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } -static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { } diff --git a/target/cris/translate.c b/target/cris/translate.c index 12b96eb68f..38a999e6f1 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "mmu.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "crisv32-decode.h" #include "exec/helper-gen.h" @@ -50,7 +51,11 @@ #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) #define BUG_ON(x) ({if (x) BUG();}) -#define DISAS_SWI 5 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_SWI DISAS_TARGET_3 /* Used by the decoder. */ #define EXTRACT_FIELD(src, start, end) \ diff --git a/target/i386/translate.c b/target/i386/translate.c index 5fdadf98cf..de0c989763 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -31,7 +32,6 @@ #include "trace-tcg.h" #include "exec/log.h" - #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 @@ -95,6 +95,8 @@ static int x86_64_hregs; #endif typedef struct DisasContext { + DisasContextBase base; + /* current insn context */ int override; /* -1 if no override */ int prefix; @@ -102,8 +104,6 @@ typedef struct DisasContext { TCGMemOp dflag; target_ulong pc_start; target_ulong pc; /* pc = eip + cs_base */ - int is_jmp; /* 1 = means jump (stop translation), 2 means CPU - static state change (stop translation) */ /* current block context */ target_ulong cs_base; /* base of CS segment */ int pe; /* protected mode */ @@ -124,12 +124,10 @@ typedef struct DisasContext { int cpl; int iopl; int tf; /* TF cpu flag */ - int singlestep_enabled; /* "hardware" single step enabled */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint64_t flags; /* all execution flags */ - struct TranslationBlock *tb; int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; @@ -1119,7 +1117,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot) static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1134,14 +1132,14 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1154,7 +1152,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -2137,7 +2135,7 @@ static inline int insn_const_size(TCGMemOp ot) static inline bool use_goto_tb(DisasContext *s, target_ulong pc) { #ifndef CONFIG_USER_ONLY - return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) || + return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) || (pc & TARGET_PAGE_MASK) == (s->pc_start & TARGET_PAGE_MASK); #else return true; @@ -2152,7 +2150,8 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); - tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); + tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num); + s->base.is_jmp = DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2173,7 +2172,6 @@ static inline void gen_jcc(DisasContext *s, int b, gen_set_label(l1); gen_goto_tb(s, 1, val); - s->is_jmp = DISAS_TB_JUMP; } else { l1 = gen_new_label(); l2 = gen_new_label(); @@ -2243,12 +2241,14 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) - s->is_jmp = DISAS_TB_JUMP; + if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) { + s->base.is_jmp = DISAS_TOO_MANY; + } } else { gen_op_movl_seg_T0_vm(seg_reg); - if (seg_reg == R_SS) - s->is_jmp = DISAS_TB_JUMP; + if (seg_reg == R_SS) { + s->base.is_jmp = DISAS_TOO_MANY; + } } } @@ -2420,7 +2420,7 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } /* Generate #UD for the current instruction. The assumption here is that @@ -2458,7 +2458,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2466,7 +2466,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2522,10 +2522,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); } - if (s->tb->flags & HF_RF_MASK) { + if (s->base.tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } - if (s->singlestep_enabled) { + if (s->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); @@ -2541,7 +2541,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } static inline void @@ -2580,7 +2580,6 @@ static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) set_cc_op(s, CC_OP_DYNAMIC); if (s->jmp_opt) { gen_goto_tb(s, tb_num, eip); - s->is_jmp = DISAS_TB_JUMP; } else { gen_jmp_im(eip); gen_eob(s); @@ -4416,17 +4415,18 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } } -/* convert one instruction. s->is_jmp is set if the translation must +/* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { + CPUX86State *env = cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start = s->base.pc_next; s->pc_start = s->pc = pc_start; prefixes = 0; @@ -5376,7 +5376,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_movl_seg_T0(s, reg); gen_pop_update(s, ot); /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg == R_SS) { s->tf = 0; @@ -5391,7 +5391,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = gen_pop_T0(s); gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -5442,7 +5442,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_movl_seg_T0(s, reg); /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg == R_SS) { s->tf = 0; @@ -5651,7 +5651,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_movl_seg_T0(s, op); /* then put the data */ gen_op_mov_reg_v(ot, reg, cpu_T1); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6307,7 +6307,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6322,7 +6322,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_outs(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6338,14 +6338,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6359,14 +6359,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6377,14 +6377,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6397,14 +6397,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6943,7 +6943,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7112,11 +7112,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7188,7 +7188,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; } break; case 0x100: @@ -7371,7 +7371,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp = DISAS_TB_JUMP; + s->base.is_jmp = DISAS_NORETURN; break; case 0xd9: /* VMMCALL */ @@ -7571,11 +7571,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7940,24 +7940,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg)); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8378,22 +8378,13 @@ void tcg_x86_init(void) } } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu, + int max_insns) { - CPUX86State *env = cs->env_ptr; - DisasContext dc1, *dc = &dc1; - target_ulong pc_ptr; - uint32_t flags; - target_ulong pc_start; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - pc_start = tb->pc; - cs_base = tb->cs_base; - flags = tb->flags; + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUX86State *env = cpu->env_ptr; + uint32_t flags = dc->base.tb->flags; + target_ulong cs_base = dc->base.tb->cs_base; dc->pe = (flags >> HF_PE_SHIFT) & 1; dc->code32 = (flags >> HF_CS32_SHIFT) & 1; @@ -8404,11 +8395,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled = cs->singlestep_enabled; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->cs_base = cs_base; - dc->tb = tb; dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; @@ -8426,7 +8415,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags = flags; - dc->jmp_opt = !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8438,7 +8427,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) record/replay modes and there will always be an additional step for ecx=0 when icount is enabled. */ - dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt = !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8458,107 +8447,112 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) cpu_ptr1 = tcg_temp_new_ptr(); cpu_cc_srcT = tcg_temp_local_new(); - dc->is_jmp = DISAS_NEXT; - pc_ptr = pc_start; - num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; + return max_insns; +} + +static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + +static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); +} + +static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags = dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + dc->base.is_jmp = DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the generic logic setting tb->size later does the right thing. */ + dc->base.pc_next += 1; + return true; + } else { + return false; } +} - gen_tb_start(tb); - for(;;) { - tcg_gen_insn_start(pc_ptr, dc->cc_op); - num_insns++; - - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, pc_ptr, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, pc_ptr - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - pc_ptr += 1; - goto done_generating; - } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } +static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_next = disas_insn(dc, cpu); - pc_ptr = disas_insn(env, dc, pc_ptr); - /* stop translation if indicated */ - if (dc->is_jmp) - break; + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(pc_ptr - dc->cs_base); - gen_eob(dc); - break; - } + chance to happen */ + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) { /* Do not cross the boundary of the pages in icount mode, it can cause an exception. Do it only when boundary is crossed by the first instruction in the block. If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((pc_ptr & TARGET_PAGE_MASK) - != ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) - || (pc_ptr & ~TARGET_PAGE_MASK) == 0)) { - gen_jmp_im(pc_ptr - dc->cs_base); - gen_eob(dc); - break; - } - /* if too long translation, stop generation too */ - if (tcg_op_buf_full() || - (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || - num_insns >= max_insns) { - gen_jmp_im(pc_ptr - dc->cs_base); - gen_eob(dc); - break; - } - if (singlestep) { - gen_jmp_im(pc_ptr - dc->cs_base); - gen_eob(dc); - break; - } + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) { + dc->base.is_jmp = DISAS_TOO_MANY; } - if (tb->cflags & CF_LAST_IO) - gen_io_end(); -done_generating: - gen_tb_end(tb, num_insns); -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - int disas_flags; - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); + dc->base.pc_next = pc_next; +} + +static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (dc->base.is_jmp == DISAS_TOO_MANY) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); + gen_eob(dc); + } +} + +static void i386_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + int disas_flags = !dc->code32; + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); #ifdef TARGET_X86_64 - if (dc->code64) - disas_flags = 2; - else -#endif - disas_flags = !dc->code32; - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags); - qemu_log("\n"); - qemu_log_unlock(); + if (dc->code64) { + disas_flags = 2; } #endif + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags); +} + +static const TranslatorOps i386_tr_ops = { + .init_disas_context = i386_tr_init_disas_context, + .tb_start = i386_tr_tb_start, + .insn_start = i386_tr_insn_start, + .breakpoint_check = i386_tr_breakpoint_check, + .translate_insn = i386_tr_translate_insn, + .tb_stop = i386_tr_tb_stop, + .disas_log = i386_tr_disas_log, +}; + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; - tb->size = pc_ptr - pc_start; - tb->icount = num_insns; + translator_loop(&i386_tr_ops, &dc.base, cpu, tb); } void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, diff --git a/target/lm32/translate.c b/target/lm32/translate.c index f68f372f15..65bc9c0bf6 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translator.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" @@ -47,6 +48,11 @@ #define MEM_INDEX 0 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index be24355080..d738f32f9c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,6 +25,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -173,7 +174,11 @@ static void do_writebacks(DisasContext *s) } } -#define DISAS_JUMP_NEXT 4 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_JUMP_NEXT DISAS_TARGET_3 #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 83e2ef4960..067b0878d6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -27,6 +27,7 @@ #include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" +#include "exec/translator.h" #include "trace-tcg.h" #include "exec/log.h" @@ -46,6 +47,11 @@ #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv env_debug; static TCGv_env cpu_env; static TCGv cpu_R[32]; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 8b97d6585f..6b0961837d 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" + +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ #define INSTRUCTION_FLG(func, flags) { (func), (flags) } #define INSTRUCTION(func) \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a01413113b..112db1ad0f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -37,6 +38,11 @@ #define LOG_DIS(str, ...) \ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + typedef struct DisasContext { TranslationBlock *tb; target_ulong pc; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4b0db7b7bd..909b12818d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -77,7 +77,8 @@ typedef struct { } u; } DisasCompare; -#define DISAS_EXCP 4 +/* is_jmp field values */ +#define DISAS_EXCP DISAS_TARGET_0 #ifdef DEBUG_INLINE_BRANCHES static uint64_t inline_branch_hit[CC_OP_MAX]; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 8f30cff932..6c094d59d7 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -16,6 +16,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -45,9 +46,13 @@ typedef struct DisasContext { #define IS_USER(s) 1 #endif +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ /* These instructions trap after executing, so defer them until after the conditional executions state has been updated. */ -#define DISAS_SYSCALL 5 +#define DISAS_SYSCALL DISAS_TARGET_3 static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f3f0ff589c..d7bf07e8e6 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -38,6 +38,7 @@ #include "sysemu/sysemu.h" #include "exec/cpu_ldst.h" #include "exec/semihost.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -46,6 +47,9 @@ #include "exec/log.h" +/* is_jmp field values */ +#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */ + typedef struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..b41a248bee 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *)start, (char *)stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5ef1086710..a38be15a39 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -134,4 +134,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *) start, (char *) stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h deleted file mode 100644 index 901bb7575d..0000000000 --- a/tcg/ia64/tcg-target.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net> - * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef IA64_TCG_TARGET_H -#define IA64_TCG_TARGET_H - -#define TCG_TARGET_INSN_UNIT_SIZE 16 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 21 - -typedef struct { - uint64_t lo __attribute__((aligned(16))); - uint64_t hi; -} tcg_insn_unit; - -/* We only map the first 64 registers */ -#define TCG_TARGET_NB_REGS 64 -typedef enum { - TCG_REG_R0 = 0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_R15, - TCG_REG_R16, - TCG_REG_R17, - TCG_REG_R18, - TCG_REG_R19, - TCG_REG_R20, - TCG_REG_R21, - TCG_REG_R22, - TCG_REG_R23, - TCG_REG_R24, - TCG_REG_R25, - TCG_REG_R26, - TCG_REG_R27, - TCG_REG_R28, - TCG_REG_R29, - TCG_REG_R30, - TCG_REG_R31, - TCG_REG_R32, - TCG_REG_R33, - TCG_REG_R34, - TCG_REG_R35, - TCG_REG_R36, - TCG_REG_R37, - TCG_REG_R38, - TCG_REG_R39, - TCG_REG_R40, - TCG_REG_R41, - TCG_REG_R42, - TCG_REG_R43, - TCG_REG_R44, - TCG_REG_R45, - TCG_REG_R46, - TCG_REG_R47, - TCG_REG_R48, - TCG_REG_R49, - TCG_REG_R50, - TCG_REG_R51, - TCG_REG_R52, - TCG_REG_R53, - TCG_REG_R54, - TCG_REG_R55, - TCG_REG_R56, - TCG_REG_R57, - TCG_REG_R58, - TCG_REG_R59, - TCG_REG_R60, - TCG_REG_R61, - TCG_REG_R62, - TCG_REG_R63, - - TCG_AREG0 = TCG_REG_R32, -} TCGReg; - -#define TCG_CT_CONST_ZERO 0x100 -#define TCG_CT_CONST_S22 0x200 - -/* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_R12 -#define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_CALL_STACK_OFFSET 16 - -/* optional instructions */ -#define TCG_TARGET_HAS_div_i32 0 -#define TCG_TARGET_HAS_rem_i32 0 -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 -#define TCG_TARGET_HAS_andc_i32 1 -#define TCG_TARGET_HAS_andc_i64 1 -#define TCG_TARGET_HAS_bswap16_i32 1 -#define TCG_TARGET_HAS_bswap16_i64 1 -#define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_bswap32_i64 1 -#define TCG_TARGET_HAS_bswap64_i64 1 -#define TCG_TARGET_HAS_eqv_i32 1 -#define TCG_TARGET_HAS_eqv_i64 1 -#define TCG_TARGET_HAS_ext8s_i32 1 -#define TCG_TARGET_HAS_ext16s_i32 1 -#define TCG_TARGET_HAS_ext8s_i64 1 -#define TCG_TARGET_HAS_ext16s_i64 1 -#define TCG_TARGET_HAS_ext32s_i64 1 -#define TCG_TARGET_HAS_ext8u_i32 1 -#define TCG_TARGET_HAS_ext16u_i32 1 -#define TCG_TARGET_HAS_ext8u_i64 1 -#define TCG_TARGET_HAS_ext16u_i64 1 -#define TCG_TARGET_HAS_ext32u_i64 1 -#define TCG_TARGET_HAS_nand_i32 1 -#define TCG_TARGET_HAS_nand_i64 1 -#define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_ctpop_i64 0 -#define TCG_TARGET_HAS_nor_i64 1 -#define TCG_TARGET_HAS_orc_i32 1 -#define TCG_TARGET_HAS_orc_i64 1 -#define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_movcond_i32 1 -#define TCG_TARGET_HAS_movcond_i64 1 -#define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_extract_i32 0 -#define TCG_TARGET_HAS_extract_i64 0 -#define TCG_TARGET_HAS_sextract_i32 0 -#define TCG_TARGET_HAS_sextract_i64 0 -#define TCG_TARGET_HAS_add2_i32 0 -#define TCG_TARGET_HAS_add2_i64 0 -#define TCG_TARGET_HAS_sub2_i32 0 -#define TCG_TARGET_HAS_sub2_i64 0 -#define TCG_TARGET_HAS_mulu2_i32 0 -#define TCG_TARGET_HAS_mulu2_i64 0 -#define TCG_TARGET_HAS_muls2_i32 0 -#define TCG_TARGET_HAS_muls2_i64 0 -#define TCG_TARGET_HAS_muluh_i32 0 -#define TCG_TARGET_HAS_muluh_i64 0 -#define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_mulsh_i64 0 -#define TCG_TARGET_HAS_extrl_i64_i32 0 -#define TCG_TARGET_HAS_extrh_i64_i32 0 -#define TCG_TARGET_HAS_goto_ptr 0 - -#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16) -#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16) - -/* optional instructions automatically implemented */ -#define TCG_TARGET_HAS_neg_i32 0 /* sub r1, r0, r3 */ -#define TCG_TARGET_HAS_neg_i64 0 /* sub r1, r0, r3 */ -#define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */ -#define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */ - -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - start = start & ~(32UL - 1UL); - stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL); - - for (; start < stop; start += 32UL) { - asm volatile ("fc.i %0" :: "r" (start)); - } - asm volatile (";;sync.i;;srlz.i;;"); -} - -#endif diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c deleted file mode 100644 index bf9a97d75c..0000000000 --- a/tcg/ia64/tcg-target.inc.c +++ /dev/null @@ -1,2482 +0,0 @@ -/* - * Tiny Code Generator for QEMU - * - * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net> - * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* - * Register definitions - */ - -#ifdef CONFIG_DEBUG_TCG -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", - "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", - "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", - "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", - "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", -}; -#endif - -#ifndef CONFIG_SOFTMMU -#define TCG_GUEST_BASE_REG TCG_REG_R55 -#endif - -/* Branch registers */ -enum { - TCG_REG_B0 = 0, - TCG_REG_B1, - TCG_REG_B2, - TCG_REG_B3, - TCG_REG_B4, - TCG_REG_B5, - TCG_REG_B6, - TCG_REG_B7, -}; - -/* Floating point registers */ -enum { - TCG_REG_F0 = 0, - TCG_REG_F1, - TCG_REG_F2, - TCG_REG_F3, - TCG_REG_F4, - TCG_REG_F5, - TCG_REG_F6, - TCG_REG_F7, - TCG_REG_F8, - TCG_REG_F9, - TCG_REG_F10, - TCG_REG_F11, - TCG_REG_F12, - TCG_REG_F13, - TCG_REG_F14, - TCG_REG_F15, -}; - -/* Predicate registers */ -enum { - TCG_REG_P0 = 0, - TCG_REG_P1, - TCG_REG_P2, - TCG_REG_P3, - TCG_REG_P4, - TCG_REG_P5, - TCG_REG_P6, - TCG_REG_P7, - TCG_REG_P8, - TCG_REG_P9, - TCG_REG_P10, - TCG_REG_P11, - TCG_REG_P12, - TCG_REG_P13, - TCG_REG_P14, - TCG_REG_P15, -}; - -/* Application registers */ -enum { - TCG_REG_PFS = 64, -}; - -static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R35, - TCG_REG_R36, - TCG_REG_R37, - TCG_REG_R38, - TCG_REG_R39, - TCG_REG_R40, - TCG_REG_R41, - TCG_REG_R42, - TCG_REG_R43, - TCG_REG_R44, - TCG_REG_R45, - TCG_REG_R46, - TCG_REG_R47, - TCG_REG_R48, - TCG_REG_R49, - TCG_REG_R50, - TCG_REG_R51, - TCG_REG_R52, - TCG_REG_R53, - TCG_REG_R54, - TCG_REG_R55, - TCG_REG_R14, - TCG_REG_R15, - TCG_REG_R16, - TCG_REG_R17, - TCG_REG_R18, - TCG_REG_R19, - TCG_REG_R20, - TCG_REG_R21, - TCG_REG_R22, - TCG_REG_R23, - TCG_REG_R24, - TCG_REG_R25, - TCG_REG_R26, - TCG_REG_R27, - TCG_REG_R28, - TCG_REG_R29, - TCG_REG_R30, - TCG_REG_R31, - TCG_REG_R56, - TCG_REG_R57, - TCG_REG_R58, - TCG_REG_R59, - TCG_REG_R60, - TCG_REG_R61, - TCG_REG_R62, - TCG_REG_R63, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11 -}; - -static const int tcg_target_call_iarg_regs[8] = { - TCG_REG_R56, - TCG_REG_R57, - TCG_REG_R58, - TCG_REG_R59, - TCG_REG_R60, - TCG_REG_R61, - TCG_REG_R62, - TCG_REG_R63, -}; - -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R8 -}; - -/* - * opcode formation - */ - -/* bundle templates: stops (double bar in the IA64 manual) are marked with - an uppercase letter. */ -enum { - mii = 0x00, - miI = 0x01, - mIi = 0x02, - mII = 0x03, - mlx = 0x04, - mLX = 0x05, - mmi = 0x08, - mmI = 0x09, - Mmi = 0x0a, - MmI = 0x0b, - mfi = 0x0c, - mfI = 0x0d, - mmf = 0x0e, - mmF = 0x0f, - mib = 0x10, - miB = 0x11, - mbb = 0x12, - mbB = 0x13, - bbb = 0x16, - bbB = 0x17, - mmb = 0x18, - mmB = 0x19, - mfb = 0x1c, - mfB = 0x1d, -}; - -enum { - OPC_ADD_A1 = 0x10000000000ull, - OPC_AND_A1 = 0x10060000000ull, - OPC_AND_A3 = 0x10160000000ull, - OPC_ANDCM_A1 = 0x10068000000ull, - OPC_ANDCM_A3 = 0x10168000000ull, - OPC_ADDS_A4 = 0x10800000000ull, - OPC_ADDL_A5 = 0x12000000000ull, - OPC_ALLOC_M34 = 0x02c00000000ull, - OPC_BR_DPTK_FEW_B1 = 0x08400000000ull, - OPC_BR_SPTK_MANY_B1 = 0x08000001000ull, - OPC_BR_CALL_SPNT_FEW_B3 = 0x0a200000000ull, - OPC_BR_SPTK_MANY_B4 = 0x00100001000ull, - OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull, - OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull, - OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull, - OPC_BRL_CALL_SPNT_MANY_X4 = 0x1a200001000ull, - OPC_BRL_CALL_SPTK_MANY_X4 = 0x1a000001000ull, - OPC_CMP_LT_A6 = 0x18000000000ull, - OPC_CMP_LTU_A6 = 0x1a000000000ull, - OPC_CMP_EQ_A6 = 0x1c000000000ull, - OPC_CMP4_LT_A6 = 0x18400000000ull, - OPC_CMP4_LTU_A6 = 0x1a400000000ull, - OPC_CMP4_EQ_A6 = 0x1c400000000ull, - OPC_DEP_I14 = 0x0ae00000000ull, - OPC_DEP_I15 = 0x08000000000ull, - OPC_DEP_Z_I12 = 0x0a600000000ull, - OPC_EXTR_I11 = 0x0a400002000ull, - OPC_EXTR_U_I11 = 0x0a400000000ull, - OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull, - OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull, - OPC_FCVT_XF_F11 = 0x000e0000000ull, - OPC_FMA_S1_F1 = 0x10400000000ull, - OPC_FNMA_S1_F1 = 0x18400000000ull, - OPC_FRCPA_S1_F6 = 0x00600000000ull, - OPC_GETF_SIG_M19 = 0x08708000000ull, - OPC_LD1_M1 = 0x08000000000ull, - OPC_LD1_M3 = 0x0a000000000ull, - OPC_LD2_M1 = 0x08040000000ull, - OPC_LD2_M3 = 0x0a040000000ull, - OPC_LD4_M1 = 0x08080000000ull, - OPC_LD4_M3 = 0x0a080000000ull, - OPC_LD8_M1 = 0x080c0000000ull, - OPC_LD8_M3 = 0x0a0c0000000ull, - OPC_MF_M24 = 0x00110000000ull, - OPC_MUX1_I3 = 0x0eca0000000ull, - OPC_NOP_B9 = 0x04008000000ull, - OPC_NOP_F16 = 0x00008000000ull, - OPC_NOP_I18 = 0x00008000000ull, - OPC_NOP_M48 = 0x00008000000ull, - OPC_MOV_I21 = 0x00e00100000ull, - OPC_MOV_RET_I21 = 0x00e00500000ull, - OPC_MOV_I22 = 0x00188000000ull, - OPC_MOV_I_I26 = 0x00150000000ull, - OPC_MOVL_X2 = 0x0c000000000ull, - OPC_OR_A1 = 0x10070000000ull, - OPC_OR_A3 = 0x10170000000ull, - OPC_SETF_EXP_M18 = 0x0c748000000ull, - OPC_SETF_SIG_M18 = 0x0c708000000ull, - OPC_SHL_I7 = 0x0f240000000ull, - OPC_SHR_I5 = 0x0f220000000ull, - OPC_SHR_U_I5 = 0x0f200000000ull, - OPC_SHRP_I10 = 0x0ac00000000ull, - OPC_SXT1_I29 = 0x000a0000000ull, - OPC_SXT2_I29 = 0x000a8000000ull, - OPC_SXT4_I29 = 0x000b0000000ull, - OPC_ST1_M4 = 0x08c00000000ull, - OPC_ST2_M4 = 0x08c40000000ull, - OPC_ST4_M4 = 0x08c80000000ull, - OPC_ST8_M4 = 0x08cc0000000ull, - OPC_SUB_A1 = 0x10028000000ull, - OPC_SUB_A3 = 0x10128000000ull, - OPC_UNPACK4_L_I2 = 0x0f860000000ull, - OPC_XMA_L_F2 = 0x1d000000000ull, - OPC_XOR_A1 = 0x10078000000ull, - OPC_XOR_A3 = 0x10178000000ull, - OPC_ZXT1_I29 = 0x00080000000ull, - OPC_ZXT2_I29 = 0x00088000000ull, - OPC_ZXT4_I29 = 0x00090000000ull, - - INSN_NOP_M = OPC_NOP_M48, /* nop.m 0 */ - INSN_NOP_I = OPC_NOP_I18, /* nop.i 0 */ -}; - -static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1, - int r2, int r3) -{ - return opc - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1, - uint64_t imm, int r3) -{ - return opc - | ((imm & 0x80) << 29) /* s */ - | ((imm & 0x7f) << 13) /* imm7b */ - | ((r3 & 0x7f) << 20) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1, - uint64_t imm, int r3) -{ - return opc - | ((imm & 0x2000) << 23) /* s */ - | ((imm & 0x1f80) << 20) /* imm6d */ - | ((imm & 0x007f) << 13) /* imm7b */ - | ((r3 & 0x7f) << 20) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1, - uint64_t imm, int r3) -{ - return opc - | ((imm & 0x200000) << 15) /* s */ - | ((imm & 0x1f0000) << 6) /* imm5c */ - | ((imm & 0x00ff80) << 20) /* imm9d */ - | ((imm & 0x00007f) << 13) /* imm7b */ - | ((r3 & 0x03) << 20) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1, - int p2, int r2, int r3) -{ - return opc - | ((p2 & 0x3f) << 27) - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | ((p1 & 0x3f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm) -{ - return opc - | ((imm & 0x100000) << 16) /* s */ - | ((imm & 0x0fffff) << 13) /* imm20b */ - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_b3(int qp, uint64_t opc, int b1, uint64_t imm) -{ - return opc - | ((imm & 0x100000) << 16) /* s */ - | ((imm & 0x0fffff) << 13) /* imm20b */ - | ((b1 & 0x7) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2) -{ - return opc - | ((b2 & 0x7) << 13) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2) -{ - return opc - | ((b2 & 0x7) << 13) - | ((b1 & 0x7) << 6) - | (qp & 0x3f); -} - - -static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm) -{ - return opc - | ((imm & 0x100000) << 16) /* i */ - | ((imm & 0x0fffff) << 6) /* imm20a */ - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1, - int f3, int f4, int f2) -{ - return opc - | ((f4 & 0x7f) << 27) - | ((f3 & 0x7f) << 20) - | ((f2 & 0x7f) << 13) - | ((f1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1, - int f3, int f4, int f2) -{ - return opc - | ((f4 & 0x7f) << 27) - | ((f3 & 0x7f) << 20) - | ((f2 & 0x7f) << 13) - | ((f1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1, - int p2, int f2, int f3) -{ - return opc - | ((p2 & 0x3f) << 27) - | ((f3 & 0x7f) << 20) - | ((f2 & 0x7f) << 13) - | ((f1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2) -{ - return opc - | ((f2 & 0x7f) << 13) - | ((f1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2) -{ - return opc - | ((f2 & 0x7f) << 13) - | ((f1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm) -{ - return opc - | ((imm & 0x100000) << 16) /* i */ - | ((imm & 0x0fffff) << 6) /* imm20a */ - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1, - int r2, int r3) -{ - return opc - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1, - int r2, int mbtype) -{ - return opc - | ((mbtype & 0x0f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1, - int r3, int r2) -{ - return opc - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1, - int r2, int r3) -{ - return opc - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1, - int r2, int r3, uint64_t count) -{ - return opc - | ((count & 0x3f) << 27) - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1, - int r3, uint64_t pos, uint64_t len) -{ - return opc - | ((len & 0x3f) << 27) - | ((r3 & 0x7f) << 20) - | ((pos & 0x3f) << 14) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1, - int r2, uint64_t pos, uint64_t len) -{ - return opc - | ((len & 0x3f) << 27) - | ((pos & 0x3f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm, - int r3, uint64_t pos, uint64_t len) -{ - return opc - | ((imm & 0x01) << 36) - | ((len & 0x3f) << 27) - | ((r3 & 0x7f) << 20) - | ((pos & 0x3f) << 14) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2, - int r3, uint64_t pos, uint64_t len) -{ - return opc - | ((pos & 0x3f) << 31) - | ((len & 0x0f) << 27) - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm) -{ - return opc - | ((imm & 0x100000) << 16) /* i */ - | ((imm & 0x0fffff) << 6) /* imm20a */ - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1, - int r2, uint64_t imm) -{ - return opc - | ((imm & 0x1ff) << 24) - | ((r2 & 0x7f) << 13) - | ((b1 & 0x7) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2) -{ - return opc - | ((b2 & 0x7) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2) -{ - return opc - | ((ar3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3) -{ - return opc - | ((r3 & 0x7f) << 20) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_l2(uint64_t imm) -{ - return (imm & 0x7fffffffffc00000ull) >> 22; -} - -static inline uint64_t tcg_opc_l3(uint64_t imm) -{ - return (imm & 0x07fffffffff00000ull) >> 18; -} - -#define tcg_opc_l4 tcg_opc_l3 - -static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3) -{ - return opc - | ((r3 & 0x7f) << 20) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1, - int r3, uint64_t imm) -{ - return opc - | ((imm & 0x100) << 28) /* s */ - | ((imm & 0x080) << 20) /* i */ - | ((imm & 0x07f) << 13) /* imm7b */ - | ((r3 & 0x7f) << 20) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3) -{ - return opc - | ((r3 & 0x7f) << 20) - | ((r2 & 0x7f) << 13) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2) -{ - return opc - | ((r2 & 0x7f) << 13) - | ((f1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2) -{ - return opc - | ((f2 & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1, - int sof, int sol, int sor) -{ - return opc - | ((sor & 0x0f) << 27) - | ((sol & 0x7f) << 20) - | ((sof & 0x7f) << 13) - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm) -{ - return opc - | ((imm & 0x100000) << 16) /* i */ - | ((imm & 0x0fffff) << 6) /* imm20a */ - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_x2(int qp, uint64_t opc, - int r1, uint64_t imm) -{ - return opc - | ((imm & 0x8000000000000000ull) >> 27) /* i */ - | (imm & 0x0000000000200000ull) /* ic */ - | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */ - | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */ - | ((imm & 0x000000000000007full) << 13) /* imm7b */ - | ((r1 & 0x7f) << 6) - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm) -{ - return opc - | ((imm & 0x0800000000000000ull) >> 23) /* i */ - | ((imm & 0x00000000000fffffull) << 13) /* imm20b */ - | (qp & 0x3f); -} - -static inline uint64_t tcg_opc_x4(int qp, uint64_t opc, int b1, uint64_t imm) -{ - return opc - | ((imm & 0x0800000000000000ull) >> 23) /* i */ - | ((imm & 0x00000000000fffffull) << 13) /* imm20b */ - | ((b1 & 0x7) << 6) - | (qp & 0x3f); -} - - -/* - * Relocations - Note that we never encode branches elsewhere than slot 2. - */ - -static void reloc_pcrel21b_slot2(tcg_insn_unit *pc, tcg_insn_unit *target) -{ - uint64_t imm = target - pc; - - pc->hi = (pc->hi & 0xf700000fffffffffull) - | ((imm & 0x100000) << 39) /* s */ - | ((imm & 0x0fffff) << 36); /* imm20b */ -} - -static uint64_t get_reloc_pcrel21b_slot2(tcg_insn_unit *pc) -{ - int64_t high = pc->hi; - - return ((high >> 39) & 0x100000) + /* s */ - ((high >> 36) & 0x0fffff); /* imm20b */ -} - -static void patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_debug_assert(addend == 0); - tcg_debug_assert(type == R_IA64_PCREL21B); - reloc_pcrel21b_slot2(code_ptr, (tcg_insn_unit *)value); -} - -/* - * Constraints - */ - -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch(*ct_str++) { - case 'r': - ct->ct |= TCG_CT_REG; - tcg_regset_set(ct->u.regs, 0xffffffffffffffffull); - break; - case 'I': - ct->ct |= TCG_CT_CONST_S22; - break; - case 'S': - ct->ct |= TCG_CT_REG; - tcg_regset_set(ct->u.regs, 0xffffffffffffffffull); -#if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R58); -#endif - break; - case 'Z': - /* We are cheating a bit here, using the fact that the register - r0 is also the register number 0. Hence there is no need - to check for const_args in each instruction. */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - -/* test if a constant matches the constraint */ -static inline int tcg_target_const_match(tcg_target_long val, TCGType type, - const TCGArgConstraint *arg_ct) -{ - int ct; - ct = arg_ct->ct; - if (ct & TCG_CT_CONST) - return 1; - else if ((ct & TCG_CT_CONST_ZERO) && val == 0) - return 1; - else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10) - return 1; - else - return 0; -} - -/* - * Code generation - */ - -static tcg_insn_unit *tb_ret_addr; - -static inline void tcg_out_bundle(TCGContext *s, int template, - uint64_t slot0, uint64_t slot1, - uint64_t slot2) -{ - template &= 0x1f; /* 5 bits */ - slot0 &= 0x1ffffffffffull; /* 41 bits */ - slot1 &= 0x1ffffffffffull; /* 41 bits */ - slot2 &= 0x1ffffffffffull; /* 41 bits */ - - *s->code_ptr++ = (tcg_insn_unit){ - (slot1 << 46) | (slot0 << 5) | template, - (slot2 << 23) | (slot1 >> 18) - }; -} - -static inline uint64_t tcg_opc_mov_a(int qp, TCGReg dst, TCGReg src) -{ - return tcg_opc_a4(qp, OPC_ADDS_A4, dst, 0, src); -} - -static inline void tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) -{ - tcg_out_bundle(s, mmI, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_mov_a(TCG_REG_P0, ret, arg)); -} - -static inline uint64_t tcg_opc_movi_a(int qp, TCGReg dst, int64_t src) -{ - tcg_debug_assert(src == sextract64(src, 0, 22)); - return tcg_opc_a5(qp, OPC_ADDL_A5, dst, src, TCG_REG_R0); -} - -static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg reg, tcg_target_long arg) -{ - tcg_out_bundle(s, mLX, - INSN_NOP_M, - tcg_opc_l2 (arg), - tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg)); -} - -static void tcg_out_br(TCGContext *s, TCGLabel *l) -{ - uint64_t imm; - - /* We pay attention here to not modify the branch target by reading - the existing value and using it again. This ensure that caches and - memory are kept coherent during retranslation. */ - if (l->has_value) { - imm = l->u.value_ptr - s->code_ptr; - } else { - imm = get_reloc_pcrel21b_slot2(s->code_ptr); - tcg_out_reloc(s, s->code_ptr, R_IA64_PCREL21B, l, 0); - } - - tcg_out_bundle(s, mmB, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_b1(TCG_REG_P0, OPC_BR_SPTK_MANY_B1, imm)); -} - -static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *desc) -{ - uintptr_t func = desc->lo, gp = desc->hi, disp; - - /* Look through the function descriptor. */ - tcg_out_bundle(s, mlx, - INSN_NOP_M, - tcg_opc_l2 (gp), - tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, gp)); - disp = (tcg_insn_unit *)func - s->code_ptr; - tcg_out_bundle(s, mLX, - INSN_NOP_M, - tcg_opc_l4 (disp), - tcg_opc_x4 (TCG_REG_P0, OPC_BRL_CALL_SPTK_MANY_X4, - TCG_REG_B0, disp)); -} - -static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg) -{ - uint64_t imm, opc1; - - /* At least arg == 0 is a common operation. */ - if (arg == sextract64(arg, 0, 22)) { - opc1 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R8, arg); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg); - opc1 = INSN_NOP_M; - } - - imm = tb_ret_addr - s->code_ptr; - - tcg_out_bundle(s, mLX, - opc1, - tcg_opc_l3 (imm), - tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm)); -} - -static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg) -{ - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - tcg_abort(); - } else { - /* indirect jump method */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, - (tcg_target_long)(s->tb_jmp_target_addr + arg)); - tcg_out_bundle(s, MmI, - tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, - TCG_REG_R2, TCG_REG_R2), - INSN_NOP_M, - tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, - TCG_REG_R2, 0)); - tcg_out_bundle(s, mmB, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, - TCG_REG_B6)); - } - s->tb_jmp_reset_offset[arg] = tcg_current_code_size(s); -} - -static inline void tcg_out_jmp(TCGContext *s, TCGArg addr) -{ - tcg_out_bundle(s, mmI, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0)); - tcg_out_bundle(s, mmB, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); -} - -static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, - TCGArg arg1, tcg_target_long arg2) -{ - if (arg2 == ((int16_t)arg2 >> 2) << 2) { - tcg_out_bundle(s, MmI, - tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, - TCG_REG_R2, arg2, arg1), - tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), - INSN_NOP_I); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); - tcg_out_bundle(s, MmI, - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, - TCG_REG_R2, TCG_REG_R2, arg1), - tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), - INSN_NOP_I); - } -} - -static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg, - TCGArg arg1, tcg_target_long arg2) -{ - if (arg2 == ((int16_t)arg2 >> 2) << 2) { - tcg_out_bundle(s, MmI, - tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, - TCG_REG_R2, arg2, arg1), - tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), - INSN_NOP_I); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2); - tcg_out_bundle(s, MmI, - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, - TCG_REG_R2, TCG_REG_R2, arg1), - tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2), - INSN_NOP_I); - } -} - -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - if (type == TCG_TYPE_I32) { - tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2); - } else { - tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2); - } -} - -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) -{ - if (type == TCG_TYPE_I32) { - tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2); - } else { - tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2); - } -} - -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) -{ - if (val == 0) { - tcg_out_st(s, type, TCG_REG_R0, base, ofs); - return true; - } - return false; -} - -static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, uint64_t opc_a3, - TCGReg ret, TCGArg arg1, int const_arg1, - TCGArg arg2, int const_arg2) -{ - uint64_t opc1 = 0, opc2 = 0, opc3 = 0; - - if (const_arg2 && arg2 != 0) { - opc2 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R3, arg2); - arg2 = TCG_REG_R3; - } - if (const_arg1 && arg1 != 0) { - if (opc_a3 && arg1 == (int8_t)arg1) { - opc3 = tcg_opc_a3(TCG_REG_P0, opc_a3, ret, arg1, arg2); - } else { - opc1 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R2, arg1); - arg1 = TCG_REG_R2; - } - } - if (opc3 == 0) { - opc3 = tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2); - } - - tcg_out_bundle(s, (opc1 || opc2 ? mII : miI), - opc1 ? opc1 : INSN_NOP_M, - opc2 ? opc2 : INSN_NOP_I, - opc3); -} - -static inline void tcg_out_add(TCGContext *s, TCGReg ret, TCGReg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2 && arg2 == sextract64(arg2, 0, 14)) { - tcg_out_bundle(s, mmI, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, arg2, arg1)); - } else { - tcg_out_alu(s, OPC_ADD_A1, 0, ret, arg1, 0, arg2, const_arg2); - } -} - -static inline void tcg_out_sub(TCGContext *s, TCGReg ret, TCGArg arg1, - int const_arg1, TCGArg arg2, int const_arg2) -{ - if (!const_arg1 && const_arg2 && -arg2 == sextract64(-arg2, 0, 14)) { - tcg_out_bundle(s, mmI, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, -arg2, arg1)); - } else { - tcg_out_alu(s, OPC_SUB_A1, OPC_SUB_A3, ret, - arg1, const_arg1, arg2, const_arg2); - } -} - -static inline void tcg_out_eqv(TCGContext *s, TCGArg ret, - TCGArg arg1, int const_arg1, - TCGArg arg2, int const_arg2) -{ - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2), - tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); -} - -static inline void tcg_out_nand(TCGContext *s, TCGArg ret, - TCGArg arg1, int const_arg1, - TCGArg arg2, int const_arg2) -{ - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2), - tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); -} - -static inline void tcg_out_nor(TCGContext *s, TCGArg ret, - TCGArg arg1, int const_arg1, - TCGArg arg2, int const_arg2) -{ - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2), - tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret)); -} - -static inline void tcg_out_orc(TCGContext *s, TCGArg ret, - TCGArg arg1, int const_arg1, - TCGArg arg2, int const_arg2) -{ - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2), - tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2)); -} - -static inline void tcg_out_mul(TCGContext *s, TCGArg ret, - TCGArg arg1, TCGArg arg2) -{ - tcg_out_bundle(s, mmI, - tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1), - tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2), - INSN_NOP_I); - tcg_out_bundle(s, mmF, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6, - TCG_REG_F7, TCG_REG_F0)); - tcg_out_bundle(s, miI, - tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6), - INSN_NOP_I, - INSN_NOP_I); -} - -static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, - ret, arg1, arg2, 31 - arg2)); - } else { - tcg_out_bundle(s, mII, - tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, - TCG_REG_R3, 0x1f, arg2), - tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1), - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, - TCG_REG_R2, TCG_REG_R3)); - } -} - -static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11, - ret, arg1, arg2, 63 - arg2)); - } else { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2)); - } -} - -static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, - arg1, 63 - arg2, 31 - arg2)); - } else { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2, - 0x1f, arg2), - tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, - arg1, TCG_REG_R2)); - } -} - -static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, - arg1, 63 - arg2, 63 - arg2)); - } else { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret, - arg1, arg2)); - } -} - -static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, - arg1, arg2, 31 - arg2)); - } else { - tcg_out_bundle(s, mII, - tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, - 0x1f, arg2), - tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1), - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, - TCG_REG_R2, TCG_REG_R3)); - } -} - -static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, - arg1, arg2, 63 - arg2)); - } else { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, - arg1, arg2)); - } -} - -static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, - TCG_REG_R2, arg1, arg1), - tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, - TCG_REG_R2, 32 - arg2, 31)); - } else { - tcg_out_bundle(s, miI, - INSN_NOP_M, - tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, - TCG_REG_R2, arg1, arg1), - tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, - 0x1f, arg2)); - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3, - 0x20, TCG_REG_R3), - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, - TCG_REG_R2, TCG_REG_R3)); - } -} - -static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, - arg1, 0x40 - arg2)); - } else { - tcg_out_bundle(s, mII, - tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, - 0x40, arg2), - tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3, - arg1, arg2), - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2, - arg1, TCG_REG_R2)); - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, - TCG_REG_R2, TCG_REG_R3)); - } -} - -static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, - TCG_REG_R2, arg1, arg1), - tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret, - TCG_REG_R2, arg2, 31)); - } else { - tcg_out_bundle(s, mII, - tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3, - 0x1f, arg2), - tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2, - TCG_REG_R2, arg1, arg1), - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret, - TCG_REG_R2, TCG_REG_R3)); - } -} - -static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1, - TCGArg arg2, int const_arg2) -{ - if (const_arg2) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1, - arg1, arg2)); - } else { - tcg_out_bundle(s, mII, - tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2, - 0x40, arg2), - tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3, - arg1, arg2), - tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2, - arg1, TCG_REG_R2)); - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, - TCG_REG_R2, TCG_REG_R3)); - } -} - -static const uint64_t opc_ext_i29[8] = { - OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, - OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 -}; - -static inline uint64_t tcg_opc_ext_i(int qp, TCGMemOp opc, TCGReg d, TCGReg s) -{ - if ((opc & MO_SIZE) == MO_64) { - return tcg_opc_mov_a(qp, d, s); - } else { - return tcg_opc_i29(qp, opc_ext_i29[opc & MO_SSIZE], d, s); - } -} - -static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29, - TCGArg ret, TCGArg arg) -{ - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg)); -} - -static inline uint64_t tcg_opc_bswap64_i(int qp, TCGReg d, TCGReg s) -{ - return tcg_opc_i3(qp, OPC_MUX1_I3, d, s, 0xb); -} - -static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg) -{ - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15), - tcg_opc_bswap64_i(TCG_REG_P0, ret, ret)); -} - -static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg) -{ - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31), - tcg_opc_bswap64_i(TCG_REG_P0, ret, ret)); -} - -static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg) -{ - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_bswap64_i(TCG_REG_P0, ret, arg)); -} - -static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1, - TCGArg a2, int const_a2, int pos, int len) -{ - uint64_t i1 = 0, i2 = 0; - int cpos = 63 - pos, lm1 = len - 1; - - if (const_a2) { - /* Truncate the value of a constant a2 to the width of the field. */ - int mask = (1u << len) - 1; - a2 &= mask; - - if (a2 == 0 || a2 == mask) { - /* 1-bit signed constant inserted into register. */ - i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1); - } else { - /* Otherwise, load any constant into a temporary. Do this into - the first I slot to help out with cross-unit delays. */ - i1 = tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R2, a2); - a2 = TCG_REG_R2; - } - } - if (i2 == 0) { - i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1); - } - tcg_out_bundle(s, (i1 ? mII : miI), - INSN_NOP_M, - i1 ? i1 : INSN_NOP_I, - i2); -} - -static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1, - TCGArg arg2, int cmp4) -{ - uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6; - - if (cmp4) { - opc_eq_a6 = OPC_CMP4_EQ_A6; - opc_lt_a6 = OPC_CMP4_LT_A6; - opc_ltu_a6 = OPC_CMP4_LTU_A6; - } else { - opc_eq_a6 = OPC_CMP_EQ_A6; - opc_lt_a6 = OPC_CMP_LT_A6; - opc_ltu_a6 = OPC_CMP_LTU_A6; - } - - switch (cond) { - case TCG_COND_EQ: - return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); - case TCG_COND_NE: - return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); - case TCG_COND_LT: - return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); - case TCG_COND_LTU: - return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2); - case TCG_COND_GE: - return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); - case TCG_COND_GEU: - return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2); - case TCG_COND_LE: - return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1); - case TCG_COND_LEU: - return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1); - case TCG_COND_GT: - return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1); - case TCG_COND_GTU: - return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1); - default: - tcg_abort(); - break; - } -} - -static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, - TCGReg arg2, TCGLabel *l, int cmp4) -{ - uint64_t imm; - - /* We pay attention here to not modify the branch target by reading - the existing value and using it again. This ensure that caches and - memory are kept coherent during retranslation. */ - if (l->has_value) { - imm = l->u.value_ptr - s->code_ptr; - } else { - imm = get_reloc_pcrel21b_slot2(s->code_ptr); - tcg_out_reloc(s, s->code_ptr, R_IA64_PCREL21B, l, 0); - } - - tcg_out_bundle(s, miB, - INSN_NOP_M, - tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), - tcg_opc_b1(TCG_REG_P6, OPC_BR_DPTK_FEW_B1, imm)); -} - -static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret, - TCGArg arg1, TCGArg arg2, int cmp4) -{ - tcg_out_bundle(s, MmI, - tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4), - tcg_opc_movi_a(TCG_REG_P6, ret, 1), - tcg_opc_movi_a(TCG_REG_P7, ret, 0)); -} - -static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret, - TCGArg c1, TCGArg c2, - TCGArg v1, int const_v1, - TCGArg v2, int const_v2, int cmp4) -{ - uint64_t opc1, opc2; - - if (const_v1) { - opc1 = tcg_opc_movi_a(TCG_REG_P6, ret, v1); - } else if (ret == v1) { - opc1 = INSN_NOP_M; - } else { - opc1 = tcg_opc_mov_a(TCG_REG_P6, ret, v1); - } - if (const_v2) { - opc2 = tcg_opc_movi_a(TCG_REG_P7, ret, v2); - } else if (ret == v2) { - opc2 = INSN_NOP_I; - } else { - opc2 = tcg_opc_mov_a(TCG_REG_P7, ret, v2); - } - - tcg_out_bundle(s, MmI, - tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4), - opc1, - opc2); -} - -#if defined(CONFIG_SOFTMMU) -/* We're expecting to use an signed 22-bit immediate add. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) - > 0x1fffff) - -/* Load and compare a TLB entry, and return the result in (p6, p7). - R2 is loaded with the addend TLB entry. - R57 is loaded with the address, zero extented on 32-bit targets. - R1, R3 are clobbered, leaving R56 free for... - BSWAP_1, BSWAP_2 and I-slot insns for swapping data for store. */ -static inline void tcg_out_qemu_tlb(TCGContext *s, TCGReg addr_reg, - TCGMemOp opc, int off_rw, int off_add, - uint64_t bswap1, uint64_t bswap2) -{ - unsigned s_bits = opc & MO_SIZE; - unsigned a_bits = get_alignment_bits(opc); - - /* We don't support unaligned accesses, but overalignment is easy. */ - if (a_bits < s_bits) { - a_bits = s_bits; - } - - /* - .mii - mov r2 = off_rw - extr.u r3 = addr_reg, ... # extract tlb page - zxt4 r57 = addr_reg # or mov for 64-bit guest - ;; - .mii - addl r2 = r2, areg0 - shl r3 = r3, cteb # via dep.z - dep r1 = 0, r57, ... # zero page ofs, keep align - ;; - .mmi - add r2 = r2, r3 - ;; - ld4 r3 = [r2], off_add-off_rw # or ld8 for 64-bit guest - nop - ;; - .mmi - nop - cmp.eq p6, p7 = r3, r58 - nop - ;; - */ - tcg_out_bundle(s, miI, - tcg_opc_movi_a(TCG_REG_P0, TCG_REG_R2, off_rw), - tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R3, - addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1), - tcg_opc_ext_i(TCG_REG_P0, - TARGET_LONG_BITS == 32 ? MO_UL : MO_Q, - TCG_REG_R57, addr_reg)); - tcg_out_bundle(s, miI, - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, - TCG_REG_R2, TCG_AREG0), - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R3, - TCG_REG_R3, 63 - CPU_TLB_ENTRY_BITS, - 63 - CPU_TLB_ENTRY_BITS), - tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R1, 0, - TCG_REG_R57, 63 - a_bits, - TARGET_PAGE_BITS - a_bits - 1)); - tcg_out_bundle(s, MmI, - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, - TCG_REG_R2, TCG_REG_R2, TCG_REG_R3), - tcg_opc_m3 (TCG_REG_P0, - (TARGET_LONG_BITS == 32 - ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R3, - TCG_REG_R2, off_add - off_rw), - bswap1); - tcg_out_bundle(s, mmI, - tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, TCG_REG_R2), - tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6, - TCG_REG_P7, TCG_REG_R1, TCG_REG_R3), - bswap2); -} - -typedef struct TCGLabelQemuLdst { - bool is_ld; - TCGMemOp size; - tcg_insn_unit *label_ptr; /* label pointers to be updated */ - struct TCGLabelQemuLdst *next; -} TCGLabelQemuLdst; - -typedef struct TCGBackendData { - TCGLabelQemuLdst *labels; -} TCGBackendData; - -static inline void tcg_out_tb_init(TCGContext *s) -{ - s->be->labels = NULL; -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc, - tcg_insn_unit *label_ptr) -{ - TCGBackendData *be = s->be; - TCGLabelQemuLdst *l = tcg_malloc(sizeof(*l)); - - l->is_ld = is_ld; - l->size = opc & MO_SIZE; - l->label_ptr = label_ptr; - l->next = be->labels; - be->labels = l; -} - -static bool tcg_out_tb_finalize(TCGContext *s) -{ - static const void * const helpers[8] = { - helper_ret_stb_mmu, - helper_le_stw_mmu, - helper_le_stl_mmu, - helper_le_stq_mmu, - helper_ret_ldub_mmu, - helper_le_lduw_mmu, - helper_le_ldul_mmu, - helper_le_ldq_mmu, - }; - tcg_insn_unit *thunks[8] = { }; - TCGLabelQemuLdst *l; - - for (l = s->be->labels; l != NULL; l = l->next) { - long x = l->is_ld * 4 + l->size; - tcg_insn_unit *dest = thunks[x]; - - /* The out-of-line thunks are all the same; load the return address - from B0, load the GP, and branch to the code. Note that we are - always post-call, so the register window has rolled, so we're - using incoming parameter register numbers, not outgoing. */ - if (dest == NULL) { - uintptr_t *desc = (uintptr_t *)helpers[x]; - uintptr_t func = desc[0], gp = desc[1], disp; - - thunks[x] = dest = s->code_ptr; - - tcg_out_bundle(s, mlx, - INSN_NOP_M, - tcg_opc_l2 (gp), - tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, - TCG_REG_R1, gp)); - tcg_out_bundle(s, mii, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, - l->is_ld ? TCG_REG_R35 : TCG_REG_R36, - TCG_REG_B0)); - disp = (tcg_insn_unit *)func - s->code_ptr; - tcg_out_bundle(s, mLX, - INSN_NOP_M, - tcg_opc_l3 (disp), - tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, disp)); - } - - reloc_pcrel21b_slot2(l->label_ptr, dest); - - /* Test for (pending) buffer overflow. The assumption is that any - one operation beginning below the high water mark cannot overrun - the buffer completely. Thus we can test for overflow after - generating code without having to check during generation. */ - if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { - return false; - } - } - return true; -} - -static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args) -{ - static const uint64_t opc_ld_m1[4] = { - OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 - }; - int addr_reg, data_reg, mem_index; - TCGMemOpIdx oi; - TCGMemOp opc, s_bits; - uint64_t fin1, fin2; - tcg_insn_unit *label_ptr; - - data_reg = args[0]; - addr_reg = args[1]; - oi = args[2]; - opc = get_memop(oi); - mem_index = get_mmuidx(oi); - s_bits = opc & MO_SIZE; - - /* Read the TLB entry */ - tcg_out_qemu_tlb(s, addr_reg, opc, - offsetof(CPUArchState, tlb_table[mem_index][0].addr_read), - offsetof(CPUArchState, tlb_table[mem_index][0].addend), - INSN_NOP_I, INSN_NOP_I); - - /* P6 is the fast path, and P7 the slow path */ - - fin2 = 0; - if (opc & MO_BSWAP) { - fin1 = tcg_opc_bswap64_i(TCG_REG_P0, data_reg, TCG_REG_R8); - if (s_bits < MO_64) { - int shift = 64 - (8 << s_bits); - fin2 = (opc & MO_SIGN ? OPC_EXTR_I11 : OPC_EXTR_U_I11); - fin2 = tcg_opc_i11(TCG_REG_P0, fin2, - data_reg, data_reg, shift, 63 - shift); - } - } else { - fin1 = tcg_opc_ext_i(TCG_REG_P0, opc, data_reg, TCG_REG_R8); - } - - tcg_out_bundle(s, mmI, - tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R56, TCG_AREG0), - tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R2, - TCG_REG_R2, TCG_REG_R57), - tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R58, oi)); - label_ptr = s->code_ptr; - tcg_out_bundle(s, miB, - tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], - TCG_REG_R8, TCG_REG_R2), - INSN_NOP_I, - tcg_opc_b3 (TCG_REG_P7, OPC_BR_CALL_SPNT_FEW_B3, TCG_REG_B0, - get_reloc_pcrel21b_slot2(label_ptr))); - - add_qemu_ldst_label(s, 1, opc, label_ptr); - - /* Note that we always use LE helper functions, so the bswap insns - here for the fast path also apply to the slow path. */ - tcg_out_bundle(s, (fin2 ? mII : miI), - INSN_NOP_M, - fin1, - fin2 ? fin2 : INSN_NOP_I); -} - -static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) -{ - static const uint64_t opc_st_m4[4] = { - OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 - }; - TCGReg addr_reg, data_reg; - int mem_index; - uint64_t pre1, pre2; - TCGMemOpIdx oi; - TCGMemOp opc, s_bits; - tcg_insn_unit *label_ptr; - - data_reg = args[0]; - addr_reg = args[1]; - oi = args[2]; - opc = get_memop(oi); - mem_index = get_mmuidx(oi); - s_bits = opc & MO_SIZE; - - /* Note that we always use LE helper functions, so the bswap insns - that are here for the fast path also apply to the slow path, - and move the data into the argument register. */ - pre2 = INSN_NOP_I; - if (opc & MO_BSWAP) { - pre1 = tcg_opc_bswap64_i(TCG_REG_P0, TCG_REG_R58, data_reg); - if (s_bits < MO_64) { - int shift = 64 - (8 << s_bits); - pre2 = tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, - TCG_REG_R58, TCG_REG_R58, shift, 63 - shift); - } - } else { - /* Just move the data into place for the slow path. */ - pre1 = tcg_opc_ext_i(TCG_REG_P0, opc, TCG_REG_R58, data_reg); - } - - tcg_out_qemu_tlb(s, addr_reg, opc, - offsetof(CPUArchState, tlb_table[mem_index][0].addr_write), - offsetof(CPUArchState, tlb_table[mem_index][0].addend), - pre1, pre2); - - /* P6 is the fast path, and P7 the slow path */ - tcg_out_bundle(s, mmI, - tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R56, TCG_AREG0), - tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R2, - TCG_REG_R2, TCG_REG_R57), - tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R59, oi)); - label_ptr = s->code_ptr; - tcg_out_bundle(s, miB, - tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits], - TCG_REG_R58, TCG_REG_R2), - INSN_NOP_I, - tcg_opc_b3 (TCG_REG_P7, OPC_BR_CALL_SPNT_FEW_B3, TCG_REG_B0, - get_reloc_pcrel21b_slot2(label_ptr))); - - add_qemu_ldst_label(s, 0, opc, label_ptr); -} - -#else /* !CONFIG_SOFTMMU */ -# include "tcg-be-null.h" - -static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args) -{ - static uint64_t const opc_ld_m1[4] = { - OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 - }; - int addr_reg, data_reg; - TCGMemOp opc, s_bits, bswap; - - data_reg = args[0]; - addr_reg = args[1]; - opc = args[2]; - s_bits = opc & MO_SIZE; - bswap = opc & MO_BSWAP; - -#if TARGET_LONG_BITS == 32 - if (guest_base != 0) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, - TCG_REG_R3, addr_reg), - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, - TCG_GUEST_BASE_REG, TCG_REG_R3)); - } else { - tcg_out_bundle(s, miI, - INSN_NOP_M, - tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, - TCG_REG_R2, addr_reg), - INSN_NOP_I); - } - - if (!bswap) { - if (!(opc & MO_SIGN)) { - tcg_out_bundle(s, miI, - tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], - data_reg, TCG_REG_R2), - INSN_NOP_I, - INSN_NOP_I); - } else { - tcg_out_bundle(s, mII, - tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], - data_reg, TCG_REG_R2), - INSN_NOP_I, - tcg_opc_ext_i(TCG_REG_P0, opc, data_reg, data_reg)); - } - } else if (s_bits == MO_64) { - tcg_out_bundle(s, mII, - tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], - data_reg, TCG_REG_R2), - INSN_NOP_I, - tcg_opc_bswap64_i(TCG_REG_P0, data_reg, data_reg)); - } else { - if (s_bits == MO_16) { - tcg_out_bundle(s, mII, - tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], - data_reg, TCG_REG_R2), - INSN_NOP_I, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - data_reg, data_reg, 15, 15)); - } else { - tcg_out_bundle(s, mII, - tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], - data_reg, TCG_REG_R2), - INSN_NOP_I, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - data_reg, data_reg, 31, 31)); - } - if (!(opc & MO_SIGN)) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_bswap64_i(TCG_REG_P0, data_reg, data_reg)); - } else { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_bswap64_i(TCG_REG_P0, data_reg, data_reg), - tcg_opc_ext_i(TCG_REG_P0, opc, data_reg, data_reg)); - } - } -#else - if (guest_base != 0) { - tcg_out_bundle(s, MmI, - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, - TCG_GUEST_BASE_REG, addr_reg), - tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], - data_reg, TCG_REG_R2), - INSN_NOP_I); - } else { - tcg_out_bundle(s, mmI, - INSN_NOP_M, - tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], - data_reg, addr_reg), - INSN_NOP_I); - } - - if (bswap && s_bits == MO_16) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - data_reg, data_reg, 15, 15), - tcg_opc_bswap64_i(TCG_REG_P0, data_reg, data_reg)); - } else if (bswap && s_bits == MO_32) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - data_reg, data_reg, 31, 31), - tcg_opc_bswap64_i(TCG_REG_P0, data_reg, data_reg)); - } else if (bswap && s_bits == MO_64) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_bswap64_i(TCG_REG_P0, data_reg, data_reg)); - } - if (opc & MO_SIGN) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_ext_i(TCG_REG_P0, opc, data_reg, data_reg)); - } -#endif -} - -static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) -{ - static uint64_t const opc_st_m4[4] = { - OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 - }; - int addr_reg, data_reg; -#if TARGET_LONG_BITS == 64 - uint64_t add_guest_base; -#endif - TCGMemOp opc, s_bits, bswap; - - data_reg = args[0]; - addr_reg = args[1]; - opc = args[2]; - s_bits = opc & MO_SIZE; - bswap = opc & MO_BSWAP; - -#if TARGET_LONG_BITS == 32 - if (guest_base != 0) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, - TCG_REG_R3, addr_reg), - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, - TCG_GUEST_BASE_REG, TCG_REG_R3)); - } else { - tcg_out_bundle(s, miI, - INSN_NOP_M, - tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, - TCG_REG_R2, addr_reg), - INSN_NOP_I); - } - - if (bswap) { - if (s_bits == MO_16) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - TCG_REG_R3, data_reg, 15, 15), - tcg_opc_bswap64_i(TCG_REG_P0, - TCG_REG_R3, TCG_REG_R3)); - data_reg = TCG_REG_R3; - } else if (s_bits == MO_32) { - tcg_out_bundle(s, mII, - INSN_NOP_M, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - TCG_REG_R3, data_reg, 31, 31), - tcg_opc_bswap64_i(TCG_REG_P0, - TCG_REG_R3, TCG_REG_R3)); - data_reg = TCG_REG_R3; - } else if (s_bits == MO_64) { - tcg_out_bundle(s, miI, - INSN_NOP_M, - INSN_NOP_I, - tcg_opc_bswap64_i(TCG_REG_P0, TCG_REG_R3, data_reg)); - data_reg = TCG_REG_R3; - } - } - tcg_out_bundle(s, mmI, - tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], - data_reg, TCG_REG_R2), - INSN_NOP_M, - INSN_NOP_I); -#else - if (guest_base != 0) { - add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, - TCG_GUEST_BASE_REG, addr_reg); - addr_reg = TCG_REG_R2; - } else { - add_guest_base = INSN_NOP_M; - } - - if (!bswap) { - tcg_out_bundle(s, (guest_base ? MmI : mmI), - add_guest_base, - tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], - data_reg, addr_reg), - INSN_NOP_I); - } else { - if (s_bits == MO_16) { - tcg_out_bundle(s, mII, - add_guest_base, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - TCG_REG_R3, data_reg, 15, 15), - tcg_opc_bswap64_i(TCG_REG_P0, - TCG_REG_R3, TCG_REG_R3)); - data_reg = TCG_REG_R3; - } else if (s_bits == MO_32) { - tcg_out_bundle(s, mII, - add_guest_base, - tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, - TCG_REG_R3, data_reg, 31, 31), - tcg_opc_bswap64_i(TCG_REG_P0, - TCG_REG_R3, TCG_REG_R3)); - data_reg = TCG_REG_R3; - } else if (s_bits == MO_64) { - tcg_out_bundle(s, miI, - add_guest_base, - INSN_NOP_I, - tcg_opc_bswap64_i(TCG_REG_P0, TCG_REG_R3, data_reg)); - data_reg = TCG_REG_R3; - } - tcg_out_bundle(s, miI, - tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], - data_reg, addr_reg), - INSN_NOP_I, - INSN_NOP_I); - } -#endif -} - -#endif - -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg *args, const int *const_args) -{ - switch(opc) { - case INDEX_op_exit_tb: - tcg_out_exit_tb(s, args[0]); - break; - case INDEX_op_br: - tcg_out_br(s, arg_label(args[0])); - break; - case INDEX_op_goto_tb: - tcg_out_goto_tb(s, args[0]); - break; - - case INDEX_op_ld8u_i32: - case INDEX_op_ld8u_i64: - tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); - break; - case INDEX_op_ld8s_i32: - case INDEX_op_ld8s_i64: - tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]); - tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]); - break; - case INDEX_op_ld16u_i32: - case INDEX_op_ld16u_i64: - tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); - break; - case INDEX_op_ld16s_i32: - case INDEX_op_ld16s_i64: - tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]); - tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]); - break; - case INDEX_op_ld_i32: - case INDEX_op_ld32u_i64: - tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); - break; - case INDEX_op_ld32s_i64: - tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]); - tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]); - break; - case INDEX_op_ld_i64: - tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]); - break; - case INDEX_op_st8_i32: - case INDEX_op_st8_i64: - tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]); - break; - case INDEX_op_st16_i32: - case INDEX_op_st16_i64: - tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]); - break; - case INDEX_op_st_i32: - case INDEX_op_st32_i64: - tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]); - break; - case INDEX_op_st_i64: - tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]); - break; - - case INDEX_op_add_i32: - case INDEX_op_add_i64: - tcg_out_add(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - tcg_out_sub(s, args[0], args[1], const_args[1], args[2], const_args[2]); - break; - - case INDEX_op_and_i32: - case INDEX_op_and_i64: - /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */ - tcg_out_alu(s, OPC_AND_A1, OPC_AND_A3, args[0], - args[2], const_args[2], args[1], const_args[1]); - break; - case INDEX_op_andc_i32: - case INDEX_op_andc_i64: - tcg_out_alu(s, OPC_ANDCM_A1, OPC_ANDCM_A3, args[0], - args[1], const_args[1], args[2], const_args[2]); - break; - case INDEX_op_eqv_i32: - case INDEX_op_eqv_i64: - tcg_out_eqv(s, args[0], args[1], const_args[1], - args[2], const_args[2]); - break; - case INDEX_op_nand_i32: - case INDEX_op_nand_i64: - tcg_out_nand(s, args[0], args[1], const_args[1], - args[2], const_args[2]); - break; - case INDEX_op_nor_i32: - case INDEX_op_nor_i64: - tcg_out_nor(s, args[0], args[1], const_args[1], - args[2], const_args[2]); - break; - case INDEX_op_or_i32: - case INDEX_op_or_i64: - /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */ - tcg_out_alu(s, OPC_OR_A1, OPC_OR_A3, args[0], - args[2], const_args[2], args[1], const_args[1]); - break; - case INDEX_op_orc_i32: - case INDEX_op_orc_i64: - tcg_out_orc(s, args[0], args[1], const_args[1], - args[2], const_args[2]); - break; - case INDEX_op_xor_i32: - case INDEX_op_xor_i64: - /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */ - tcg_out_alu(s, OPC_XOR_A1, OPC_XOR_A3, args[0], - args[2], const_args[2], args[1], const_args[1]); - break; - - case INDEX_op_mul_i32: - case INDEX_op_mul_i64: - tcg_out_mul(s, args[0], args[1], args[2]); - break; - - case INDEX_op_sar_i32: - tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_sar_i64: - tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_shl_i32: - tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_shl_i64: - tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_shr_i32: - tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_shr_i64: - tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_rotl_i32: - tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_rotl_i64: - tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_rotr_i32: - tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]); - break; - case INDEX_op_rotr_i64: - tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]); - break; - - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]); - break; - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]); - break; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]); - break; - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]); - break; - case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]); - break; - case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]); - break; - - case INDEX_op_bswap16_i32: - case INDEX_op_bswap16_i64: - tcg_out_bswap16(s, args[0], args[1]); - break; - case INDEX_op_bswap32_i32: - case INDEX_op_bswap32_i64: - tcg_out_bswap32(s, args[0], args[1]); - break; - case INDEX_op_bswap64_i64: - tcg_out_bswap64(s, args[0], args[1]); - break; - - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - tcg_out_deposit(s, args[0], args[1], args[2], const_args[2], - args[3], args[4]); - break; - - case INDEX_op_brcond_i32: - tcg_out_brcond(s, args[2], args[0], args[1], arg_label(args[3]), 1); - break; - case INDEX_op_brcond_i64: - tcg_out_brcond(s, args[2], args[0], args[1], arg_label(args[3]), 0); - break; - case INDEX_op_setcond_i32: - tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1); - break; - case INDEX_op_setcond_i64: - tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0); - break; - case INDEX_op_movcond_i32: - tcg_out_movcond(s, args[5], args[0], args[1], args[2], - args[3], const_args[3], args[4], const_args[4], 1); - break; - case INDEX_op_movcond_i64: - tcg_out_movcond(s, args[5], args[0], args[1], args[2], - args[3], const_args[3], args[4], const_args[4], 0); - break; - - case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args); - break; - case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args); - break; - case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args); - break; - - case INDEX_op_mb: - tcg_out_bundle(s, mmI, OPC_MF_M24, INSN_NOP_M, INSN_NOP_I); - break; - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ - case INDEX_op_movi_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - tcg_abort(); - } -} - -static const TCGTargetOpDef ia64_op_defs[] = { - { INDEX_op_br, { } }, - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "rZ", "r" } }, - { INDEX_op_st16_i32, { "rZ", "r" } }, - { INDEX_op_st_i32, { "rZ", "r" } }, - - { INDEX_op_add_i32, { "r", "rZ", "rI" } }, - { INDEX_op_sub_i32, { "r", "rI", "rI" } }, - - { INDEX_op_and_i32, { "r", "rI", "rI" } }, - { INDEX_op_andc_i32, { "r", "rI", "rI" } }, - { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } }, - { INDEX_op_nand_i32, { "r", "rZ", "rZ" } }, - { INDEX_op_nor_i32, { "r", "rZ", "rZ" } }, - { INDEX_op_or_i32, { "r", "rI", "rI" } }, - { INDEX_op_orc_i32, { "r", "rZ", "rZ" } }, - { INDEX_op_xor_i32, { "r", "rI", "rI" } }, - - { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, - - { INDEX_op_sar_i32, { "r", "rZ", "ri" } }, - { INDEX_op_shl_i32, { "r", "rZ", "ri" } }, - { INDEX_op_shr_i32, { "r", "rZ", "ri" } }, - { INDEX_op_rotl_i32, { "r", "rZ", "ri" } }, - { INDEX_op_rotr_i32, { "r", "rZ", "ri" } }, - - { INDEX_op_ext8s_i32, { "r", "rZ"} }, - { INDEX_op_ext8u_i32, { "r", "rZ"} }, - { INDEX_op_ext16s_i32, { "r", "rZ"} }, - { INDEX_op_ext16u_i32, { "r", "rZ"} }, - - { INDEX_op_bswap16_i32, { "r", "rZ" } }, - { INDEX_op_bswap32_i32, { "r", "rZ" } }, - - { INDEX_op_brcond_i32, { "rZ", "rZ" } }, - { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, - { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } }, - - { INDEX_op_ld8u_i64, { "r", "r" } }, - { INDEX_op_ld8s_i64, { "r", "r" } }, - { INDEX_op_ld16u_i64, { "r", "r" } }, - { INDEX_op_ld16s_i64, { "r", "r" } }, - { INDEX_op_ld32u_i64, { "r", "r" } }, - { INDEX_op_ld32s_i64, { "r", "r" } }, - { INDEX_op_ld_i64, { "r", "r" } }, - { INDEX_op_st8_i64, { "rZ", "r" } }, - { INDEX_op_st16_i64, { "rZ", "r" } }, - { INDEX_op_st32_i64, { "rZ", "r" } }, - { INDEX_op_st_i64, { "rZ", "r" } }, - - { INDEX_op_add_i64, { "r", "rZ", "rI" } }, - { INDEX_op_sub_i64, { "r", "rI", "rI" } }, - - { INDEX_op_and_i64, { "r", "rI", "rI" } }, - { INDEX_op_andc_i64, { "r", "rI", "rI" } }, - { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } }, - { INDEX_op_nand_i64, { "r", "rZ", "rZ" } }, - { INDEX_op_nor_i64, { "r", "rZ", "rZ" } }, - { INDEX_op_or_i64, { "r", "rI", "rI" } }, - { INDEX_op_orc_i64, { "r", "rZ", "rZ" } }, - { INDEX_op_xor_i64, { "r", "rI", "rI" } }, - - { INDEX_op_mul_i64, { "r", "rZ", "rZ" } }, - - { INDEX_op_sar_i64, { "r", "rZ", "ri" } }, - { INDEX_op_shl_i64, { "r", "rZ", "ri" } }, - { INDEX_op_shr_i64, { "r", "rZ", "ri" } }, - { INDEX_op_rotl_i64, { "r", "rZ", "ri" } }, - { INDEX_op_rotr_i64, { "r", "rZ", "ri" } }, - - { INDEX_op_ext8s_i64, { "r", "rZ"} }, - { INDEX_op_ext8u_i64, { "r", "rZ"} }, - { INDEX_op_ext16s_i64, { "r", "rZ"} }, - { INDEX_op_ext16u_i64, { "r", "rZ"} }, - { INDEX_op_ext32s_i64, { "r", "rZ"} }, - { INDEX_op_ext32u_i64, { "r", "rZ"} }, - { INDEX_op_ext_i32_i64, { "r", "rZ" } }, - { INDEX_op_extu_i32_i64, { "r", "rZ" } }, - - { INDEX_op_bswap16_i64, { "r", "rZ" } }, - { INDEX_op_bswap32_i64, { "r", "rZ" } }, - { INDEX_op_bswap64_i64, { "r", "rZ" } }, - - { INDEX_op_brcond_i64, { "rZ", "rZ" } }, - { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } }, - { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } }, - - { INDEX_op_deposit_i32, { "r", "rZ", "ri" } }, - { INDEX_op_deposit_i64, { "r", "rZ", "ri" } }, - - { INDEX_op_qemu_ld_i32, { "r", "r" } }, - { INDEX_op_qemu_ld_i64, { "r", "r" } }, - { INDEX_op_qemu_st_i32, { "SZ", "r" } }, - { INDEX_op_qemu_st_i64, { "SZ", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - int i, n = ARRAY_SIZE(ia64_op_defs); - - for (i = 0; i < n; ++i) { - if (ia64_op_defs[i].op == op) { - return &ia64_op_defs[i]; - } - } - return NULL; -} - -/* Generate global QEMU prologue and epilogue code */ -static void tcg_target_qemu_prologue(TCGContext *s) -{ - int frame_size; - - /* reserve some stack space */ - frame_size = TCG_STATIC_CALL_ARGS_SIZE + - CPU_TEMP_BUF_NLONGS * sizeof(long); - frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & - ~(TCG_TARGET_STACK_ALIGN - 1); - tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, - CPU_TEMP_BUF_NLONGS * sizeof(long)); - - /* First emit adhoc function descriptor */ - *s->code_ptr = (tcg_insn_unit){ - (uint64_t)(s->code_ptr + 1), /* entry point */ - 0 /* skip gp */ - }; - s->code_ptr++; - - /* prologue */ - tcg_out_bundle(s, miI, - tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34, - TCG_REG_R34, 32, 24, 0), - INSN_NOP_I, - tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, - TCG_REG_B6, TCG_REG_R33, 0)); - - /* ??? If guest_base < 0x200000, we could load the register via - an ADDL in the M slot of the next bundle. */ - if (guest_base != 0) { - tcg_out_bundle(s, mlx, - INSN_NOP_M, - tcg_opc_l2(guest_base), - tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, - TCG_GUEST_BASE_REG, guest_base)); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); - } - - tcg_out_bundle(s, miB, - tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, - TCG_REG_R12, -frame_size, TCG_REG_R12), - tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, - TCG_REG_R33, TCG_REG_B0), - tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); - - /* epilogue */ - tb_ret_addr = s->code_ptr; - tcg_out_bundle(s, miI, - INSN_NOP_M, - tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, - TCG_REG_B0, TCG_REG_R33, 0), - tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, - TCG_REG_R12, frame_size, TCG_REG_R12)); - tcg_out_bundle(s, miB, - INSN_NOP_M, - tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26, - TCG_REG_PFS, TCG_REG_R34), - tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4, - TCG_REG_B0)); -} - -static void tcg_target_init(TCGContext *s) -{ - tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], - 0xffffffffffffffffull); - tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], - 0xffffffffffffffffull); - - tcg_regset_clear(tcg_target_call_clobber_regs); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62); - tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63); - - tcg_regset_clear(s->reserved_regs); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* return address */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */ - - /* The following 4 are not in use, are call-saved, but *not* saved - by the prologue. Therefore we cannot use them without modifying - the prologue. There doesn't seem to be any good reason to use - these as opposed to the windowed registers. */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7); -} diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..e9558d15bc 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -206,4 +206,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) cacheflush ((void *)start, stop-start, ICACHE); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5f4a40a5b4..5a092b038a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -125,4 +125,6 @@ extern bool have_isa_3_00; void flush_icache_range(uintptr_t start, uintptr_t stop); +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..bedda5edf6 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -58,6 +58,8 @@ typedef enum TCGReg { #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND +#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND +#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53)) extern uint64_t s390_facilities; @@ -133,6 +135,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + enum { TCG_AREG0 = TCG_REG_R10, }; diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5d7083e90c..38b9e791ee 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -38,12 +38,13 @@ a 32-bit displacement here Just In Case. */ #define USE_LONG_BRANCHES 0 -#define TCG_CT_CONST_MULI 0x100 -#define TCG_CT_CONST_ORI 0x200 -#define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_CMPI 0x800 -#define TCG_CT_CONST_ADLI 0x1000 -#define TCG_CT_CONST_ZERO 0x2000 +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_S32 0x200 +#define TCG_CT_CONST_NN16 0x400 +#define TCG_CT_CONST_NN32 0x800 +#define TCG_CT_CONST_U31 0x1000 +#define TCG_CT_CONST_S33 0x2000 +#define TCG_CT_CONST_ZERO 0x4000 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -121,6 +122,7 @@ typedef enum S390Opcode { RIE_CLGIJ = 0xec7d, RIE_CLRJ = 0xec77, RIE_CRJ = 0xec76, + RIE_LOCGHI = 0xec46, RIE_RISBG = 0xec55, RRE_AGR = 0xb908, @@ -158,6 +160,16 @@ typedef enum S390Opcode { RRF_LOCR = 0xb9f2, RRF_LOCGR = 0xb9e2, + RRF_NRK = 0xb9f4, + RRF_NGRK = 0xb9e4, + RRF_ORK = 0xb9f6, + RRF_OGRK = 0xb9e6, + RRF_SRK = 0xb9f9, + RRF_SGRK = 0xb9e9, + RRF_SLRK = 0xb9fb, + RRF_SLGRK = 0xb9eb, + RRF_XRK = 0xb9f7, + RRF_XGRK = 0xb9e7, RR_AR = 0x1a, RR_ALR = 0x1e, @@ -178,8 +190,11 @@ typedef enum S390Opcode { RSY_RLL = 0xeb1d, RSY_RLLG = 0xeb1c, RSY_SLLG = 0xeb0d, + RSY_SLLK = 0xebdf, RSY_SRAG = 0xeb0a, + RSY_SRAK = 0xebdc, RSY_SRLG = 0xeb0c, + RSY_SRLK = 0xebde, RS_SLL = 0x89, RS_SRA = 0x8a, @@ -386,19 +401,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); break; case 'A': - ct->ct |= TCG_CT_CONST_ADLI; + ct->ct |= TCG_CT_CONST_S33; break; - case 'K': - ct->ct |= TCG_CT_CONST_MULI; + case 'I': + ct->ct |= TCG_CT_CONST_S16; break; - case 'O': - ct->ct |= TCG_CT_CONST_ORI; + case 'J': + ct->ct |= TCG_CT_CONST_S32; break; - case 'X': - ct->ct |= TCG_CT_CONST_XORI; + case 'N': + ct->ct |= TCG_CT_CONST_NN16; + break; + case 'M': + ct->ct |= TCG_CT_CONST_NN32; break; case 'C': - ct->ct |= TCG_CT_CONST_CMPI; + /* ??? We have no insight here into whether the comparison is + signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit + signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses + a 32-bit unsigned immediate. If we were to use the (semi) + obvious "val == (int32_t)val" we would be enabling unsigned + comparisons vs very large numbers. The only solution is to + take the intersection of the ranges. */ + /* ??? Another possible solution is to simply lie and allow all + constants here and force the out-of-range values into a temp + register in tgen_cmp when we have knowledge of the actual + comparison code in use. */ + ct->ct |= TCG_CT_CONST_U31; break; case 'Z': ct->ct |= TCG_CT_CONST_ZERO; @@ -409,103 +438,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, return ct_str; } -/* Immediates to be used with logical OR. This is an optimization only, - since a full 64-bit immediate OR can always be performed with 4 sequential - OI[LH][LH] instructions. What we're looking for is immediates that we - can load efficiently, and the immediate load plus the reg-reg OR is - smaller than the sequential OI's. */ - -static int tcg_match_ori(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type == TCG_TYPE_I32) { - /* All 32-bit ORs can be performed with 1 48-bit insn. */ - return 1; - } - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0) { - if (val == (int16_t)val) { - return 0; - } - if (s390_facilities & FACILITY_EXT_IMM) { - if (val == (int32_t)val) { - return 0; - } - } - } - - return 1; -} - -/* Immediates to be used with logical XOR. This is almost, but not quite, - only an optimization. XOR with immediate is only supported with the - extended-immediate facility. That said, there are a few patterns for - which it is better to load the value into a register first. */ - -static int tcg_match_xori(TCGType type, tcg_target_long val) -{ - if ((s390_facilities & FACILITY_EXT_IMM) == 0) { - return 0; - } - - if (type == TCG_TYPE_I32) { - /* All 32-bit XORs can be performed with 1 48-bit insn. */ - return 1; - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0 && val == (int32_t)val) { - return 0; - } - - return 1; -} - -/* Imediates to be used with comparisons. */ - -static int tcg_match_cmpi(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - /* The COMPARE IMMEDIATE instruction is available. */ - if (type == TCG_TYPE_I32) { - /* We have a 32-bit immediate and can compare against anything. */ - return 1; - } else { - /* ??? We have no insight here into whether the comparison is - signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit - signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses - a 32-bit unsigned immediate. If we were to use the (semi) - obvious "val == (int32_t)val" we would be enabling unsigned - comparisons vs very large numbers. The only solution is to - take the intersection of the ranges. */ - /* ??? Another possible solution is to simply lie and allow all - constants here and force the out-of-range values into a temp - register in tgen_cmp when we have knowledge of the actual - comparison code in use. */ - return val >= 0 && val <= 0x7fffffff; - } - } else { - /* Only the LOAD AND TEST instruction is available. */ - return val == 0; - } -} - -/* Immediates to be used with add2/sub2. */ - -static int tcg_match_add2i(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type == TCG_TYPE_I32) { - return 1; - } else if (val >= -0xffffffffll && val <= 0xffffffffll) { - return 1; - } - } - return 0; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -521,24 +453,18 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, } /* The following are mutually exclusive. */ - if (ct & TCG_CT_CONST_MULI) { - /* Immediates that may be used with multiply. If we have the - general-instruction-extensions, then we have MULTIPLY SINGLE - IMMEDIATE with a signed 32-bit, otherwise we have only - MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { - return val == (int32_t)val; - } else { - return val == (int16_t)val; - } - } else if (ct & TCG_CT_CONST_ADLI) { - return tcg_match_add2i(type, val); - } else if (ct & TCG_CT_CONST_ORI) { - return tcg_match_ori(type, val); - } else if (ct & TCG_CT_CONST_XORI) { - return tcg_match_xori(type, val); - } else if (ct & TCG_CT_CONST_CMPI) { - return tcg_match_cmpi(type, val); + if (ct & TCG_CT_CONST_S16) { + return val == (int16_t)val; + } else if (ct & TCG_CT_CONST_S32) { + return val == (int32_t)val; + } else if (ct & TCG_CT_CONST_S33) { + return val >= -0xffffffffll && val <= 0xffffffffll; + } else if (ct & TCG_CT_CONST_NN16) { + return !(val < 0 && val == (int16_t)val); + } else if (ct & TCG_CT_CONST_NN32) { + return !(val < 0 && val == (int32_t)val); + } else if (ct & TCG_CT_CONST_U31) { + return val >= 0 && val <= 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { return val == 0; } @@ -570,6 +496,13 @@ static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2) tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); } +static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1, + int i2, int m3) +{ + tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); + tcg_out32(s, (i2 << 16) | (op & 0xff)); +} + static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2) { tcg_out16(s, op | (r1 << 4)); @@ -1138,11 +1071,33 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int c2const) { int cc; + bool have_loc; + + /* With LOC2, we can always emit the minimum 3 insns. */ + if (s390_facilities & FACILITY_LOAD_ON_COND2) { + /* Emit: d = 0, d = (cc ? 1 : d). */ + cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc); + return; + } + have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0; + + /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ + restart: switch (cond) { + case TCG_COND_NE: + /* X != 0 is X > 0. */ + if (c2const && c2 == 0) { + cond = TCG_COND_GTU; + } else { + break; + } + /* fallthru */ + case TCG_COND_GTU: case TCG_COND_GT: - do_greater: /* The result of a compare has CC=2 for GT and CC=3 unused. ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ tgen_cmp(s, type, cond, c1, c2, c2const, true); @@ -1150,34 +1105,34 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, tcg_out_insn(s, RRE, ALCGR, dest, dest); return; - case TCG_COND_GEU: - do_geu: - /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This needs an extra move. */ - tcg_out_mov(s, type, TCG_TMP0, c1); - if (c2const) { - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); - } + case TCG_COND_EQ: + /* X == 0 is X <= 0. */ + if (c2const && c2 == 0) { + cond = TCG_COND_LEU; } else { - if (type == TCG_TYPE_I32) { - tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); - } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + break; } - tcg_out_insn(s, RRE, ALCGR, dest, dest); - return; + /* fallthru */ case TCG_COND_LEU: + case TCG_COND_LE: + /* As above, but we're looking for borrow, or !carry. + The second insn computes d - d - borrow, or -1 for true + and 0 for false. So we must mask to 1 bit afterward. */ + tgen_cmp(s, type, cond, c1, c2, c2const, true); + tcg_out_insn(s, RRE, SLBGR, dest, dest); + tgen_andi(s, type, dest, 1); + return; + + case TCG_COND_GEU: case TCG_COND_LTU: case TCG_COND_LT: - /* Swap operands so that we can use GEU/GTU/GT. */ + case TCG_COND_GE: + /* Swap operands so that we can use LEU/GTU/GT/LE. */ if (c2const) { + if (have_loc) { + break; + } tcg_out_movi(s, type, TCG_TMP0, c2); c2 = c1; c2const = 0; @@ -1187,37 +1142,15 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, c1 = c2; c2 = t; } - if (cond == TCG_COND_LEU) { - goto do_geu; - } cond = tcg_swap_cond(cond); - goto do_greater; - - case TCG_COND_NE: - /* X != 0 is X > 0. */ - if (c2const && c2 == 0) { - cond = TCG_COND_GTU; - goto do_greater; - } - break; - - case TCG_COND_EQ: - /* X == 0 is X <= 0 is 0 >= X. */ - if (c2const && c2 == 0) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0); - c2 = c1; - c2const = 0; - c1 = TCG_TMP0; - goto do_geu; - } - break; + goto restart; default: - break; + g_assert_not_reached(); } cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); - if (s390_facilities & FACILITY_LOAD_ON_COND) { + if (have_loc) { /* Emit: d = 0, t = 1, d = (cc ? t : d). */ tcg_out_movi(s, TCG_TYPE_I64, dest, 0); tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); @@ -1231,19 +1164,24 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, } static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, - TCGReg c1, TCGArg c2, int c2const, TCGReg r3) + TCGReg c1, TCGArg c2, int c2const, + TCGArg v3, int v3const) { int cc; if (s390_facilities & FACILITY_LOAD_ON_COND) { cc = tgen_cmp(s, type, c, c1, c2, c2const, false); - tcg_out_insn(s, RRF, LOCGR, dest, r3, cc); + if (v3const) { + tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); + } else { + tcg_out_insn(s, RRF, LOCGR, dest, v3, cc); + } } else { c = tcg_invert_cond(c); cc = tgen_cmp(s, type, c, c1, c2, c2const, false); /* Emit: if (cc) goto over; dest = r3; over: */ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, r3); + tcg_out_insn(s, RRE, LGR, dest, v3); } } @@ -1736,7 +1674,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg, static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - S390Opcode op; + S390Opcode op, op2; TCGArg a0, a1, a2; switch (opc) { @@ -1841,29 +1779,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { a2 = -a2; goto do_addi_32; + } else if (a0 == a1) { + tcg_out_insn(s, RR, SR, a0, a2); + } else { + tcg_out_insn(s, RRF, SRK, a0, a1, a2); } - tcg_out_insn(s, RR, SR, args[0], args[2]); break; case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { - tgen_andi(s, TCG_TYPE_I32, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_andi(s, TCG_TYPE_I32, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, NR, a0, a2); } else { - tcg_out_insn(s, RR, NR, args[0], args[2]); + tcg_out_insn(s, RRF, NRK, a0, a1, a2); } break; case INDEX_op_or_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2] & 0xffffffff); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RR, OR, a0, a2); } else { - tcg_out_insn(s, RR, OR, args[0], args[2]); + tcg_out_insn(s, RRF, ORK, a0, a1, a2); } break; case INDEX_op_xor_i32: + a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2] & 0xffffffff); - } else { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 == a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; @@ -1892,18 +1845,31 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_shl_i32: op = RS_SLL; + op2 = RSY_SLLK; do_shift32: - if (const_args[2]) { - tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]); + a0 = args[0], a1 = args[1], a2 = (int32_t)args[2]; + if (a0 == a1) { + if (const_args[2]) { + tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); + } else { + tcg_out_sh32(s, op, a0, a2, 0); + } } else { - tcg_out_sh32(s, op, args[0], args[2], 0); + /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */ + if (const_args[2]) { + tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); + } else { + tcg_out_sh64(s, op2, a0, a1, a2, 0); + } } break; case INDEX_op_shr_i32: op = RS_SRL; + op2 = RSY_SRLK; goto do_shift32; case INDEX_op_sar_i32: op = RS_SRA; + op2 = RSY_SRAK; goto do_shift32; case INDEX_op_rotl_i32: @@ -1978,7 +1944,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_movcond_i32: tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; case INDEX_op_qemu_ld_i32: @@ -2045,30 +2011,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (const_args[2]) { a2 = -a2; goto do_addi_64; + } else if (a0 == a1) { + tcg_out_insn(s, RRE, SGR, a0, a2); } else { - tcg_out_insn(s, RRE, SGR, args[0], args[2]); + tcg_out_insn(s, RRF, SGRK, a0, a1, a2); } break; case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); - } else { + } else if (a0 == a1) { tcg_out_insn(s, RRE, NGR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, OGR, a0, a2); } else { - tcg_out_insn(s, RRE, OGR, args[0], args[2]); + tcg_out_insn(s, RRF, OGRK, a0, a1, a2); } break; case INDEX_op_xor_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 == a1) { + tcg_out_insn(s, RRE, XGR, a0, a2); } else { - tcg_out_insn(s, RRE, XGR, args[0], args[2]); + tcg_out_insn(s, RRF, XGRK, a0, a1, a2); } break; @@ -2197,7 +2177,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_movcond_i64: tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; OP_32_64(deposit): @@ -2246,134 +2226,210 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef s390_op_defs[] = { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "r", "r" } }, - { INDEX_op_st16_i32, { "r", "r" } }, - { INDEX_op_st_i32, { "r", "r" } }, - - { INDEX_op_add_i32, { "r", "r", "ri" } }, - { INDEX_op_sub_i32, { "r", "0", "ri" } }, - { INDEX_op_mul_i32, { "r", "0", "rK" } }, - - { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, - - { INDEX_op_and_i32, { "r", "0", "ri" } }, - { INDEX_op_or_i32, { "r", "0", "rO" } }, - { INDEX_op_xor_i32, { "r", "0", "rX" } }, - - { INDEX_op_neg_i32, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "0", "ri" } }, - { INDEX_op_shr_i32, { "r", "0", "ri" } }, - { INDEX_op_sar_i32, { "r", "0", "ri" } }, - - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - - { INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i32, { "r", "rC" } }, - { INDEX_op_setcond_i32, { "r", "r", "rC" } }, - { INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i32, { "r", "rZ", "r" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - - { INDEX_op_qemu_ld_i32, { "r", "L" } }, - { INDEX_op_qemu_ld_i64, { "r", "L" } }, - { INDEX_op_qemu_st_i32, { "L", "L" } }, - { INDEX_op_qemu_st_i64, { "L", "L" } }, - - { INDEX_op_ld8u_i64, { "r", "r" } }, - { INDEX_op_ld8s_i64, { "r", "r" } }, - { INDEX_op_ld16u_i64, { "r", "r" } }, - { INDEX_op_ld16s_i64, { "r", "r" } }, - { INDEX_op_ld32u_i64, { "r", "r" } }, - { INDEX_op_ld32s_i64, { "r", "r" } }, - { INDEX_op_ld_i64, { "r", "r" } }, - - { INDEX_op_st8_i64, { "r", "r" } }, - { INDEX_op_st16_i64, { "r", "r" } }, - { INDEX_op_st32_i64, { "r", "r" } }, - { INDEX_op_st_i64, { "r", "r" } }, - - { INDEX_op_add_i64, { "r", "r", "ri" } }, - { INDEX_op_sub_i64, { "r", "0", "ri" } }, - { INDEX_op_mul_i64, { "r", "0", "rK" } }, - - { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_mulu2_i64, { "b", "a", "0", "r" } }, - - { INDEX_op_and_i64, { "r", "0", "ri" } }, - { INDEX_op_or_i64, { "r", "0", "rO" } }, - { INDEX_op_xor_i64, { "r", "0", "rX" } }, - - { INDEX_op_neg_i64, { "r", "r" } }, - - { INDEX_op_shl_i64, { "r", "r", "ri" } }, - { INDEX_op_shr_i64, { "r", "r", "ri" } }, - { INDEX_op_sar_i64, { "r", "r", "ri" } }, - - { INDEX_op_rotl_i64, { "r", "r", "ri" } }, - { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i64, { "r", "r" } }, - { INDEX_op_ext8u_i64, { "r", "r" } }, - { INDEX_op_ext16s_i64, { "r", "r" } }, - { INDEX_op_ext16u_i64, { "r", "r" } }, - { INDEX_op_ext32s_i64, { "r", "r" } }, - { INDEX_op_ext32u_i64, { "r", "r" } }, - - { INDEX_op_ext_i32_i64, { "r", "r" } }, - { INDEX_op_extu_i32_i64, { "r", "r" } }, - - { INDEX_op_bswap16_i64, { "r", "r" } }, - { INDEX_op_bswap32_i64, { "r", "r" } }, - { INDEX_op_bswap64_i64, { "r", "r" } }, - - { INDEX_op_clz_i64, { "r", "r", "ri" } }, - - { INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i64, { "r", "rC" } }, - { INDEX_op_setcond_i64, { "r", "r", "rC" } }, - { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, - { INDEX_op_extract_i64, { "r", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n = ARRAY_SIZE(s390_op_defs); + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; + static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } }; + static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } }; + static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rM = { .args_ct_str = { "r", "r", "rM" } }; + static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } }; + static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; + static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; + static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; + static const TCGTargetOpDef r_0_rN = { .args_ct_str = { "r", "0", "rN" } }; + static const TCGTargetOpDef r_0_rM = { .args_ct_str = { "r", "0", "rM" } }; + static const TCGTargetOpDef a2_r + = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; + static const TCGTargetOpDef a2_ri + = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } }; + static const TCGTargetOpDef a2_rA + = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_ri; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + + case INDEX_op_mul_i32: + /* If we have the general-instruction-extensions, then we have + MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we + have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI); + case INDEX_op_mul_i64: + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); + + case INDEX_op_or_i32: + /* The use of [iNM] constraints are optimization only, since a full + 64-bit immediate OR can always be performed with 4 sequential + OI[LH][LH] instructions. By rejecting certain negative ranges, + the immediate load plus the reg-reg OR is smaller. */ + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri) + : &r_0_rN); + case INDEX_op_or_i64: + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM) + : &r_0_rN); + + case INDEX_op_xor_i32: + /* Without EXT_IMM, no immediates are supported. Otherwise, + rejecting certain negative ranges leads to smaller code. */ + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri) + : &r_0_r); + case INDEX_op_xor_i64: + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM) + : &r_0_r); + + case INDEX_op_and_i32: + case INDEX_op_and_i64: + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); + + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ); + case INDEX_op_brcond_i64: + return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ); + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_clz_i64: + return &r_r_ri; - for (i = 0; i < n; ++i) { - if (s390_op_defs[i].op == op) { - return &s390_op_defs[i]; + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_L; + case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_i32: + return &L_L; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + { + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "rZ", "r" } }; + return &dep; + } + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + { + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + static const TCGTargetOpDef setc_z + = { .args_ct_str = { "r", "r", "rZ" } }; + static const TCGTargetOpDef setc_c + = { .args_ct_str = { "r", "r", "rC" } }; + return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z); + } + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + { + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + static const TCGTargetOpDef movc_z + = { .args_ct_str = { "r", "r", "rZ", "r", "0" } }; + static const TCGTargetOpDef movc_c + = { .args_ct_str = { "r", "r", "rC", "r", "0" } }; + static const TCGTargetOpDef movc_l + = { .args_ct_str = { "r", "r", "rC", "rI", "0" } }; + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_LOAD_ON_COND2 + ? &movc_l : &movc_c) + : &movc_z); + } + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: + { + static const TCGTargetOpDef div2 + = { .args_ct_str = { "b", "a", "0", "1", "r" } }; + return &div2; } + case INDEX_op_mulu2_i64: + { + static const TCGTargetOpDef mul2 + = { .args_ct_str = { "b", "a", "0", "r" } }; + return &mul2; + } + + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + case INDEX_op_add2_i64: + case INDEX_op_sub2_i64: + return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); + + default: + break; } return NULL; } diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 854a0afd70..4515c9ab48 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -162,6 +162,8 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 +#define TCG_TARGET_DEFAULT_MO (0) + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { uintptr_t p; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673ef49..688d91755b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,6 +28,7 @@ #include "exec/exec-all.h" #include "tcg.h" #include "tcg-op.h" +#include "tcg-mo.h" #include "trace-tcg.h" #include "trace/mem.h" @@ -2662,8 +2663,20 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, #endif } +static void tcg_gen_req_mo(TCGBar type) +{ +#ifdef TCG_GUEST_DEFAULT_MO + type &= TCG_GUEST_DEFAULT_MO; +#endif + type &= ~TCG_TARGET_DEFAULT_MO; + if (type) { + tcg_gen_mb(type | TCG_BAR_SC); + } +} + void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 0)); @@ -2672,6 +2685,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 1)); @@ -2680,6 +2694,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2698,6 +2713,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return; diff --git a/tests/qemu-iotests/068 b/tests/qemu-iotests/068 index cfa0f2aed5..e7fca6a494 100755 --- a/tests/qemu-iotests/068 +++ b/tests/qemu-iotests/068 @@ -78,7 +78,7 @@ for extra_args in \ # Give qemu some time to boot before saving the VM state { sleep 1; printf "savevm 0\nquit\n"; } | _qemu $extra_args # Now try to continue from that VM state (this should just work) - echo quit | _qemu $extra_args -loadvm 0 + { sleep 1; printf "loadvm 0\nloadvm 0\nquit\n"; } | _qemu $extra_args -S done # success, all done diff --git a/tests/qemu-iotests/068.out b/tests/qemu-iotests/068.out index aa063cf711..f07a938a38 100644 --- a/tests/qemu-iotests/068.out +++ b/tests/qemu-iotests/068.out @@ -7,6 +7,8 @@ QEMU X.Y.Z monitor - type 'help' for more information (qemu) savevm 0 (qemu) quit QEMU X.Y.Z monitor - type 'help' for more information +(qemu) loadvm 0 +(qemu) loadvm 0 (qemu) quit === Saving and reloading a VM state to/from a qcow2 image (-object iothread,id=iothread0 -set device.hba0.iothread=iothread0) === @@ -16,5 +18,7 @@ QEMU X.Y.Z monitor - type 'help' for more information (qemu) savevm 0 (qemu) quit QEMU X.Y.Z monitor - type 'help' for more information +(qemu) loadvm 0 +(qemu) loadvm 0 (qemu) quit *** done @@ -621,6 +621,7 @@ static const RunStateTransition runstate_transitions_def[] = { { RUN_STATE_PAUSED, RUN_STATE_RUNNING }, { RUN_STATE_PAUSED, RUN_STATE_FINISH_MIGRATE }, + { RUN_STATE_PAUSED, RUN_STATE_POSTMIGRATE }, { RUN_STATE_PAUSED, RUN_STATE_PRELAUNCH }, { RUN_STATE_PAUSED, RUN_STATE_COLO}, @@ -633,6 +634,7 @@ static const RunStateTransition runstate_transitions_def[] = { { RUN_STATE_PRELAUNCH, RUN_STATE_INMIGRATE }, { RUN_STATE_FINISH_MIGRATE, RUN_STATE_RUNNING }, + { RUN_STATE_FINISH_MIGRATE, RUN_STATE_PAUSED }, { RUN_STATE_FINISH_MIGRATE, RUN_STATE_POSTMIGRATE }, { RUN_STATE_FINISH_MIGRATE, RUN_STATE_PRELAUNCH }, { RUN_STATE_FINISH_MIGRATE, RUN_STATE_COLO}, |