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-rw-r--r--Makefile2
-rwxr-xr-xconfigure3
-rw-r--r--crypto/cipher.c5
-rw-r--r--crypto/hash.c13
-rw-r--r--crypto/hmac.c4
-rw-r--r--disas.c96
-rw-r--r--hw/display/sm501.c2
-rw-r--r--hw/ppc/e500.c32
-rw-r--r--hw/s390x/s390-pci-bus.c2
-rw-r--r--include/disas/bfd.h2
-rw-r--r--target/arm/cpu.c6
-rw-r--r--target/i386/cpu.c2
-rw-r--r--target/ppc/compat.c2
-rw-r--r--target/s390x/translate.c9
-rw-r--r--tests/test-aio-multithread.c5
-rw-r--r--tests/test-crypto-block.c3
-rw-r--r--util/async.c2
17 files changed, 129 insertions, 61 deletions
diff --git a/Makefile b/Makefile
index 0496c5057a..814f6820d9 100644
--- a/Makefile
+++ b/Makefile
@@ -405,7 +405,7 @@ CAP_CFLAGS += -DCAPSTONE_HAS_POWERPC
CAP_CFLAGS += -DCAPSTONE_HAS_X86
subdir-capstone: .git-submodule-status
- $(call quiet-command,$(MAKE) -C $(SRC_PATH)/capstone CAPSTONE_SHARED=no BUILDDIR="$(BUILD_DIR)/capstone" CC="$(CC)" AR="$(AR)" LD="$(LD)" CFLAGS="$(CAP_CFLAGS)" $(SUBDIR_MAKEFLAGS) $(BUILD_DIR)/capstone/$(LIBCAPSTONE))
+ $(call quiet-command,$(MAKE) -C $(SRC_PATH)/capstone CAPSTONE_SHARED=no BUILDDIR="$(BUILD_DIR)/capstone" CC="$(CC)" AR="$(AR)" LD="$(LD)" RANLIB="$(RANLIB)" CFLAGS="$(CAP_CFLAGS)" $(SUBDIR_MAKEFLAGS) $(BUILD_DIR)/capstone/$(LIBCAPSTONE))
$(SUBDIR_RULES): libqemuutil.a $(common-obj-y) $(chardev-obj-y) \
$(qom-obj-y) $(crypto-aes-obj-$(CONFIG_USER_ONLY))
diff --git a/configure b/configure
index a6055c0710..0e856bbc04 100755
--- a/configure
+++ b/configure
@@ -482,6 +482,7 @@ ccas="${CCAS-$cc}"
cpp="${CPP-$cc -E}"
objcopy="${OBJCOPY-${cross_prefix}objcopy}"
ld="${LD-${cross_prefix}ld}"
+ranlib="${RANLIB-${cross_prefix}ranlib}"
nm="${NM-${cross_prefix}nm}"
strip="${STRIP-${cross_prefix}strip}"
windres="${WINDRES-${cross_prefix}windres}"
@@ -6288,6 +6289,7 @@ echo "CCAS=$ccas" >> $config_host_mak
echo "CPP=$cpp" >> $config_host_mak
echo "OBJCOPY=$objcopy" >> $config_host_mak
echo "LD=$ld" >> $config_host_mak
+echo "RANLIB=$ranlib" >> $config_host_mak
echo "NM=$nm" >> $config_host_mak
echo "WINDRES=$windres" >> $config_host_mak
echo "CFLAGS=$CFLAGS" >> $config_host_mak
@@ -6782,6 +6784,7 @@ for rom in seabios vgabios ; do
echo "OBJCOPY=objcopy" >> $config_mak
echo "IASL=$iasl" >> $config_mak
echo "LD=$ld" >> $config_mak
+ echo "RANLIB=$ranlib" >> $config_mak
done
# set up tests data directory
diff --git a/crypto/cipher.c b/crypto/cipher.c
index 0aad9d6d79..bcbfb3d5b8 100644
--- a/crypto/cipher.c
+++ b/crypto/cipher.c
@@ -164,11 +164,10 @@ QCryptoCipher *qcrypto_cipher_new(QCryptoCipherAlgorithm alg,
{
QCryptoCipher *cipher;
void *ctx = NULL;
- Error *err2 = NULL;
QCryptoCipherDriver *drv = NULL;
#ifdef CONFIG_AF_ALG
- ctx = qcrypto_afalg_cipher_ctx_new(alg, mode, key, nkey, &err2);
+ ctx = qcrypto_afalg_cipher_ctx_new(alg, mode, key, nkey, NULL);
if (ctx) {
drv = &qcrypto_cipher_afalg_driver;
}
@@ -177,12 +176,10 @@ QCryptoCipher *qcrypto_cipher_new(QCryptoCipherAlgorithm alg,
if (!ctx) {
ctx = qcrypto_cipher_ctx_new(alg, mode, key, nkey, errp);
if (!ctx) {
- error_free(err2);
return NULL;
}
drv = &qcrypto_cipher_lib_driver;
- error_free(err2);
}
cipher = g_new0(QCryptoCipher, 1);
diff --git a/crypto/hash.c b/crypto/hash.c
index ac59c63d5f..8dab25d9ea 100644
--- a/crypto/hash.c
+++ b/crypto/hash.c
@@ -48,19 +48,16 @@ int qcrypto_hash_bytesv(QCryptoHashAlgorithm alg,
{
#ifdef CONFIG_AF_ALG
int ret;
-
+ /*
+ * TODO:
+ * Maybe we should treat some afalg errors as fatal
+ */
ret = qcrypto_hash_afalg_driver.hash_bytesv(alg, iov, niov,
result, resultlen,
- errp);
+ NULL);
if (ret == 0) {
return ret;
}
-
- /*
- * TODO:
- * Maybe we should treat some afalg errors as fatal
- */
- error_free(*errp);
#endif
return qcrypto_hash_lib_driver.hash_bytesv(alg, iov, niov,
diff --git a/crypto/hmac.c b/crypto/hmac.c
index 82b0055adf..f6c2d8db60 100644
--- a/crypto/hmac.c
+++ b/crypto/hmac.c
@@ -90,11 +90,10 @@ QCryptoHmac *qcrypto_hmac_new(QCryptoHashAlgorithm alg,
{
QCryptoHmac *hmac;
void *ctx = NULL;
- Error *err2 = NULL;
QCryptoHmacDriver *drv = NULL;
#ifdef CONFIG_AF_ALG
- ctx = qcrypto_afalg_hmac_ctx_new(alg, key, nkey, &err2);
+ ctx = qcrypto_afalg_hmac_ctx_new(alg, key, nkey, NULL);
if (ctx) {
drv = &qcrypto_hmac_afalg_driver;
}
@@ -107,7 +106,6 @@ QCryptoHmac *qcrypto_hmac_new(QCryptoHashAlgorithm alg,
}
drv = &qcrypto_hmac_lib_driver;
- error_free(err2);
}
hmac = g_new0(QCryptoHmac, 1);
diff --git a/disas.c b/disas.c
index 92b389d25f..d4ad1089ef 100644
--- a/disas.c
+++ b/disas.c
@@ -220,6 +220,77 @@ static cs_err cap_disas_start(disassemble_info *info, csh *handle)
return CS_ERR_OK;
}
+static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn,
+ int i, int n)
+{
+ fprintf_function print = info->fprintf_func;
+ FILE *stream = info->stream;
+
+ switch (info->cap_insn_unit) {
+ case 4:
+ if (info->endian == BFD_ENDIAN_BIG) {
+ for (; i < n; i += 4) {
+ print(stream, " %08x", ldl_be_p(insn->bytes + i));
+
+ }
+ } else {
+ for (; i < n; i += 4) {
+ print(stream, " %08x", ldl_le_p(insn->bytes + i));
+ }
+ }
+ break;
+
+ case 2:
+ if (info->endian == BFD_ENDIAN_BIG) {
+ for (; i < n; i += 2) {
+ print(stream, " %04x", lduw_be_p(insn->bytes + i));
+ }
+ } else {
+ for (; i < n; i += 2) {
+ print(stream, " %04x", lduw_le_p(insn->bytes + i));
+ }
+ }
+ break;
+
+ default:
+ for (; i < n; i++) {
+ print(stream, " %02x", insn->bytes[i]);
+ }
+ break;
+ }
+}
+
+static void cap_dump_insn(disassemble_info *info, cs_insn *insn)
+{
+ fprintf_function print = info->fprintf_func;
+ int i, n, split;
+
+ print(info->stream, "0x%08" PRIx64 ": ", insn->address);
+
+ n = insn->size;
+ split = info->cap_insn_split;
+
+ /* Dump the first SPLIT bytes of the instruction. */
+ cap_dump_insn_units(info, insn, 0, MIN(n, split));
+
+ /* Add padding up to SPLIT so that mnemonics line up. */
+ if (n < split) {
+ int width = (split - n) / info->cap_insn_unit;
+ width *= (2 * info->cap_insn_unit + 1);
+ print(info->stream, "%*s", width, "");
+ }
+
+ /* Print the actual instruction. */
+ print(info->stream, " %-8s %s\n", insn->mnemonic, insn->op_str);
+
+ /* Dump any remaining part of the insn on subsequent lines. */
+ for (i = split; i < n; i += split) {
+ print(info->stream, "0x%08" PRIx64 ": ", insn->address + i);
+ cap_dump_insn_units(info, insn, i, MIN(n, i + split));
+ print(info->stream, "\n");
+ }
+}
+
/* Disassemble SIZE bytes at PC for the target. */
static bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size)
{
@@ -242,10 +313,7 @@ static bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size)
size -= tsize;
while (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
- (*info->fprintf_func)(info->stream,
- "0x%08" PRIx64 ": %-12s %s\n",
- insn->address, insn->mnemonic,
- insn->op_str);
+ cap_dump_insn(info, insn);
}
/* If the target memory is not consumed, go back for more... */
@@ -290,10 +358,7 @@ static bool cap_disas_host(disassemble_info *info, void *code, size_t size)
pc = (uintptr_t)code;
while (cs_disasm_iter(handle, &cbuf, &size, &pc, insn)) {
- (*info->fprintf_func)(info->stream,
- "0x%08" PRIx64 ": %-12s %s\n",
- insn->address, insn->mnemonic,
- insn->op_str);
+ cap_dump_insn(info, insn);
}
if (size != 0) {
(*info->fprintf_func)(info->stream,
@@ -337,10 +402,7 @@ static bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
csize += tsize;
if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
- (*info->fprintf_func)(info->stream,
- "0x%08" PRIx64 ": %-12s %s\n",
- insn->address, insn->mnemonic,
- insn->op_str);
+ cap_dump_insn(info, insn);
if (--count <= 0) {
break;
}
@@ -376,6 +438,8 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
s.info.print_address_func = generic_print_address;
s.info.cap_arch = -1;
s.info.cap_mode = 0;
+ s.info.cap_insn_unit = 4;
+ s.info.cap_insn_split = 4;
#ifdef TARGET_WORDS_BIGENDIAN
s.info.endian = BFD_ENDIAN_BIG;
@@ -427,6 +491,8 @@ void disas(FILE *out, void *code, unsigned long size)
s.info.buffer_length = size;
s.info.cap_arch = -1;
s.info.cap_mode = 0;
+ s.info.cap_insn_unit = 4;
+ s.info.cap_insn_split = 4;
#ifdef HOST_WORDS_BIGENDIAN
s.info.endian = BFD_ENDIAN_BIG;
@@ -440,11 +506,15 @@ void disas(FILE *out, void *code, unsigned long size)
print_insn = print_insn_i386;
s.info.cap_arch = CS_ARCH_X86;
s.info.cap_mode = CS_MODE_32;
+ s.info.cap_insn_unit = 1;
+ s.info.cap_insn_split = 8;
#elif defined(__x86_64__)
s.info.mach = bfd_mach_x86_64;
print_insn = print_insn_i386;
s.info.cap_arch = CS_ARCH_X86;
s.info.cap_mode = CS_MODE_64;
+ s.info.cap_insn_unit = 1;
+ s.info.cap_insn_split = 8;
#elif defined(_ARCH_PPC)
s.info.disassembler_options = (char *)"any";
print_insn = print_insn_ppc;
@@ -537,6 +607,8 @@ void monitor_disas(Monitor *mon, CPUState *cpu,
s.info.buffer_vma = pc;
s.info.cap_arch = -1;
s.info.cap_mode = 0;
+ s.info.cap_insn_unit = 4;
+ s.info.cap_insn_split = 4;
#ifdef TARGET_WORDS_BIGENDIAN
s.info.endian = BFD_ENDIAN_BIG;
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 6eddac911e..7f1822421a 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -1758,7 +1758,7 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
dc->reset = sm501_reset_sysbus;
dc->vmsd = &vmstate_sm501_sysbus;
/* Note: pointer property "chr-state" may remain null, thus
- * no need for dc->cannot_instantiate_with_device_add_yet = true;
+ * no need for dc->user_creatable = false;
*/
}
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 9178e70132..5cf0dabef3 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -729,15 +729,13 @@ static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
return dev;
}
-static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params,
- MemoryRegion *ccsr, qemu_irq **irqs)
+static DeviceState *ppce500_init_mpic(MachineState *machine,
+ PPCE500Params *params,
+ MemoryRegion *ccsr,
+ qemu_irq **irqs)
{
- qemu_irq *mpic;
DeviceState *dev = NULL;
SysBusDevice *s;
- int i;
-
- mpic = g_new0(qemu_irq, 256);
if (kvm_enabled()) {
Error *err = NULL;
@@ -756,15 +754,11 @@ static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params,
dev = ppce500_init_mpic_qemu(params, irqs);
}
- for (i = 0; i < 256; i++) {
- mpic[i] = qdev_get_gpio_in(dev, i);
- }
-
s = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
s->mmio[0].memory);
- return mpic;
+ return dev;
}
static void ppce500_power_off(void *opaque, int line, int on)
@@ -796,8 +790,8 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
/* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
* 4 respectively */
unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
- qemu_irq **irqs, *mpic;
- DeviceState *dev;
+ qemu_irq **irqs;
+ DeviceState *dev, *mpicdev;
CPUPPCState *firstenv = NULL;
MemoryRegion *ccsr_addr_space;
SysBusDevice *s;
@@ -866,18 +860,18 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
ccsr_addr_space);
- mpic = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
+ mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
/* Serial */
if (serial_hds[0]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
- 0, mpic[42], 399193,
+ 0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hds[0], DEVICE_BIG_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
- 0, mpic[42], 399193,
+ 0, qdev_get_gpio_in(mpicdev, 42), 399193,
serial_hds[1], DEVICE_BIG_ENDIAN);
}
@@ -895,7 +889,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
for (i = 0; i < PCI_NUM_PINS; i++) {
- sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]);
+ sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
}
memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
@@ -926,7 +920,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
dev = qdev_create(NULL, "mpc8xxx_gpio");
s = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
- sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]);
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
sysbus_mmio_get_region(s, 0));
@@ -946,7 +940,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
for (i = 0; i < params->platform_bus_num_irqs; i++) {
int irqn = params->platform_bus_first_irq + i;
- sysbus_connect_irq(s, i, mpic[irqn]);
+ sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
}
memory_region_add_subregion(address_space_mem,
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
index e7a58e81f7..2b1e1409bf 100644
--- a/hw/s390x/s390-pci-bus.c
+++ b/hw/s390x/s390-pci-bus.c
@@ -715,7 +715,7 @@ static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
pbdev->pdev = pdev;
pbdev->iommu = s390_pci_get_iommu(s, pdev->bus, pdev->devfn);
pbdev->iommu->pbdev = pbdev;
- pbdev->state = ZPCI_FS_STANDBY;
+ pbdev->state = ZPCI_FS_DISABLED;
if (s390_pci_msix_init(pbdev)) {
error_setg(errp, "MSI-X support is mandatory "
diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index 1f88c9e9d5..46c7ec3376 100644
--- a/include/disas/bfd.h
+++ b/include/disas/bfd.h
@@ -374,6 +374,8 @@ typedef struct disassemble_info {
/* Options for Capstone disassembly. */
int cap_arch;
int cap_mode;
+ int cap_insn_unit;
+ int cap_insn_split;
} disassemble_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 47c8b2a85c..7f7a3d1e32 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -489,13 +489,19 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
info->print_insn = print_insn_arm_a64;
#endif
info->cap_arch = CS_ARCH_ARM64;
+ info->cap_insn_unit = 4;
+ info->cap_insn_split = 4;
} else {
int cap_mode;
if (env->thumb) {
info->print_insn = print_insn_thumb1;
+ info->cap_insn_unit = 2;
+ info->cap_insn_split = 4;
cap_mode = CS_MODE_THUMB;
} else {
info->print_insn = print_insn_arm;
+ info->cap_insn_unit = 4;
+ info->cap_insn_split = 4;
cap_mode = CS_MODE_ARM;
}
if (arm_feature(env, ARM_FEATURE_V8)) {
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6f21a5e518..1edcf29e27 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4109,6 +4109,8 @@ static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
: env->hflags & HF_CS32_MASK ? CS_MODE_32
: CS_MODE_16);
+ info->cap_insn_unit = 1;
+ info->cap_insn_split = 8;
}
static Property x86_cpu_properties[] = {
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index f8729fe46d..ad8f93c064 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -141,7 +141,7 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
cpu_synchronize_state(CPU(cpu));
if (kvm_enabled() && cpu->compat_pvr != compat_pvr) {
- int ret = kvmppc_set_compat(cpu, cpu->compat_pvr);
+ int ret = kvmppc_set_compat(cpu, compat_pvr);
if (ret < 0) {
error_setg_errno(errp, -ret,
"Unable to set CPU compatibility mode in KVM");
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index dee72a787d..85d0a6c3af 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3432,6 +3432,7 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
/* Adjust the arguments for the specific insn. */
switch (s->fields->op2) {
case 0x55: /* risbg */
+ case 0x59: /* risbgn */
i3 &= 63;
i4 &= 63;
pmask = ~0;
@@ -3447,7 +3448,7 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
pmask = 0x00000000ffffffffull;
break;
default:
- abort();
+ g_assert_not_reached();
}
/* MASK is the set of bits to be inserted from R2.
@@ -3464,11 +3465,7 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
insns, we need to keep the other half of the register. */
imask = ~mask | ~pmask;
if (do_zero) {
- if (s->fields->op2 == 0x55) {
- imask = 0;
- } else {
- imask = ~pmask;
- }
+ imask = ~pmask;
}
len = i4 - i3 + 1;
diff --git a/tests/test-aio-multithread.c b/tests/test-aio-multithread.c
index 549d784915..d396185972 100644
--- a/tests/test-aio-multithread.c
+++ b/tests/test-aio-multithread.c
@@ -144,17 +144,16 @@ static void finish_cb(void *opaque)
static coroutine_fn void test_multi_co_schedule_entry(void *opaque)
{
g_assert(to_schedule[id] == NULL);
- atomic_mb_set(&to_schedule[id], qemu_coroutine_self());
while (!atomic_mb_read(&now_stopping)) {
int n;
n = g_test_rand_int_range(0, NUM_CONTEXTS);
schedule_next(n);
- qemu_coroutine_yield();
- g_assert(to_schedule[id] == NULL);
atomic_mb_set(&to_schedule[id], qemu_coroutine_self());
+ qemu_coroutine_yield();
+ g_assert(to_schedule[id] == NULL);
}
}
diff --git a/tests/test-crypto-block.c b/tests/test-crypto-block.c
index bd7fe593e3..fd29a045d2 100644
--- a/tests/test-crypto-block.c
+++ b/tests/test-crypto-block.c
@@ -28,7 +28,8 @@
#include <sys/resource.h>
#endif
-#if (defined(_WIN32) || defined RUSAGE_THREAD)
+#if (defined(_WIN32) || defined RUSAGE_THREAD) && \
+ (defined(CONFIG_NETTLE_KDF) || defined(CONFIG_GCRYPT_KDF))
#define TEST_LUKS
#else
#undef TEST_LUKS
diff --git a/util/async.c b/util/async.c
index 355af73ee7..0e1bd8780a 100644
--- a/util/async.c
+++ b/util/async.c
@@ -174,7 +174,7 @@ void qemu_bh_schedule(QEMUBH *bh)
*/
void qemu_bh_cancel(QEMUBH *bh)
{
- bh->scheduled = 0;
+ atomic_mb_set(&bh->scheduled, 0);
}
/* This func is async.The bottom half will do the delete action at the finial
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-27 10:06:46 +0200