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Diffstat (limited to 'hw/display/cirrus_vga.c')
-rw-r--r--hw/display/cirrus_vga.c119
1 files changed, 52 insertions, 67 deletions
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index 1f29731ffe..212d6f5e61 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -35,6 +35,7 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qemu/units.h"
+#include "qemu/log.h"
#include "sysemu/reset.h"
#include "qapi/error.h"
#include "trace.h"
@@ -52,7 +53,6 @@
*/
//#define DEBUG_CIRRUS
-//#define DEBUG_BITBLT
/***************************************
*
@@ -905,9 +905,8 @@ static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
{
/* XXX */
-#ifdef DEBUG_BITBLT
- printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
-#endif
+ qemu_log_mask(LOG_UNIMP,
+ "cirrus: bitblt (video to cpu) is not implemented\n");
return 0;
}
@@ -950,19 +949,16 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
-#ifdef DEBUG_BITBLT
- printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
- blt_rop,
- s->cirrus_blt_mode,
- s->cirrus_blt_modeext,
- s->cirrus_blt_width,
- s->cirrus_blt_height,
- s->cirrus_blt_dstpitch,
- s->cirrus_blt_srcpitch,
- s->cirrus_blt_dstaddr,
- s->cirrus_blt_srcaddr,
- s->vga.gr[0x2f]);
-#endif
+ trace_vga_cirrus_bitblt_start(blt_rop,
+ s->cirrus_blt_mode,
+ s->cirrus_blt_modeext,
+ s->cirrus_blt_width,
+ s->cirrus_blt_height,
+ s->cirrus_blt_dstpitch,
+ s->cirrus_blt_srcpitch,
+ s->cirrus_blt_dstaddr,
+ s->cirrus_blt_srcaddr,
+ s->vga.gr[0x2f]);
switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
@@ -978,9 +974,8 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
s->cirrus_blt_pixelwidth = 4;
break;
default:
-#ifdef DEBUG_BITBLT
- printf("cirrus: bitblt - pixel width is unknown\n");
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: bitblt - pixel width is unknown\n");
goto bitblt_ignore;
}
s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
@@ -989,9 +984,8 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
CIRRUS_BLTMODE_MEMSYSDEST))
== (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
-#ifdef DEBUG_BITBLT
- printf("cirrus: bitblt - memory-to-memory copy is requested\n");
-#endif
+ qemu_log_mask(LOG_UNIMP,
+ "cirrus: bitblt - memory-to-memory copy requested\n");
goto bitblt_ignore;
}
@@ -1038,7 +1032,9 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
} else {
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
if (s->cirrus_blt_pixelwidth > 2) {
- printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: src transparent without colorexpand "
+ "must be 8bpp or 16bpp\n");
goto bitblt_ignore;
}
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
@@ -1136,10 +1132,9 @@ static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
ret = 16;
break; /* XGA HiColor */
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: invalid DAC value %x in 16bpp\n",
- (s->cirrus_hidden_dac_data & 0xf));
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: invalid DAC value 0x%x in 16bpp\n",
+ (s->cirrus_hidden_dac_data & 0xf));
ret = 15; /* XXX */
break;
}
@@ -1308,11 +1303,9 @@ static int cirrus_vga_read_sr(CirrusVGAState * s)
#endif
return s->vga.sr[s->vga.sr_index];
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: inport sr_index 0x%02x\n", s->vga.sr_index);
return 0xff;
- break;
}
}
@@ -1401,10 +1394,9 @@ static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
cirrus_update_memory_access(s);
break;
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: outport sr_index %02x, sr_value %02x\n",
- s->vga.sr_index, val);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: outport sr_index 0x%02x, sr_value 0x%02x\n",
+ s->vga.sr_index, val);
break;
}
}
@@ -1502,9 +1494,8 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
if (reg_index < 0x3a) {
return s->vga.gr[reg_index];
} else {
-#ifdef DEBUG_CIRRUS
- printf("cirrus: inport gr_index %02x\n", reg_index);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: inport gr_index 0x%02x\n", reg_index);
return 0xff;
}
}
@@ -1512,9 +1503,7 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
static void
cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
{
-#if defined(DEBUG_BITBLT) && 0
- printf("gr%02x: %02x\n", reg_index, reg_value);
-#endif
+ trace_vga_cirrus_write_gr(reg_index, reg_value);
switch (reg_index) {
case 0x00: // Standard VGA, BGCOLOR 0x000000ff
s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
@@ -1593,10 +1582,9 @@ cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
cirrus_write_bitblt(s, reg_value);
break;
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
- reg_value);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: outport gr_index 0x%02x, gr_value 0x%02x\n",
+ reg_index, reg_value);
break;
}
}
@@ -1651,9 +1639,8 @@ static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
return s->vga.ar_index & 0x3f;
break;
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: inport cr_index %02x\n", reg_index);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: inport cr_index 0x%02x\n", reg_index);
return 0xff;
}
}
@@ -1724,10 +1711,9 @@ static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
break;
case 0x25: // Part Status
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: outport cr_index %02x, cr_value %02x\n",
- s->vga.cr_index, reg_value);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: outport cr_index 0x%02x, cr_value 0x%02x\n",
+ s->vga.cr_index, reg_value);
break;
}
}
@@ -1837,9 +1823,8 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
value = cirrus_vga_read_gr(s, 0x31);
break;
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: mmio read - address 0x%04x\n", address);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: mmio read - address 0x%04x\n", address);
break;
}
@@ -1949,10 +1934,9 @@ static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
cirrus_vga_write_gr(s, 0x31, value);
break;
default:
-#ifdef DEBUG_CIRRUS
- printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
- address, value);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
+ address, value);
break;
}
}
@@ -2050,9 +2034,8 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
}
} else {
val = 0xff;
-#ifdef DEBUG_CIRRUS
- printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr);
}
return val;
}
@@ -2115,10 +2098,9 @@ static void cirrus_vga_mem_write(void *opaque,
cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
}
} else {
-#ifdef DEBUG_CIRRUS
- printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
- mem_value);
-#endif
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cirrus: mem_writeb 0x" TARGET_FMT_plx " "
+ "value 0x%02" PRIu64 "\n", addr, mem_value);
}
}
@@ -2414,6 +2396,9 @@ static uint64_t cirrus_linear_bitblt_read(void *opaque,
/* XXX handle bitblt */
(void)s;
+ qemu_log_mask(LOG_UNIMP,
+ "cirrus: linear bitblt is not implemented\n");
+
return 0xff;
}
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-01 16:58:33 +0100