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-rw-r--r--hw/i386/Makefile.objs2
-rw-r--r--hw/i386/acpi-build.c366
-rw-r--r--hw/i386/acpi-dsdt-cpu-hotplug.dsl14
-rw-r--r--hw/i386/acpi-dsdt-hpet.dsl3
-rw-r--r--hw/i386/acpi-dsdt-isa.dsl11
-rw-r--r--hw/i386/acpi-dsdt-pci-crs.dsl15
-rw-r--r--hw/i386/acpi-dsdt.dsl76
-rw-r--r--hw/i386/acpi-dsdt.hex.generated217
-rw-r--r--hw/i386/bios-linker-loader.c3
-rw-r--r--hw/i386/kvm/i8254.c8
-rw-r--r--hw/i386/kvm/pci-assign.c1
-rw-r--r--hw/i386/pc.c5
-rw-r--r--hw/i386/pc_piix.c13
-rw-r--r--hw/i386/pc_q35.c20
-rw-r--r--hw/i386/q35-acpi-dsdt.dsl19
-rw-r--r--hw/i386/q35-acpi-dsdt.hex.generated74
-rw-r--r--hw/i386/ssdt-pcihp.dsl11
-rw-r--r--hw/i386/ssdt-pcihp.hex.generated20
-rw-r--r--hw/i386/ssdt-proc.hex.generated6
19 files changed, 663 insertions, 221 deletions
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 09ac433cf9..3df1612651 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -17,7 +17,7 @@ iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
ifdef IASL
#IASL Present. Generate hex files from .dsl
hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.dsl $(SRC_PATH)/scripts/acpi_extract_preprocess.py $(SRC_PATH)/scripts/acpi_extract.py
- $(call quiet-command, cpp -P $< -o $*.dsl.i.orig, " CPP $(TARGET_DIR)$*.dsl.i.orig")
+ $(call quiet-command, cpp -P $(QEMU_DGFLAGS) $(QEMU_INCLUDES) $< -o $*.dsl.i.orig, " CPP $(TARGET_DIR)$*.dsl.i.orig")
$(call quiet-command, $(PYTHON) $(SRC_PATH)/scripts/acpi_extract_preprocess.py $*.dsl.i.orig > $*.dsl.i, " ACPI_PREPROCESS $(TARGET_DIR)$*.dsl.i")
$(call quiet-command, $(IASL) $(call iasl-option,$(IASL),-Pn,) -vs -l -tc -p $* $*.dsl.i $(if $(V), , > /dev/null) 2>&1 ," IASL $(TARGET_DIR)$*.dsl.i")
$(call quiet-command, $(PYTHON) $(SRC_PATH)/scripts/acpi_extract.py $*.lst > $*.off, " ACPI_EXTRACT $(TARGET_DIR)$*.off")
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 48312f5a83..b1a7ebb8e3 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -36,9 +36,11 @@
#include "hw/nvram/fw_cfg.h"
#include "bios-linker-loader.h"
#include "hw/loader.h"
+#include "hw/isa/isa.h"
/* Supported chipsets: */
#include "hw/acpi/piix4.h"
+#include "hw/acpi/pcihp.h"
#include "hw/i386/ich9.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/q35.h"
@@ -78,8 +80,15 @@ typedef struct AcpiMiscInfo {
uint16_t pvpanic_port;
} AcpiMiscInfo;
+typedef struct AcpiBuildPciBusHotplugState {
+ GArray *device_table;
+ GArray *notify_table;
+ struct AcpiBuildPciBusHotplugState *parent;
+} AcpiBuildPciBusHotplugState;
+
static void acpi_get_dsdt(AcpiMiscInfo *info)
{
+ uint16_t *applesmc_sta;
Object *piix = piix4_pm_find();
Object *lpc = ich9_lpc_find();
assert(!!piix != !!lpc);
@@ -87,11 +96,17 @@ static void acpi_get_dsdt(AcpiMiscInfo *info)
if (piix) {
info->dsdt_code = AcpiDsdtAmlCode;
info->dsdt_size = sizeof AcpiDsdtAmlCode;
+ applesmc_sta = piix_dsdt_applesmc_sta;
}
if (lpc) {
info->dsdt_code = Q35AcpiDsdtAmlCode;
info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
+ applesmc_sta = q35_dsdt_applesmc_sta;
}
+
+ /* Patch in appropriate value for AppleSMC _STA */
+ *(uint8_t *)(info->dsdt_code + *applesmc_sta) =
+ applesmc_find() ? 0x0b : 0x00;
}
static
@@ -171,38 +186,6 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
NULL);
}
-static void acpi_get_hotplug_info(AcpiMiscInfo *misc)
-{
- int i;
- PCIBus *bus = find_i440fx();
-
- if (!bus) {
- /* Only PIIX supports ACPI hotplug */
- memset(misc->slot_hotplug_enable, 0, sizeof misc->slot_hotplug_enable);
- return;
- }
-
- memset(misc->slot_hotplug_enable, 0xff,
- DIV_ROUND_UP(PCI_SLOT_MAX, BITS_PER_BYTE));
-
- for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
- PCIDeviceClass *pc;
- PCIDevice *pdev = bus->devices[i];
-
- if (!pdev) {
- continue;
- }
-
- pc = PCI_DEVICE_GET_CLASS(pdev);
-
- if (pc->no_hotplug) {
- int slot = PCI_SLOT(i);
-
- clear_bit(slot, misc->slot_hotplug_enable);
- }
- }
-}
-
static void acpi_get_misc_info(AcpiMiscInfo *info)
{
info->has_hpet = hpet_find();
@@ -368,6 +351,12 @@ static void build_package(GArray *package, uint8_t op, unsigned min_bytes)
build_prepend_byte(package, op);
}
+static void build_extop_package(GArray *package, uint8_t op)
+{
+ build_package(package, op, 1);
+ build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
+}
+
static void build_append_value(GArray *table, uint32_t value, int size)
{
uint8_t prefix;
@@ -394,8 +383,44 @@ static void build_append_value(GArray *table, uint32_t value, int size)
}
}
-static void build_append_notify_target(GArray *method, GArray *target_name,
- uint32_t value, int size)
+static void build_append_int(GArray *table, uint32_t value)
+{
+ if (value == 0x00) {
+ build_append_byte(table, 0x00); /* ZeroOp */
+ } else if (value == 0x01) {
+ build_append_byte(table, 0x01); /* OneOp */
+ } else if (value <= 0xFF) {
+ build_append_value(table, value, 1);
+ } else if (value <= 0xFFFFF) {
+ build_append_value(table, value, 2);
+ } else {
+ build_append_value(table, value, 4);
+ }
+}
+
+static GArray *build_alloc_method(const char *name, uint8_t arg_count)
+{
+ GArray *method = build_alloc_array();
+
+ build_append_nameseg(method, "%s", name);
+ build_append_byte(method, arg_count); /* MethodFlags: ArgCount */
+
+ return method;
+}
+
+static void build_append_and_cleanup_method(GArray *device, GArray *method)
+{
+ uint8_t op = 0x14; /* MethodOp */
+
+ build_package(method, op, 0);
+
+ build_append_array(device, method);
+ build_free_array(method);
+}
+
+static void build_append_notify_target_ifequal(GArray *method,
+ GArray *target_name,
+ uint32_t value, int size)
{
GArray *notify = build_alloc_array();
uint8_t op = 0xA0; /* IfOp */
@@ -415,6 +440,7 @@ static void build_append_notify_target(GArray *method, GArray *target_name,
build_free_array(notify);
}
+/* End here */
#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
static inline void *acpi_data_push(GArray *table_data, unsigned size)
@@ -624,44 +650,238 @@ static inline char acpi_get_hex(uint32_t val)
#include "hw/i386/ssdt-pcihp.hex"
static void
-build_append_notify(GArray *device, const char *name,
- const char *format, int skip, int count)
+build_append_notify_method(GArray *device, const char *name,
+ const char *format, int count)
{
int i;
- GArray *method = build_alloc_array();
- uint8_t op = 0x14; /* MethodOp */
+ GArray *method = build_alloc_method(name, 2);
- build_append_nameseg(method, "%s", name);
- build_append_byte(method, 0x02); /* MethodFlags: ArgCount */
- for (i = skip; i < count; i++) {
+ for (i = 0; i < count; i++) {
GArray *target = build_alloc_array();
build_append_nameseg(target, format, i);
assert(i < 256); /* Fits in 1 byte */
- build_append_notify_target(method, target, i, 1);
+ build_append_notify_target_ifequal(method, target, i, 1);
build_free_array(target);
}
- build_package(method, op, 2);
- build_append_array(device, method);
- build_free_array(method);
+ build_append_and_cleanup_method(device, method);
}
-static void patch_pcihp(int slot, uint8_t *ssdt_ptr, uint32_t eject)
+static void patch_pcihp(int slot, uint8_t *ssdt_ptr)
{
- ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(slot >> 4);
- ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(slot);
+ unsigned devfn = PCI_DEVFN(slot, 0);
+
+ ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
+ ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
+}
+
+/* Assign BSEL property to all buses. In the future, this can be changed
+ * to only assign to buses that support hotplug.
+ */
+static void *acpi_set_bsel(PCIBus *bus, void *opaque)
+{
+ unsigned *bsel_alloc = opaque;
+ unsigned *bus_bsel;
+
+ if (bus->qbus.allow_hotplug) {
+ bus_bsel = g_malloc(sizeof *bus_bsel);
- /* Runtime patching of ACPI_EJ0: to disable hotplug for a slot,
- * replace the method name: _EJ0 by ACPI_EJ0_.
+ *bus_bsel = (*bsel_alloc)++;
+ object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
+ bus_bsel, NULL);
+ }
+
+ return bsel_alloc;
+}
+
+static void acpi_set_pci_info(void)
+{
+ PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
+ unsigned bsel_alloc = 0;
+
+ if (bus) {
+ /* Scan all PCI buses. Set property to enable acpi based hotplug. */
+ pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
+ }
+}
+
+static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state,
+ AcpiBuildPciBusHotplugState *parent)
+{
+ state->parent = parent;
+ state->device_table = build_alloc_array();
+ state->notify_table = build_alloc_array();
+}
+
+static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state)
+{
+ build_free_array(state->device_table);
+ build_free_array(state->notify_table);
+}
+
+static void *build_pci_bus_begin(PCIBus *bus, void *parent_state)
+{
+ AcpiBuildPciBusHotplugState *parent = parent_state;
+ AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child);
+
+ build_pci_bus_state_init(child, parent);
+
+ return child;
+}
+
+static void build_pci_bus_end(PCIBus *bus, void *bus_state)
+{
+ AcpiBuildPciBusHotplugState *child = bus_state;
+ AcpiBuildPciBusHotplugState *parent = child->parent;
+ GArray *bus_table = build_alloc_array();
+ DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
+ uint8_t op;
+ int i;
+ QObject *bsel;
+ GArray *method;
+ bool bus_hotplug_support = false;
+
+ if (bus->parent_dev) {
+ op = 0x82; /* DeviceOp */
+ build_append_nameseg(bus_table, "S%.02X_",
+ bus->parent_dev->devfn);
+ build_append_byte(bus_table, 0x08); /* NameOp */
+ build_append_nameseg(bus_table, "_SUN");
+ build_append_value(bus_table, PCI_SLOT(bus->parent_dev->devfn), 1);
+ build_append_byte(bus_table, 0x08); /* NameOp */
+ build_append_nameseg(bus_table, "_ADR");
+ build_append_value(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) |
+ PCI_FUNC(bus->parent_dev->devfn), 4);
+ } else {
+ op = 0x10; /* ScopeOp */;
+ build_append_nameseg(bus_table, "PCI0");
+ }
+
+ bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
+ if (bsel) {
+ build_append_byte(bus_table, 0x08); /* NameOp */
+ build_append_nameseg(bus_table, "BSEL");
+ build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel)));
+
+ memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable);
+
+ for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
+ DeviceClass *dc;
+ PCIDeviceClass *pc;
+ PCIDevice *pdev = bus->devices[i];
+
+ if (!pdev) {
+ continue;
+ }
+
+ pc = PCI_DEVICE_GET_CLASS(pdev);
+ dc = DEVICE_GET_CLASS(pdev);
+
+ if (!dc->hotpluggable || pc->is_bridge) {
+ int slot = PCI_SLOT(i);
+
+ clear_bit(slot, slot_hotplug_enable);
+ }
+ }
+
+ /* Append Device object for each slot which supports eject */
+ for (i = 0; i < PCI_SLOT_MAX; i++) {
+ bool can_eject = test_bit(i, slot_hotplug_enable);
+ if (can_eject) {
+ void *pcihp = acpi_data_push(bus_table,
+ ACPI_PCIHP_SIZEOF);
+ memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
+ patch_pcihp(i, pcihp);
+ bus_hotplug_support = true;
+ }
+ }
+
+ method = build_alloc_method("DVNT", 2);
+
+ for (i = 0; i < PCI_SLOT_MAX; i++) {
+ GArray *notify;
+ uint8_t op;
+
+ if (!test_bit(i, slot_hotplug_enable)) {
+ continue;
+ }
+
+ notify = build_alloc_array();
+ op = 0xA0; /* IfOp */
+
+ build_append_byte(notify, 0x7B); /* AndOp */
+ build_append_byte(notify, 0x68); /* Arg0Op */
+ build_append_int(notify, 0x1 << i);
+ build_append_byte(notify, 0x00); /* NullName */
+ build_append_byte(notify, 0x86); /* NotifyOp */
+ build_append_nameseg(notify, "S%.02X_", PCI_DEVFN(i, 0));
+ build_append_byte(notify, 0x69); /* Arg1Op */
+
+ /* Pack it up */
+ build_package(notify, op, 0);
+
+ build_append_array(method, notify);
+
+ build_free_array(notify);
+ }
+
+ build_append_and_cleanup_method(bus_table, method);
+ }
+
+ /* Append PCNT method to notify about events on local and child buses.
+ * Add unconditionally for root since DSDT expects it.
*/
- /* Sanity check */
- assert(!memcmp(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "_EJ0", 4));
+ if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) {
+ method = build_alloc_method("PCNT", 0);
+
+ /* If bus supports hotplug select it and notify about local events */
+ if (bsel) {
+ build_append_byte(method, 0x70); /* StoreOp */
+ build_append_int(method, qint_get_int(qobject_to_qint(bsel)));
+ build_append_nameseg(method, "BNUM");
+ build_append_nameseg(method, "DVNT");
+ build_append_nameseg(method, "PCIU");
+ build_append_int(method, 1); /* Device Check */
+ build_append_nameseg(method, "DVNT");
+ build_append_nameseg(method, "PCID");
+ build_append_int(method, 3); /* Eject Request */
+ }
+
+ /* Notify about child bus events in any case */
+ build_append_array(method, child->notify_table);
+
+ build_append_and_cleanup_method(bus_table, method);
+
+ /* Append description of child buses */
+ build_append_array(bus_table, child->device_table);
+
+ /* Pack it up */
+ if (bus->parent_dev) {
+ build_extop_package(bus_table, op);
+ } else {
+ build_package(bus_table, op, 0);
+ }
- if (!eject) {
- memcpy(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "EJ0_", 4);
+ /* Append our bus description to parent table */
+ build_append_array(parent->device_table, bus_table);
+
+ /* Also tell parent how to notify us, invoking PCNT method.
+ * At the moment this is not needed for root as we have a single root.
+ */
+ if (bus->parent_dev) {
+ build_append_byte(parent->notify_table, '^'); /* ParentPrefixChar */
+ build_append_byte(parent->notify_table, 0x2E); /* DualNamePrefix */
+ build_append_nameseg(parent->notify_table, "S%.02X_",
+ bus->parent_dev->devfn);
+ build_append_nameseg(parent->notify_table, "PCNT");
+ }
}
+
+ build_free_array(bus_table);
+ build_pci_bus_state_cleanup(child);
+ g_free(child);
}
static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
@@ -733,7 +953,7 @@ build_ssdt(GArray *table_data, GArray *linker,
* Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
*/
/* Arg0 = Processor ID = APIC ID */
- build_append_notify(sb_scope, "NTFY", "CP%0.02X", 0, acpi_cpus);
+ build_append_notify_method(sb_scope, "NTFY", "CP%0.02X", acpi_cpus);
/* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" */
build_append_byte(sb_scope, 0x08); /* NameOp */
@@ -755,24 +975,19 @@ build_ssdt(GArray *table_data, GArray *linker,
}
{
- GArray *pci0 = build_alloc_array();
- uint8_t op = 0x10; /* ScopeOp */;
+ AcpiBuildPciBusHotplugState hotplug_state;
+ PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
- build_append_nameseg(pci0, "PCI0");
+ build_pci_bus_state_init(&hotplug_state, NULL);
- /* build Device object for each slot */
- for (i = 1; i < PCI_SLOT_MAX; i++) {
- bool eject = test_bit(i, misc->slot_hotplug_enable);
- void *pcihp = acpi_data_push(pci0, ACPI_PCIHP_SIZEOF);
-
- memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
- patch_pcihp(i, pcihp, eject);
+ if (bus) {
+ /* Scan all PCI buses. Generate tables to support hotplug. */
+ pci_for_each_bus_depth_first(bus, build_pci_bus_begin,
+ build_pci_bus_end, &hotplug_state);
}
- build_append_notify(pci0, "PCNT", "S%0.02X_", 1, PCI_SLOT_MAX);
- build_package(pci0, op, 3);
- build_append_array(sb_scope, pci0);
- build_free_array(pci0);
+ build_append_array(sb_scope, hotplug_state.device_table);
+ build_pci_bus_state_cleanup(&hotplug_state);
}
build_package(sb_scope, op, 3);
@@ -867,16 +1082,16 @@ build_srat(GArray *table_data, GArray *linker,
next_base = mem_base + mem_len;
/* Cut out the ACPI_PCI hole */
- if (mem_base <= guest_info->ram_size &&
- next_base > guest_info->ram_size) {
- mem_len -= next_base - guest_info->ram_size;
+ if (mem_base <= guest_info->ram_size_below_4g &&
+ next_base > guest_info->ram_size_below_4g) {
+ mem_len -= next_base - guest_info->ram_size_below_4g;
if (mem_len > 0) {
numamem = acpi_data_push(table_data, sizeof *numamem);
acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
}
mem_base = 1ULL << 32;
- mem_len = next_base - guest_info->ram_size;
- next_base += (1ULL << 32) - guest_info->ram_size;
+ mem_len = next_base - guest_info->ram_size_below_4g;
+ next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
}
numamem = acpi_data_push(table_data, sizeof *numamem);
acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1);
@@ -1055,7 +1270,6 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_get_cpu_info(&cpu);
acpi_get_pm_info(&pm);
acpi_get_dsdt(&misc);
- acpi_get_hotplug_info(&misc);
acpi_get_misc_info(&misc);
acpi_get_pci_info(&pci);
@@ -1200,6 +1414,8 @@ void acpi_setup(PcGuestInfo *guest_info)
build_state->guest_info = guest_info;
+ acpi_set_pci_info();
+
acpi_build_tables_init(&tables);
acpi_build(build_state->guest_info, &tables);
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index 995b415bae..dee4843cde 100644
--- a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -16,6 +16,7 @@
/****************************************************************
* CPU hotplug
****************************************************************/
+#define CPU_HOTPLUG_RESOURCE_DEVICE PRES
Scope(\_SB) {
/* Objects filled in by run-time generated SSDT */
@@ -52,7 +53,8 @@ Scope(\_SB) {
Sleep(200)
}
- OperationRegion(PRST, SystemIO, 0xaf00, 32)
+#define CPU_STATUS_LEN ACPI_GPE_PROC_LEN
+ OperationRegion(PRST, SystemIO, CPU_STATUS_BASE, CPU_STATUS_LEN)
Field(PRST, ByteAcc, NoLock, Preserve) {
PRS, 256
}
@@ -89,4 +91,14 @@ Scope(\_SB) {
Increment(Local0)
}
}
+
+ Device(CPU_HOTPLUG_RESOURCE_DEVICE) {
+ Name(_HID, "ACPI0004")
+
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, CPU_STATUS_BASE, CPU_STATUS_BASE, 0, CPU_STATUS_LEN)
+ })
+
+ Name(_STA, 0xB) /* present, functioning, decoding, not shown in UI */
+ }
}
diff --git a/hw/i386/acpi-dsdt-hpet.dsl b/hw/i386/acpi-dsdt-hpet.dsl
index dfde174317..44961b87a1 100644
--- a/hw/i386/acpi-dsdt-hpet.dsl
+++ b/hw/i386/acpi-dsdt-hpet.dsl
@@ -39,9 +39,6 @@ Scope(\_SB) {
Return (0x0F)
}
Name(_CRS, ResourceTemplate() {
-#if 0 /* This makes WinXP BSOD for not yet figured reasons. */
- IRQNoFlags() {2, 8}
-#endif
Memory32Fixed(ReadOnly,
0xFED00000, // Address Base
0x00000400, // Address Length
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
index 89caa1649d..deb37de92e 100644
--- a/hw/i386/acpi-dsdt-isa.dsl
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -16,6 +16,17 @@
/* Common legacy ISA style devices. */
Scope(\_SB.PCI0.ISA) {
+ Device (SMC) {
+ Name(_HID, EisaId("APP0001"))
+ /* _STA will be patched to 0x0B if AppleSMC is present */
+ ACPI_EXTRACT_NAME_BYTE_CONST DSDT_APPLESMC_STA
+ Name(_STA, 0xF0)
+ Name(_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0300, 0x0300, 0x01, 0x20)
+ IRQNoFlags() { 6 }
+ })
+ }
+
Device(RTC) {
Name(_HID, EisaId("PNP0B00"))
Name(_CRS, ResourceTemplate() {
diff --git a/hw/i386/acpi-dsdt-pci-crs.dsl b/hw/i386/acpi-dsdt-pci-crs.dsl
index b375a19cf6..4648e90366 100644
--- a/hw/i386/acpi-dsdt-pci-crs.dsl
+++ b/hw/i386/acpi-dsdt-pci-crs.dsl
@@ -30,20 +30,7 @@ Scope(\_SB.PCI0) {
0x01, // Address Alignment
0x08, // Address Length
)
- WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0D00, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0xF300, // Address Length
- ,, , TypeStatic)
+ BOARD_SPECIFIC_PCI_RESOURSES
DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x000A0000, // Address Range Minimum
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index a377424f39..b23d5e0eac 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -35,6 +35,45 @@ DefinitionBlock (
/****************************************************************
* PCI Bus definition
****************************************************************/
+#define BOARD_SPECIFIC_PCI_RESOURSES \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0x0000, \
+ 0x0CF7, \
+ 0x0000, \
+ 0x0CF8, \
+ ,, , TypeStatic) \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0x0D00, \
+ 0xADFF, \
+ 0x0000, \
+ 0xA100, \
+ ,, , TypeStatic) \
+ /* 0xae00-0xae0e hole for PCI hotplug, hw/acpi/piix4.c:PCI_HOTPLUG_ADDR */ \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0xAE0F, \
+ 0xAEFF, \
+ 0x0000, \
+ 0x00F1, \
+ ,, , TypeStatic) \
+ /* 0xaf00-0xaf1f hole for CPU hotplug, hw/acpi/piix4.c:PIIX4_PROC_BASE */ \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0xAF20, \
+ 0xAFDF, \
+ 0x0000, \
+ 0x00C0, \
+ ,, , TypeStatic) \
+ /* 0xafe0-0xafe3 hole for ACPI.GPE0, hw/acpi/piix4.c:GPE_BASE */ \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0xAFE4, \
+ 0xFFFF, \
+ 0x0000, \
+ 0x501C, \
+ ,, , TypeStatic)
Scope(\_SB) {
Device(PCI0) {
@@ -114,6 +153,7 @@ DefinitionBlock (
}
}
+#define DSDT_APPLESMC_STA piix_dsdt_applesmc_sta
#include "acpi-dsdt-isa.dsl"
@@ -133,32 +173,28 @@ DefinitionBlock (
B0EJ, 32,
}
+ OperationRegion(BNMR, SystemIO, 0xae10, 0x04)
+ Field(BNMR, DWordAcc, NoLock, WriteAsZeros) {
+ BNUM, 32,
+ }
+
+ /* Lock to protect access to fields above. */
+ Mutex(BLCK, 0)
+
/* Methods called by bulk generated PCI devices below */
/* Methods called by hotplug devices */
- Method(PCEJ, 1, NotSerialized) {
+ Method(PCEJ, 2, NotSerialized) {
// _EJ0 method - eject callback
- Store(ShiftLeft(1, Arg0), B0EJ)
+ Acquire(BLCK, 0xFFFF)
+ Store(Arg0, BNUM)
+ Store(ShiftLeft(1, Arg1), B0EJ)
+ Release(BLCK)
Return (0x0)
}
/* Hotplug notification method supplied by SSDT */
External(\_SB.PCI0.PCNT, MethodObj)
-
- /* PCI hotplug notify method */
- Method(PCNF, 0) {
- // Local0 = iterator
- Store(Zero, Local0)
- While (LLess(Local0, 31)) {
- Increment(Local0)
- If (And(PCIU, ShiftLeft(1, Local0))) {
- PCNT(Local0, 1)
- }
- If (And(PCID, ShiftLeft(1, Local0))) {
- PCNT(Local0, 3)
- }
- }
- }
}
@@ -293,6 +329,8 @@ DefinitionBlock (
}
}
+#include "hw/acpi/cpu_hotplug_defs.h"
+#define CPU_STATUS_BASE PIIX4_CPU_HOTPLUG_IO_BASE
#include "acpi-dsdt-cpu-hotplug.dsl"
@@ -307,7 +345,9 @@ DefinitionBlock (
}
Method(_E01) {
// PCI hotplug event
- \_SB.PCI0.PCNF()
+ Acquire(\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT()
+ Release(\_SB.PCI0.BLCK)
}
Method(_E02) {
// CPU hotplug event
diff --git a/hw/i386/acpi-dsdt.hex.generated b/hw/i386/acpi-dsdt.hex.generated
index f8bd4ea1b5..1e58801b2a 100644
--- a/hw/i386/acpi-dsdt.hex.generated
+++ b/hw/i386/acpi-dsdt.hex.generated
@@ -3,12 +3,12 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x53,
0x44,
0x54,
-0x37,
+0x87,
0x11,
0x0,
0x0,
0x1,
-0xd8,
+0xb8,
0x42,
0x58,
0x50,
@@ -860,8 +860,8 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x4e,
0x1,
0x10,
-0x4c,
-0x1b,
+0x4b,
+0x1e,
0x2f,
0x3,
0x5f,
@@ -879,6 +879,53 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x5b,
0x82,
0x2d,
+0x53,
+0x4d,
+0x43,
+0x5f,
+0x8,
+0x5f,
+0x48,
+0x49,
+0x44,
+0xc,
+0x6,
+0x10,
+0x0,
+0x1,
+0x8,
+0x5f,
+0x53,
+0x54,
+0x41,
+0xb,
+0x0,
+0xff,
+0x8,
+0x5f,
+0x43,
+0x52,
+0x53,
+0x11,
+0x10,
+0xa,
+0xd,
+0x47,
+0x1,
+0x0,
+0x3,
+0x0,
+0x3,
+0x1,
+0x20,
+0x22,
+0x40,
+0x0,
+0x79,
+0x0,
+0x5b,
+0x82,
+0x2d,
0x52,
0x54,
0x43,
@@ -1305,7 +1352,7 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x79,
0x0,
0x10,
-0x4b,
+0x48,
0x8,
0x2e,
0x5f,
@@ -1371,79 +1418,76 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x45,
0x4a,
0x20,
+0x5b,
+0x80,
+0x42,
+0x4e,
+0x4d,
+0x52,
+0x1,
+0xb,
+0x10,
+0xae,
+0xa,
+0x4,
+0x5b,
+0x81,
+0xb,
+0x42,
+0x4e,
+0x4d,
+0x52,
+0x43,
+0x42,
+0x4e,
+0x55,
+0x4d,
+0x20,
+0x5b,
+0x1,
+0x42,
+0x4c,
+0x43,
+0x4b,
+0x0,
0x14,
-0x11,
+0x25,
0x50,
0x43,
0x45,
0x4a,
-0x1,
+0x2,
+0x5b,
+0x23,
+0x42,
+0x4c,
+0x43,
+0x4b,
+0xff,
+0xff,
0x70,
-0x79,
-0x1,
0x68,
-0x0,
0x42,
-0x30,
-0x45,
-0x4a,
-0xa4,
-0x0,
-0x14,
-0x36,
-0x50,
-0x43,
0x4e,
-0x46,
-0x0,
-0x70,
-0x0,
-0x60,
-0xa2,
-0x2c,
-0x95,
-0x60,
-0xa,
-0x1f,
-0x75,
-0x60,
-0xa0,
-0x11,
-0x7b,
-0x50,
-0x43,
-0x49,
0x55,
+0x4d,
+0x70,
0x79,
0x1,
-0x60,
+0x69,
0x0,
-0x0,
-0x50,
-0x43,
-0x4e,
-0x54,
-0x60,
-0x1,
-0xa0,
-0x12,
-0x7b,
-0x50,
+0x42,
+0x30,
+0x45,
+0x4a,
+0x5b,
+0x27,
+0x42,
+0x4c,
0x43,
-0x49,
-0x44,
-0x79,
-0x1,
-0x60,
-0x0,
+0x4b,
+0xa4,
0x0,
-0x50,
-0x43,
-0x4e,
-0x54,
-0x60,
-0xa,
-0x3,
0x10,
0x4a,
0xa0,
@@ -4248,8 +4292,8 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x75,
0x60,
0x10,
-0x4e,
-0x9,
+0x42,
+0xc,
0x5f,
0x47,
0x50,
@@ -4277,12 +4321,31 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x30,
0x0,
0x14,
-0x15,
+0x39,
0x5f,
0x45,
0x30,
0x31,
0x0,
+0x5b,
+0x23,
+0x5c,
+0x2f,
+0x3,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x50,
+0x43,
+0x49,
+0x30,
+0x42,
+0x4c,
+0x43,
+0x4b,
+0xff,
+0xff,
0x5c,
0x2f,
0x3,
@@ -4297,7 +4360,24 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x50,
0x43,
0x4e,
-0x46,
+0x54,
+0x5b,
+0x27,
+0x5c,
+0x2f,
+0x3,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x50,
+0x43,
+0x49,
+0x30,
+0x42,
+0x4c,
+0x43,
+0x4b,
0x14,
0x10,
0x5f,
@@ -4407,3 +4487,6 @@ static unsigned char AcpiDsdtAmlCode[] = {
0x46,
0x0
};
+static unsigned short piix_dsdt_applesmc_sta[] = {
+0x384
+};
diff --git a/hw/i386/bios-linker-loader.c b/hw/i386/bios-linker-loader.c
index fd23611008..aa56184e9a 100644
--- a/hw/i386/bios-linker-loader.c
+++ b/hw/i386/bios-linker-loader.c
@@ -18,11 +18,10 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu-common.h"
#include "bios-linker-loader.h"
#include "hw/nvram/fw_cfg.h"
-#include <string.h>
-#include <assert.h>
#include "qemu/bswap.h"
#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c
index 20b6457fbd..59373aaade 100644
--- a/hw/i386/kvm/i8254.c
+++ b/hw/i386/kvm/i8254.c
@@ -268,9 +268,9 @@ static void kvm_pit_realizefn(DeviceState *dev, Error **errp)
return;
}
switch (s->lost_tick_policy) {
- case LOST_TICK_DELAY:
+ case LOST_TICK_POLICY_DELAY:
break; /* enabled by default */
- case LOST_TICK_DISCARD:
+ case LOST_TICK_POLICY_DISCARD:
if (kvm_check_extension(kvm_state, KVM_CAP_REINJECT_CONTROL)) {
struct kvm_reinject_control control = { .pit_reinject = 0 };
@@ -298,9 +298,9 @@ static void kvm_pit_realizefn(DeviceState *dev, Error **errp)
}
static Property kvm_pit_properties[] = {
- DEFINE_PROP_HEX32("iobase", PITCommonState, iobase, -1),
+ DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", KVMPITState,
- lost_tick_policy, LOST_TICK_DELAY),
+ lost_tick_policy, LOST_TICK_POLICY_DELAY),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/i386/kvm/pci-assign.c b/hw/i386/kvm/pci-assign.c
index 968680104b..a825871d8a 100644
--- a/hw/i386/kvm/pci-assign.c
+++ b/hw/i386/kvm/pci-assign.c
@@ -743,6 +743,7 @@ static void assign_failed_examine(AssignedDevice *dev)
goto fail;
}
+ driver[r] = 0;
ns = strrchr(driver, '/');
if (!ns) {
goto fail;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6f0be37d8b..e715a3312d 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -835,8 +835,8 @@ static void load_linux(FWCfgState *fw_cfg,
initrd_size = get_image_size(initrd_filename);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: error reading initrd %s\n",
- initrd_filename);
+ fprintf(stderr, "qemu: error reading initrd %s: %s\n",
+ initrd_filename, strerror(errno));
exit(1);
}
@@ -1072,6 +1072,7 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
PcGuestInfo *guest_info = &guest_info_state->info;
int i, j;
+ guest_info->ram_size_below_4g = below_4g_mem_size;
guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
guest_info->apic_xrupt_override = kvm_allows_irq0_override();
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index a327d71fb1..d5dc1ef336 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -236,7 +236,7 @@ static void pc_init1(QEMUMachineInitArgs *args,
}
if (pci_enabled && acpi_enabled) {
- i2c_bus *smbus;
+ I2CBus *smbus;
smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
/* TODO: Populate SPD eeprom data. */
@@ -793,6 +793,17 @@ static QEMUMachine xenfv_machine = {
.max_cpus = HVM_MAX_VCPUS,
.default_machine_opts = "accel=xen",
.hot_add_cpu = pc_hot_add_cpu,
+ .compat_props = (GlobalProperty[]) {
+ /* xenfv has no fwcfg and so does not load acpi from QEMU.
+ * as such new acpi features don't work.
+ */
+ {
+ .driver = "PIIX4_PM",
+ .property = "acpi-pci-hotplug-with-bridge-support",
+ .value = "off",
+ },
+ { /* end of list */ }
+ },
};
#endif
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 07f38ff704..a7f626096a 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -51,6 +51,11 @@
static bool has_pci_info;
static bool has_acpi_build = true;
static bool smbios_type1_defaults = true;
+/* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
+ * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
+ * pages in the host.
+ */
+static bool gigabyte_align = true;
/* PC hardware initialisation */
static void pc_q35_init(QEMUMachineInitArgs *args)
@@ -92,9 +97,19 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
kvmclock_create();
+ /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
+ * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
+ * also known as MMCFG).
+ * If it doesn't, we need to split it in chunks below and above 4G.
+ * In any case, try to make sure that guest addresses aligned at
+ * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
+ * For old machine types, use whatever split we used historically to avoid
+ * breaking migration.
+ */
if (args->ram_size >= 0xb0000000) {
- above_4g_mem_size = args->ram_size - 0xb0000000;
- below_4g_mem_size = 0xb0000000;
+ ram_addr_t lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
+ above_4g_mem_size = args->ram_size - lowmem;
+ below_4g_mem_size = lowmem;
} else {
above_4g_mem_size = 0;
below_4g_mem_size = args->ram_size;
@@ -228,6 +243,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
static void pc_compat_1_7(QEMUMachineInitArgs *args)
{
smbios_type1_defaults = false;
+ gigabyte_align = false;
}
static void pc_compat_1_6(QEMUMachineInitArgs *args)
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 7934a9ddfb..d618e9e2d2 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -48,6 +48,22 @@ DefinitionBlock (
/****************************************************************
* PCI Bus definition
****************************************************************/
+#define BOARD_SPECIFIC_PCI_RESOURSES \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0x0000, \
+ 0x0CD7, \
+ 0x0000, \
+ 0x0CD8, \
+ ,, , TypeStatic) \
+ /* 0xcd8-0xcf7 hole for CPU hotplug, hw/acpi/ich9.c:ICH9_PROC_BASE */ \
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \
+ 0x0000, \
+ 0x0D00, \
+ 0xFFFF, \
+ 0x0000, \
+ 0xF300, \
+ ,, , TypeStatic)
Scope(\_SB) {
Device(PCI0) {
@@ -171,6 +187,7 @@ DefinitionBlock (
}
}
+#define DSDT_APPLESMC_STA q35_dsdt_applesmc_sta
#include "acpi-dsdt-isa.dsl"
@@ -404,6 +421,8 @@ DefinitionBlock (
define_gsi_link(GSIH, 0, 0x17)
}
+#include "hw/acpi/cpu_hotplug_defs.h"
+#define CPU_STATUS_BASE ICH9_CPU_HOTPLUG_IO_BASE
#include "acpi-dsdt-cpu-hotplug.dsl"
diff --git a/hw/i386/q35-acpi-dsdt.hex.generated b/hw/i386/q35-acpi-dsdt.hex.generated
index 111ad3e9c2..6d885a9055 100644
--- a/hw/i386/q35-acpi-dsdt.hex.generated
+++ b/hw/i386/q35-acpi-dsdt.hex.generated
@@ -3,12 +3,12 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x53,
0x44,
0x54,
-0xb0,
+0xdf,
0x1c,
0x0,
0x0,
0x1,
-0xfe,
+0xff,
0x42,
0x58,
0x50,
@@ -1033,8 +1033,8 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x4e,
0x1,
0x10,
-0x4c,
-0x1b,
+0x4b,
+0x1e,
0x2f,
0x3,
0x5f,
@@ -1052,6 +1052,53 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x5b,
0x82,
0x2d,
+0x53,
+0x4d,
+0x43,
+0x5f,
+0x8,
+0x5f,
+0x48,
+0x49,
+0x44,
+0xc,
+0x6,
+0x10,
+0x0,
+0x1,
+0x8,
+0x5f,
+0x53,
+0x54,
+0x41,
+0xb,
+0x0,
+0xff,
+0x8,
+0x5f,
+0x43,
+0x52,
+0x53,
+0x11,
+0x10,
+0xa,
+0xd,
+0x47,
+0x1,
+0x0,
+0x3,
+0x0,
+0x3,
+0x1,
+0x20,
+0x22,
+0x40,
+0x0,
+0x79,
+0x0,
+0x5b,
+0x82,
+0x2d,
0x52,
0x54,
0x43,
@@ -7229,12 +7276,19 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x30,
0x0,
0x14,
-0x10,
+0x6,
0x5f,
0x4c,
0x30,
0x31,
0x0,
+0x14,
+0x10,
+0x5f,
+0x45,
+0x30,
+0x32,
+0x0,
0x5c,
0x2e,
0x5f,
@@ -7250,13 +7304,6 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x5f,
0x4c,
0x30,
-0x32,
-0x0,
-0x14,
-0x6,
-0x5f,
-0x4c,
-0x30,
0x33,
0x0,
0x14,
@@ -7344,3 +7391,6 @@ static unsigned char Q35AcpiDsdtAmlCode[] = {
0x46,
0x0
};
+static unsigned short q35_dsdt_applesmc_sta[] = {
+0x431
+};
diff --git a/hw/i386/ssdt-pcihp.dsl b/hw/i386/ssdt-pcihp.dsl
index d29a5b95d2..cc245c3e7c 100644
--- a/hw/i386/ssdt-pcihp.dsl
+++ b/hw/i386/ssdt-pcihp.dsl
@@ -25,6 +25,7 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
/* Objects supplied by DSDT */
External(\_SB.PCI0, DeviceObj)
External(\_SB.PCI0.PCEJ, MethodObj)
+ External(BSEL, IntObj)
Scope(\_SB.PCI0) {
@@ -33,19 +34,17 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end
ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name
- // Method _EJ0 can be patched by BIOS to EJ0_
- // at runtime, if the slot is detected to not support hotplug.
- // Extract the offset of the address dword and the
- // _EJ0 name to allow this patching.
+ // Extract the offsets of the device name, address dword and the slot
+ // name byte - we fill them in for each device.
Device(SAA) {
ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id
Name(_SUN, 0xAA)
ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr
Name(_ADR, 0xAA0000)
- ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0
Method(_EJ0, 1) {
- Return (PCEJ(_SUN))
+ PCEJ(BSEL, _SUN)
}
}
+
}
}
diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
index b3c2cd5cf9..610a631fd1 100644
--- a/hw/i386/ssdt-pcihp.hex.generated
+++ b/hw/i386/ssdt-pcihp.hex.generated
@@ -5,19 +5,19 @@ static unsigned char ssdt_pcihp_adr[] = {
0x44
};
static unsigned char ssdt_pcihp_end[] = {
-0x58
+0x5b
};
static unsigned char ssdp_pcihp_aml[] = {
0x53,
0x53,
0x44,
0x54,
-0x58,
+0x5b,
0x0,
0x0,
0x0,
0x1,
-0x76,
+0xe8,
0x42,
0x58,
0x50,
@@ -45,7 +45,7 @@ static unsigned char ssdp_pcihp_aml[] = {
0x13,
0x20,
0x10,
-0x33,
+0x36,
0x5c,
0x2e,
0x5f,
@@ -58,7 +58,7 @@ static unsigned char ssdp_pcihp_aml[] = {
0x30,
0x5b,
0x82,
-0x26,
+0x29,
0x53,
0x41,
0x41,
@@ -81,17 +81,20 @@ static unsigned char ssdp_pcihp_aml[] = {
0xaa,
0x0,
0x14,
-0xf,
+0x12,
0x5f,
0x45,
0x4a,
0x30,
0x1,
-0xa4,
0x50,
0x43,
0x45,
0x4a,
+0x42,
+0x53,
+0x45,
+0x4c,
0x5f,
0x53,
0x55,
@@ -103,6 +106,3 @@ static unsigned char ssdt_pcihp_start[] = {
static unsigned char ssdt_pcihp_id[] = {
0x3d
};
-static unsigned char ssdt_pcihp_ej0[] = {
-0x4a
-};
diff --git a/hw/i386/ssdt-proc.hex.generated b/hw/i386/ssdt-proc.hex.generated
index bb9920d3c9..97e28d4820 100644
--- a/hw/i386/ssdt-proc.hex.generated
+++ b/hw/i386/ssdt-proc.hex.generated
@@ -11,7 +11,7 @@ static unsigned char ssdp_proc_aml[] = {
0x0,
0x0,
0x1,
-0xb8,
+0x78,
0x42,
0x58,
0x50,
@@ -47,8 +47,8 @@ static unsigned char ssdp_proc_aml[] = {
0x41,
0x41,
0xaa,
-0x10,
-0xb0,
+0x0,
+0x0,
0x0,
0x0,
0x0,
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-27 03:57:16 +0200