bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

diff options

Diffstat (limited to 'hw/net/ftgmac100.c')

0 files changed, 0 insertions, 0 deletions

a id='n58' href='#n58'>58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339

/*
 * ASPEED Interrupt Controller (New)
 *
 * Andrew Jeffery <andrew@aj.id.au>
 *
 * Copyright 2015, 2016 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 */

/* The hardware exposes two register sets, a legacy set and a 'new' set. The
 * model implements the 'new' register set, and logs warnings on accesses to
 * the legacy IO space.
 *
 * The hardware uses 32bit registers to manage 51 IRQs, with low and high
 * registers for each conceptual register. The device model's implementation
 * uses 64bit data types to store both low and high register values (in the one
 * member), but must cope with access offset values in multiples of 4 passed to
 * the callbacks. As such the read() and write() implementations process the
 * provided offset to understand whether the access is requesting the lower or
 * upper 32 bits of the 64bit member.
 *
 * Additionally, the "Interrupt Enable", "Edge Status" and "Software Interrupt"
 * fields have separate "enable"/"status" and "clear" registers, where set bits
 * are written to one or the other to change state (avoiding a
 * read-modify-write sequence).
 */

#include "qemu/osdep.h"
#include "hw/intc/aspeed_vic.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "trace.h"

#define AVIC_NEW_BASE_OFFSET 0x80

#define AVIC_L_MASK 0xFFFFFFFFU
#define AVIC_H_MASK 0x0007FFFFU
#define AVIC_EVENT_W_MASK (0x78000ULL << 32)

static void aspeed_vic_update(AspeedVICState *s)
{
    uint64_t new = (s->raw & s->enable);
    uint64_t flags;

    flags = new & s->select;
    trace_aspeed_vic_update_fiq(!!flags);
    qemu_set_irq(s->fiq, !!flags);

    flags = new & ~s->select;
    trace_aspeed_vic_update_irq(!!flags);
    qemu_set_irq(s->irq, !!flags);
}

static void aspeed_vic_set_irq(void *opaque, int irq, int level)
{
    uint64_t irq_mask;
    bool raise;
    AspeedVICState *s = (AspeedVICState *)opaque;

    if (irq > ASPEED_VIC_NR_IRQS) {
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n",
                      __func__, irq);
        return;
    }

    trace_aspeed_vic_set_irq(irq, level);

    irq_mask = BIT(irq);
    if (s->sense & irq_mask) {
        /* level-triggered */
        if (s->event & irq_mask) {
            /* high-sensitive */
            raise = level;
        } else {
            /* low-sensitive */
            raise = !level;
        }
        s->raw = deposit64(s->raw, irq, 1, raise);
    } else {
        uint64_t old_level = s->level & irq_mask;

        /* edge-triggered */
        if (s->dual_edge & irq_mask) {
            raise = (!!old_level) != (!!level);
        } else {
            if (s->event & irq_mask) {
                /* rising-sensitive */
                raise = !old_level && level;
            } else {
                /* falling-sensitive */
                raise = old_level && !level;
            }
        }
        if (raise) {
            s->raw = deposit64(s->raw, irq, 1, raise);
        }
    }
    s->level = deposit64(s->level, irq, 1, level);
    aspeed_vic_update(s);
}

static uint64_t aspeed_vic_read(void *opaque, hwaddr offset, unsigned size)
{
    uint64_t val;
    const bool high = !!(offset & 0x4);
    hwaddr n_offset = (offset & ~0x4);
    AspeedVICState *s = (AspeedVICState *)opaque;

    if (offset < AVIC_NEW_BASE_OFFSET) {
        qemu_log_mask(LOG_UNIMP, "%s: Ignoring read from legacy registers "
                      "at 0x%" HWADDR_PRIx "[%u]\n", __func__, offset, size);
        return 0;
    }

    n_offset -= AVIC_NEW_BASE_OFFSET;

    switch (n_offset) {
    case 0x0: /* IRQ Status */
        val = s->raw & ~s->select & s->enable;
        break;
    case 0x08: /* FIQ Status */
        val = s->raw & s->select & s->enable;
        break;
    case 0x10: /* Raw Interrupt Status */
        val = s->raw;
        break;
    case 0x18: /* Interrupt Selection */
        val = s->select;
        break;
    case 0x20: /* Interrupt Enable */
        val = s->enable;
        break;
    case 0x30: /* Software Interrupt */
        val = s->trigger;
        break;
    case 0x40: /* Interrupt Sensitivity */
        val = s->sense;
        break;
    case 0x48: /* Interrupt Both Edge Trigger Control */
        val = s->dual_edge;
        break;
    case 0x50: /* Interrupt Event */
        val = s->event;
        break;
    case 0x60: /* Edge Triggered Interrupt Status */
        val = s->raw & ~s->sense;
        break;
        /* Illegal */
    case 0x28: /* Interrupt Enable Clear */
    case 0x38: /* Software Interrupt Clear */
    case 0x58: /* Edge Triggered Interrupt Clear */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Read of write-only register with offset 0x%"
                      HWADDR_PRIx "\n", __func__, offset);
        val = 0;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad register at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        val = 0;
        break;
    }
    if (high) {
        val = extract64(val, 32, 19);
    }
    trace_aspeed_vic_read(offset, size, val);
    return val;
}

static void aspeed_vic_write(void *opaque, hwaddr offset, uint64_t data,
                             unsigned size)
{
    const bool high = !!(offset & 0x4);
    hwaddr n_offset = (offset & ~0x4);
    AspeedVICState *s = (AspeedVICState *)opaque;

    if (offset < AVIC_NEW_BASE_OFFSET) {
        qemu_log_mask(LOG_UNIMP,
                      "%s: Ignoring write to legacy registers at 0x%"
                      HWADDR_PRIx "[%u] <- 0x%" PRIx64 "\n", __func__, offset,
                      size, data);
        return;
    }

    n_offset -= AVIC_NEW_BASE_OFFSET;
    trace_aspeed_vic_write(offset, size, data);

    /* Given we have members using separate enable/clear registers, deposit64()
     * isn't quite the tool for the job. Instead, relocate the incoming bits to
     * the required bit offset based on the provided access address
     */
    if (high) {
        data &= AVIC_H_MASK;
        data <<= 32;
    } else {
        data &= AVIC_L_MASK;
    }

    switch (n_offset) {
    case 0x18: /* Interrupt Selection */
        /* Register has deposit64() semantics - overwrite requested 32 bits */
        if (high) {
            s->select &= AVIC_L_MASK;
        } else {
            s->select &= ((uint64_t) AVIC_H_MASK) << 32;
        }
        s->select |= data;
        break;
    case 0x20: /* Interrupt Enable */
        s->enable |= data;
        break;
    case 0x28: /* Interrupt Enable Clear */
        s->enable &= ~data;
        break;
    case 0x30: /* Software Interrupt */
        qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
                      "IRQs requested: 0x%016" PRIx64 "\n", __func__, data);
        break;
    case 0x38: /* Software Interrupt Clear */
        qemu_log_mask(LOG_UNIMP, "%s: Software interrupts unavailable. "
                      "IRQs to be cleared: 0x%016" PRIx64 "\n", __func__, data);
        break;
    case 0x50: /* Interrupt Event */
        /* Register has deposit64() semantics - overwrite the top four valid
         * IRQ bits, as only the top four IRQs (GPIOs) can change their event
         * type */
        if (high) {
            s->event &= ~AVIC_EVENT_W_MASK;
            s->event |= (data & AVIC_EVENT_W_MASK);
        } else {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "Ignoring invalid write to interrupt event register");
        }
        break;
    case 0x58: /* Edge Triggered Interrupt Clear */
        s->raw &= ~(data & ~s->sense);
        break;
    case 0x00: /* IRQ Status */
    case 0x08: /* FIQ Status */
    case 0x10: /* Raw Interrupt Status */
    case 0x40: /* Interrupt Sensitivity */
    case 0x48: /* Interrupt Both Edge Trigger Control */
    case 0x60: /* Edge Triggered Interrupt Status */


context:
space:
mode: