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-rw-r--r--hw/ppc/Kconfig4
-rw-r--r--hw/ppc/Makefile.objs2
-rw-r--r--hw/ppc/e500.c18
-rw-r--r--hw/ppc/e500plat.c1
-rw-r--r--hw/ppc/mac_newworld.c6
-rw-r--r--hw/ppc/mac_oldworld.c6
-rw-r--r--hw/ppc/mpc8544ds.c1
-rw-r--r--hw/ppc/pnv.c10
-rw-r--r--hw/ppc/ppc405_boards.c48
-rw-r--r--hw/ppc/ppc440_bamboo.c12
-rw-r--r--hw/ppc/ppc4xx_devs.c67
-rw-r--r--hw/ppc/sam460ex.c6
-rw-r--r--hw/ppc/spapr.c124
-rw-r--r--hw/ppc/spapr_drc.c62
-rw-r--r--hw/ppc/spapr_events.c4
-rw-r--r--hw/ppc/spapr_hcall.c14
-rw-r--r--hw/ppc/spapr_nvdimm.c475
-rw-r--r--hw/ppc/spapr_rtas.c7
-rw-r--r--hw/ppc/virtex_ml507.c13
19 files changed, 751 insertions, 129 deletions
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 354828bf13..dd86e664d2 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -29,6 +29,8 @@ config POWERNV
select XICS
select XIVE
select FDT_PPC
+ select PCI_EXPRESS
+ select MSI_NONBROKEN
config PPC405
bool
@@ -135,8 +137,6 @@ config XIVE_SPAPR
default y
depends on PSERIES
select XIVE
- select PCI
- select PCIE_PORT
config XIVE_KVM
bool
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index a4bac57be6..c3d3cc56eb 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -7,7 +7,7 @@ obj-$(CONFIG_PSERIES) += spapr.o spapr_caps.o spapr_vio.o spapr_events.o
obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o
obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o spapr_irq.o
-obj-$(CONFIG_PSERIES) += spapr_tpm_proxy.o
+obj-$(CONFIG_PSERIES) += spapr_tpm_proxy.o spapr_nvdimm.o
obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o
obj-$(call land,$(CONFIG_PSERIES),$(CONFIG_LINUX)) += spapr_pci_vfio.o spapr_pci_nvlink2.o
# IBM PowerNV
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 886442e54f..854cd3ac46 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -594,6 +594,7 @@ done:
cpu_physical_memory_write(addr, fdt, fdt_size);
}
ret = fdt_size;
+ g_free(fdt);
out:
g_free(pci_map);
@@ -831,7 +832,6 @@ static void ppce500_power_off(void *opaque, int line, int on)
void ppce500_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
PPCE500MachineState *pms = PPCE500_MACHINE(machine);
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
PCIBus *pci_bus;
@@ -906,13 +906,13 @@ void ppce500_init(MachineState *machine)
env = firstenv;
- /* Fixup Memory size on a alignment boundary */
- ram_size &= ~(RAM_SIZES_ALIGN - 1);
- machine->ram_size = ram_size;
+ if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) {
+ error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN);
+ exit(EXIT_FAILURE);
+ }
/* Register Memory */
- memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
- memory_region_add_subregion(address_space_mem, 0, ram);
+ memory_region_add_subregion(address_space_mem, 0, machine->ram);
dev = qdev_create(NULL, "e500-ccsr");
object_property_add_child(qdev_get_machine(), "e500-ccsr",
@@ -1083,7 +1083,7 @@ void ppce500_init(MachineState *machine)
kernel_base = cur_base;
kernel_size = load_image_targphys(machine->kernel_filename,
cur_base,
- ram_size - cur_base);
+ machine->ram_size - cur_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'",
machine->kernel_filename);
@@ -1097,7 +1097,7 @@ void ppce500_init(MachineState *machine)
if (machine->initrd_filename) {
initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
- ram_size - initrd_base);
+ machine->ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
@@ -1115,7 +1115,7 @@ void ppce500_init(MachineState *machine)
* ensures enough space between kernel and initrd.
*/
dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
- if (dt_base + DTB_MAX_SIZE > ram_size) {
+ if (dt_base + DTB_MAX_SIZE > machine->ram_size) {
error_report("not enough memory for device tree");
exit(1);
}
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 7078386300..bddd5e7c48 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -97,6 +97,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
mc->init = e500plat_init;
mc->max_cpus = 32;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30");
+ mc->default_ram_id = "mpc8544ds.ram";
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ETSEC_COMMON);
}
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 464d012103..b8189bf7a4 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -118,7 +118,7 @@ static void ppc_core99_init(MachineState *machine)
char *filename;
IrqLines *openpic_irqs;
int linux_boot, i, j, k;
- MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
UNINHostState *uninorth_pci;
@@ -152,8 +152,7 @@ static void ppc_core99_init(MachineState *machine)
}
/* allocate RAM */
- memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
- memory_region_add_subregion(get_system_memory(), 0, ram);
+ memory_region_add_subregion(get_system_memory(), 0, machine->ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
@@ -586,6 +585,7 @@ static void core99_machine_class_init(ObjectClass *oc, void *data)
#else
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
#endif
+ mc->default_ram_id = "ppc_core99.ram";
mc->ignore_boot_device_suffixes = true;
fwc->get_dev_path = core99_fw_dev_path;
}
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 7318d7e9b4..66e434bba3 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -91,7 +91,6 @@ static void ppc_heathrow_init(MachineState *machine)
CPUPPCState *env = NULL;
char *filename;
int linux_boot, i;
- MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
@@ -127,9 +126,7 @@ static void ppc_heathrow_init(MachineState *machine)
exit(1);
}
- memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
- ram_size);
- memory_region_add_subregion(sysmem, 0, ram);
+ memory_region_add_subregion(sysmem, 0, machine->ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
@@ -446,6 +443,7 @@ static void heathrow_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
mc->default_display = "std";
mc->ignore_boot_device_suffixes = true;
+ mc->default_ram_id = "ppc_heathrow.ram";
fwc->get_dev_path = heathrow_fw_dev_path;
}
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index c2c5e11fa1..81177505f0 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -55,6 +55,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data)
mc->init = mpc8544ds_init;
mc->max_cpus = 15;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30");
+ mc->default_ram_id = "mpc8544ds.ram";
}
#define TYPE_MPC8544DS_MACHINE MACHINE_TYPE_NAME("mpc8544ds")
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 139c857b1e..b75ad06390 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -582,6 +582,8 @@ static void pnv_reset(MachineState *machine)
qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
+
+ g_free(fdt);
}
static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
@@ -690,7 +692,6 @@ static void pnv_init(MachineState *machine)
{
PnvMachineState *pnv = PNV_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
- MemoryRegion *ram;
char *fw_filename;
long fw_size;
int i;
@@ -702,11 +703,7 @@ static void pnv_init(MachineState *machine)
if (machine->ram_size < (1 * GiB)) {
warn_report("skiboot may not work with < 1GB of RAM");
}
-
- ram = g_new(MemoryRegion, 1);
- memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
- machine->ram_size);
- memory_region_add_subregion(get_system_memory(), 0, ram);
+ memory_region_add_subregion(get_system_memory(), 0, machine->ram);
/*
* Create our simple PNOR device
@@ -1976,6 +1973,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
* enough to fit the maximum initrd size at it's load address
*/
mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
+ mc->default_ram_id = "pnv.ram";
ispc->print_info = pnv_pic_print_info;
object_class_property_add_bool(oc, "hb-mode",
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 1f721feed6..de93c40f1a 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -40,6 +40,7 @@
#include "qemu/error-report.h"
#include "hw/loader.h"
#include "exec/address-spaces.h"
+#include "qemu/cutils.h"
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2 * MiB)
@@ -137,7 +138,7 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
static void ref405ep_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -161,15 +162,21 @@ static void ref405ep_init(MachineState *machine)
DriveInfo *dinfo;
MemoryRegion *sysmem = get_system_memory();
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
/* XXX: fix this */
- memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
- 0x08000000);
+ memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
+ machine->ram, 0, machine->ram_size);
ram_bases[0] = 0;
- ram_sizes[0] = 0x08000000;
+ ram_sizes[0] = machine->ram_size;
memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
ram_bases[1] = 0x00000000;
ram_sizes[1] = 0x00000000;
- ram_size = 128 * MiB;
env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
33333333, &pic, kernel_filename == NULL ? 0 : 1);
/* allocate SRAM */
@@ -227,7 +234,7 @@ static void ref405ep_init(MachineState *machine)
if (linux_boot) {
memset(&bd, 0, sizeof(bd));
bd.bi_memstart = 0x00000000;
- bd.bi_memsize = ram_size;
+ bd.bi_memsize = machine->ram_size;
bd.bi_flashstart = -bios_size;
bd.bi_flashsize = -bios_size;
bd.bi_flashoffset = 0;
@@ -255,7 +262,7 @@ static void ref405ep_init(MachineState *machine)
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
kernel_size = load_image_targphys(kernel_filename, kernel_base,
- ram_size - kernel_base);
+ machine->ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
@@ -266,7 +273,7 @@ static void ref405ep_init(MachineState *machine)
if (initrd_filename) {
initrd_base = INITRD_LOAD_ADDR;
initrd_size = load_image_targphys(initrd_filename, initrd_base,
- ram_size - initrd_base);
+ machine->ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
@@ -304,6 +311,8 @@ static void ref405ep_class_init(ObjectClass *oc, void *data)
mc->desc = "ref405ep";
mc->init = ref405ep_init;
+ mc->default_ram_size = 0x08000000;
+ mc->default_ram_id = "ef405ep.ram";
}
static const TypeInfo ref405ep_type = {
@@ -408,7 +417,7 @@ static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
static void taihu_405ep_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
char *filename;
@@ -416,7 +425,6 @@ static void taihu_405ep_init(MachineState *machine)
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *bios;
MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
- MemoryRegion *ram = g_malloc0(sizeof(*ram));
hwaddr ram_bases[2], ram_sizes[2];
long bios_size;
target_ulong kernel_base, initrd_base;
@@ -425,20 +433,22 @@ static void taihu_405ep_init(MachineState *machine)
int fl_idx;
DriveInfo *dinfo;
- /* RAM is soldered to the board so the size cannot be changed */
- ram_size = 0x08000000;
- memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
- ram_size);
+ if (machine->ram_size != mc->default_ram_size) {
+ char *sz = size_to_str(mc->default_ram_size);
+ error_report("Invalid RAM size, should be %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
ram_bases[0] = 0;
ram_sizes[0] = 0x04000000;
memory_region_init_alias(&ram_memories[0], NULL,
- "taihu_405ep.ram-0", ram, ram_bases[0],
+ "taihu_405ep.ram-0", machine->ram, ram_bases[0],
ram_sizes[0]);
ram_bases[1] = 0x04000000;
ram_sizes[1] = 0x04000000;
memory_region_init_alias(&ram_memories[1], NULL,
- "taihu_405ep.ram-1", ram, ram_bases[1],
+ "taihu_405ep.ram-1", machine->ram, ram_bases[1],
ram_sizes[1]);
ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
33333333, &pic, kernel_filename == NULL ? 0 : 1);
@@ -500,7 +510,7 @@ static void taihu_405ep_init(MachineState *machine)
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
kernel_size = load_image_targphys(kernel_filename, kernel_base,
- ram_size - kernel_base);
+ machine->ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
@@ -509,7 +519,7 @@ static void taihu_405ep_init(MachineState *machine)
if (initrd_filename) {
initrd_base = INITRD_LOAD_ADDR;
initrd_size = load_image_targphys(initrd_filename, initrd_base,
- ram_size - initrd_base);
+ machine->ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
@@ -533,6 +543,8 @@ static void taihu_class_init(ObjectClass *oc, void *data)
mc->desc = "taihu";
mc->init = taihu_405ep_init;
+ mc->default_ram_size = 0x08000000;
+ mc->default_ram_id = "taihu_405ep.ram";
}
static const TypeInfo taihu_type = {
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index da777ef9c2..4c5e9e4373 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -158,7 +158,6 @@ static void main_cpu_reset(void *opaque)
static void bamboo_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@@ -203,10 +202,8 @@ static void bamboo_init(MachineState *machine)
/* SDRAM controller */
memset(ram_bases, 0, sizeof(ram_bases));
memset(ram_sizes, 0, sizeof(ram_sizes));
- ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS,
- ram_memories,
- ram_bases, ram_sizes,
- ppc440ep_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
+ ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, 1);
@@ -268,7 +265,7 @@ static void bamboo_init(MachineState *machine)
/* Load initrd. */
if (initrd_filename) {
initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
- ram_size - RAMDISK_ADDR);
+ machine->ram_size - RAMDISK_ADDR);
if (initrd_size < 0) {
error_report("could not load ram disk '%s' at %x",
@@ -279,7 +276,7 @@ static void bamboo_init(MachineState *machine)
/* If we're loading a kernel directly, we must load the device tree too. */
if (kernel_filename) {
- if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR,
+ if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
initrd_size, kernel_cmdline) < 0) {
error_report("couldn't load device tree");
exit(1);
@@ -292,6 +289,7 @@ static void bamboo_machine_init(MachineClass *mc)
mc->desc = "bamboo";
mc->init = bamboo_init;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb");
+ mc->default_ram_id = "ppc4xx.sdram";
}
DEFINE_MACHINE("bamboo", bamboo_machine_init)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index c2e50138aa..3376c43ff5 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -666,21 +666,22 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
sdram_map_bcr(sdram);
}
-/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
+/*
+ * Split RAM between SDRAM banks.
*
- * sdram_bank_sizes[] must be 0-terminated.
+ * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
+ * and must be 0-terminated.
*
* The 4xx SDRAM controller supports a small number of banks, and each bank
* must be one of a small set of sizes. The number of banks and the supported
- * sizes varies by SoC. */
-ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[],
- hwaddr ram_sizes[],
- const ram_addr_t sdram_bank_sizes[])
+ * sizes varies by SoC.
+ */
+void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
+ MemoryRegion ram_memories[],
+ hwaddr ram_bases[], hwaddr ram_sizes[],
+ const ram_addr_t sdram_bank_sizes[])
{
- MemoryRegion *ram = g_malloc0(sizeof(*ram));
- ram_addr_t size_left = ram_size;
+ ram_addr_t size_left = memory_region_size(ram);
ram_addr_t base = 0;
ram_addr_t bank_size;
int i;
@@ -690,7 +691,16 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
for (j = 0; sdram_bank_sizes[j] != 0; j++) {
bank_size = sdram_bank_sizes[j];
if (bank_size <= size_left) {
+ char name[32];
+
+ ram_bases[i] = base;
+ ram_sizes[i] = bank_size;
+ base += bank_size;
size_left -= bank_size;
+ snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
+ memory_region_init_alias(&ram_memories[i], NULL, name, ram,
+ ram_bases[i], ram_sizes[i]);
+ break;
}
}
if (!size_left) {
@@ -699,34 +709,23 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
}
}
- ram_size -= size_left;
if (size_left) {
- error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM"
- " controller limits", ram_size / MiB);
- }
+ ram_addr_t used_size = memory_region_size(ram) - size_left;
+ GString *s = g_string_new(NULL);
- memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size);
-
- size_left = ram_size;
- for (i = 0; i < nr_banks && size_left; i++) {
- for (j = 0; sdram_bank_sizes[j] != 0; j++) {
- bank_size = sdram_bank_sizes[j];
-
- if (bank_size <= size_left) {
- char name[32];
- snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- memory_region_init_alias(&ram_memories[i], NULL, name, ram,
- base, bank_size);
- ram_bases[i] = base;
- ram_sizes[i] = bank_size;
- base += bank_size;
- size_left -= bank_size;
- break;
- }
+ for (i = 0; sdram_bank_sizes[i]; i++) {
+ g_string_append_printf(s, "%" PRIi64 "%s",
+ sdram_bank_sizes[i] / MiB,
+ sdram_bank_sizes[i + 1] ? " ," : "");
}
- }
+ error_report("Max %d banks of %s MB DIMM/bank supported",
+ nr_banks, s->str);
+ error_report("Possible valid RAM size: %" PRIi64,
+ used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
- return ram_size;
+ g_string_free(s, true);
+ exit(EXIT_FAILURE);
+ }
}
/*****************************************************************************/
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 89bc70eb94..898453cf30 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -324,9 +324,8 @@ static void sam460ex_init(MachineState *machine)
/* SDRAM controller */
/* put all RAM on first bank because board has one slot
* and firmware only checks that */
- machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
- ram_memories, ram_bases, ram_sizes,
- ppc460ex_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes,
+ ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
@@ -485,6 +484,7 @@ static void sam460ex_machine_init(MachineClass *mc)
mc->init = sam460ex_init;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
mc->default_ram_size = 512 * MiB;
+ mc->default_ram_id = "ppc4xx.sdram";
}
DEFINE_MACHINE("sam460ex", sam460ex_machine_init)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index c9b2e0a5e0..c03ce6afb9 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -80,6 +80,7 @@
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/mem/memory-device.h"
#include "hw/ppc/spapr_tpm_proxy.h"
+#include "hw/ppc/spapr_nvdimm.h"
#include "monitor/monitor.h"
@@ -675,6 +676,14 @@ static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
size = di->size;
node = di->node;
+ /*
+ * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
+ * area is marked hotpluggable in the next iteration for the bigger
+ * chunk including the NVDIMM occupied area.
+ */
+ if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
+ continue;
+
/* Entry for hot-pluggable area */
if (cur_addr < addr) {
drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
@@ -1055,7 +1064,7 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
}
if (spapr->kernel_size) {
- uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
+ uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
cpu_to_be64(spapr->kernel_size) };
_FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
@@ -1243,7 +1252,8 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
/* Build memory reserve map */
if (reset) {
if (spapr->kernel_size) {
- _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
+ _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr,
+ spapr->kernel_size)));
}
if (spapr->initrd_size) {
_FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
@@ -1266,12 +1276,19 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
}
}
+ /* NVDIMM devices */
+ if (mc->nvdimm_supported) {
+ spapr_dt_persistent_memory(fdt);
+ }
+
return fdt;
}
static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
{
- return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
+ SpaprMachineState *spapr = opaque;
+
+ return (addr & 0x0fffffff) + spapr->kernel_addr;
}
static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
@@ -2629,12 +2646,12 @@ static void spapr_machine_init(MachineState *machine)
{
SpaprMachineState *spapr = SPAPR_MACHINE(machine);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
PCIHostState *phb;
int i;
MemoryRegion *sysmem = get_system_memory();
- MemoryRegion *ram = g_new(MemoryRegion, 1);
hwaddr node0_size = spapr_node0_size(machine);
long load_limit, fw_size;
char *filename;
@@ -2813,10 +2830,8 @@ static void spapr_machine_init(MachineState *machine)
kvmppc_enable_h_page_init();
}
- /* allocate RAM */
- memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
- machine->ram_size);
- memory_region_add_subregion(sysmem, 0, ram);
+ /* map RAM */
+ memory_region_add_subregion(sysmem, 0, machine->ram);
/* always allocate the device memory information */
machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
@@ -2861,6 +2876,10 @@ static void spapr_machine_init(MachineState *machine)
"may run and log hardware error on the destination");
}
+ if (mc->nvdimm_supported) {
+ spapr_create_nvdimm_dr_connectors(spapr);
+ }
+
/* Set up RTAS event infrastructure */
spapr_events_init(spapr);
@@ -2948,14 +2967,15 @@ static void spapr_machine_init(MachineState *machine)
uint64_t lowaddr = 0;
spapr->kernel_size = load_elf(kernel_filename, NULL,
- translate_kernel_address, NULL,
+ translate_kernel_address, spapr,
NULL, &lowaddr, NULL, NULL, 1,
PPC_ELF_MACHINE, 0, 0);
if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
spapr->kernel_size = load_elf(kernel_filename, NULL,
- translate_kernel_address, NULL, NULL,
+ translate_kernel_address, spapr, NULL,
&lowaddr, NULL, NULL, 0,
- PPC_ELF_MACHINE, 0, 0);
+ PPC_ELF_MACHINE,
+ 0, 0);
spapr->kernel_le = spapr->kernel_size > 0;
}
if (spapr->kernel_size < 0) {
@@ -2969,7 +2989,7 @@ static void spapr_machine_init(MachineState *machine)
/* Try to locate the initrd in the gap between the kernel
* and the firmware. Add a bit of space just in case
*/
- spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
+ spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size
+ 0x1ffff) & ~0xffff;
spapr->initrd_size = load_image_targphys(initrd_filename,
spapr->initrd_base,
@@ -3215,6 +3235,18 @@ static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
}
+static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint64(v, name, (uint64_t *)opaque, errp);
+}
+
+static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint64(v, name, (uint64_t *)opaque, errp);
+}
+
static char *spapr_get_ic_mode(Object *obj, Error **errp)
{
SpaprMachineState *spapr = SPAPR_MACHINE(obj);
@@ -3320,6 +3352,14 @@ static void spapr_instance_init(Object *obj)
object_property_add_bool(obj, "vfio-no-msix-emulation",
spapr_get_msix_emulation, NULL, NULL);
+ object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr,
+ spapr_set_kernel_addr, NULL, &spapr->kernel_addr,
+ &error_abort);
+ object_property_set_description(obj, "kernel-addr",
+ stringify(KERNEL_LOAD_ADDR)
+ " for -kernel is the default",
+ NULL);
+ spapr->kernel_addr = KERNEL_LOAD_ADDR;
/* The machine class defines the default interrupt controller mode */
spapr->irq = smc->irq;
object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
@@ -3430,7 +3470,8 @@ static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error *local_err = NULL;
SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
PCDIMMDevice *dimm = PC_DIMM(dev);
- uint64_t size, addr;
+ uint64_t size, addr, slot;
+ bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
@@ -3439,14 +3480,24 @@ static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
goto out;
}
- addr = object_property_get_uint(OBJECT(dimm),
- PC_DIMM_ADDR_PROP, &local_err);
- if (local_err) {
- goto out_unplug;
+ if (!is_nvdimm) {
+ addr = object_property_get_uint(OBJECT(dimm),
+ PC_DIMM_ADDR_PROP, &local_err);
+ if (local_err) {
+ goto out_unplug;
+ }
+ spapr_add_lmbs(dev, addr, size,
+ spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
+ &local_err);
+ } else {
+ slot = object_property_get_uint(OBJECT(dimm),
+ PC_DIMM_SLOT_PROP, &local_err);
+ if (local_err) {
+ goto out_unplug;
+ }
+ spapr_add_nvdimm(dev, slot, &local_err);
}
- spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
- &local_err);
if (local_err) {
goto out_unplug;
}
@@ -3464,6 +3515,8 @@ static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
{
const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
+ const MachineClass *mc = MACHINE_CLASS(smc);
+ bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
PCDIMMDevice *dimm = PC_DIMM(dev);
Error *local_err = NULL;
uint64_t size;
@@ -3475,16 +3528,27 @@ static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
return;
}
+ if (is_nvdimm && !mc->nvdimm_supported) {
+ error_setg(errp, "NVDIMM hotplug not supported for this machine");
+ return;
+ }
+
size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- if (size % SPAPR_MEMORY_BLOCK_SIZE) {
+ if (!is_nvdimm && size % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp, "Hotplugged memory size must be a multiple of "
- "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
+ "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
return;
+ } else if (is_nvdimm) {
+ spapr_nvdimm_validate_opts(NVDIMM(dev), size, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
}
memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
@@ -3624,6 +3688,12 @@ static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
int i;
SpaprDrc *drc;
+ if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
+ error_setg(&local_err,
+ "nvdimm device hot unplug is not supported yet.");
+ goto out;
+ }
+
size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
@@ -4400,6 +4470,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
mc->no_parallel = 1;
mc->default_boot_order = "";
mc->default_ram_size = 512 * MiB;
+ mc->default_ram_id = "ppc_spapr.ram";
mc->default_display = "std";
mc->kvm_type = spapr_kvm_type;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
@@ -4418,6 +4489,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->update_dt_enabled = true;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
mc->has_hotpluggable_cpus = true;
+ mc->nvdimm_supported = true;
smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
fwc->get_dev_path = spapr_get_fw_dev_path;
nc->nmi_monitor_handler = spapr_nmi;
@@ -4485,6 +4557,12 @@ static const TypeInfo spapr_machine_info = {
},
};
+static void spapr_machine_latest_class_options(MachineClass *mc)
+{
+ mc->alias = "pseries";
+ mc->is_default = 1;
+}
+
#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
void *data) \
@@ -4492,8 +4570,7 @@ static const TypeInfo spapr_machine_info = {
MachineClass *mc = MACHINE_CLASS(oc); \
spapr_machine_##suffix##_class_options(mc); \
if (latest) { \
- mc->alias = "pseries"; \
- mc->is_default = 1; \
+ spapr_machine_latest_class_options(mc); \
} \
} \
static const TypeInfo spapr_machine_##suffix##_info = { \
@@ -4528,6 +4605,7 @@ static void spapr_machine_4_2_class_options(MachineClass *mc)
compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF;
+ mc->nvdimm_supported = false;
}
DEFINE_SPAPR_MACHINE(4_2, "4.2", false);
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 17aeac3801..e373d342eb 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -22,6 +22,7 @@
#include "qemu/error-report.h"
#include "hw/ppc/spapr.h" /* for RTAS return codes */
#include "hw/pci-host/spapr.h" /* spapr_phb_remove_pci_device_cb callback */
+#include "hw/ppc/spapr_nvdimm.h"
#include "sysemu/device_tree.h"
#include "sysemu/reset.h"
#include "trace.h"
@@ -455,21 +456,46 @@ void spapr_drc_reset(SpaprDrc *drc)
}
}
-bool spapr_drc_needed(void *opaque)
+static bool spapr_drc_unplug_requested_needed(void *opaque)
+{
+ return spapr_drc_unplug_requested(opaque);
+}
+
+static const VMStateDescription vmstate_spapr_drc_unplug_requested = {
+ .name = "spapr_drc/unplug_requested",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = spapr_drc_unplug_requested_needed,
+ .fields = (VMStateField []) {
+ VMSTATE_BOOL(unplug_requested, SpaprDrc),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+bool spapr_drc_transient(SpaprDrc *drc)
{
- SpaprDrc *drc = (SpaprDrc *)opaque;
SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
- /* If no dev is plugged in there is no need to migrate the DRC state */
+ /*
+ * If no dev is plugged in there is no need to migrate the DRC state
+ * nor to reset the DRC at CAS.
+ */
if (!drc->dev) {
return false;
}
/*
- * We need to migrate the state if it's not equal to the expected
- * long-term state, which is the same as the coldplugged initial
- * state */
- return (drc->state != drck->ready_state);
+ * We need to reset the DRC at CAS or to migrate the DRC state if it's
+ * not equal to the expected long-term state, which is the same as the
+ * coldplugged initial state, or if an unplug request is pending.
+ */
+ return drc->state != drck->ready_state ||
+ spapr_drc_unplug_requested(drc);
+}
+
+static bool spapr_drc_needed(void *opaque)
+{
+ return spapr_drc_transient(opaque);
}
static const VMStateDescription vmstate_spapr_drc = {
@@ -480,6 +506,10 @@ static const VMStateDescription vmstate_spapr_drc = {
.fields = (VMStateField []) {
VMSTATE_UINT32(state, SpaprDrc),
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_spapr_drc_unplug_requested,
+ NULL
}
};
@@ -709,6 +739,17 @@ static void spapr_drc_phb_class_init(ObjectClass *k, void *data)
drck->dt_populate = spapr_phb_dt_populate;
}
+static void spapr_drc_pmem_class_init(ObjectClass *k, void *data)
+{
+ SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k);
+
+ drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PMEM;
+ drck->typename = "PMEM";
+ drck->drc_name_prefix = "PMEM ";
+ drck->release = NULL;
+ drck->dt_populate = spapr_pmem_dt_populate;
+}
+
static const TypeInfo spapr_dr_connector_info = {
.name = TYPE_SPAPR_DR_CONNECTOR,
.parent = TYPE_DEVICE,
@@ -759,6 +800,12 @@ static const TypeInfo spapr_drc_phb_info = {
.class_init = spapr_drc_phb_class_init,
};
+static const TypeInfo spapr_drc_pmem_info = {
+ .name = TYPE_SPAPR_DRC_PMEM,
+ .parent = TYPE_SPAPR_DRC_LOGICAL,
+ .class_init = spapr_drc_pmem_class_init,
+};
+
/* helper functions for external users */
SpaprDrc *spapr_drc_by_index(uint32_t index)
@@ -1230,6 +1277,7 @@ static void spapr_drc_register_types(void)
type_register_static(&spapr_drc_pci_info);
type_register_static(&spapr_drc_lmb_info);
type_register_static(&spapr_drc_phb_info);
+ type_register_static(&spapr_drc_pmem_info);
spapr_rtas_register(RTAS_SET_INDICATOR, "set-indicator",
rtas_set_indicator);
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index 884e455f02..8b32b7eea5 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -196,6 +196,7 @@ struct rtas_event_log_v6_hp {
#define RTAS_LOG_V6_HP_TYPE_SLOT 3
#define RTAS_LOG_V6_HP_TYPE_PHB 4
#define RTAS_LOG_V6_HP_TYPE_PCI 5
+#define RTAS_LOG_V6_HP_TYPE_PMEM 6
uint8_t hotplug_action;
#define RTAS_LOG_V6_HP_ACTION_ADD 1
#define RTAS_LOG_V6_HP_ACTION_REMOVE 2
@@ -631,6 +632,9 @@ static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action,
case SPAPR_DR_CONNECTOR_TYPE_PHB:
hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PHB;
break;
+ case SPAPR_DR_CONNECTOR_TYPE_PMEM:
+ hp->hotplug_type = RTAS_LOG_V6_HP_TYPE_PMEM;
+ break;
default:
/* we shouldn't be signaling hotplug events for resources
* that don't support them
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index caf55ab044..934eb12d27 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1640,20 +1640,24 @@ static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu,
return best_compat;
}
-static bool spapr_hotplugged_dev_before_cas(void)
+static bool spapr_transient_dev_before_cas(void)
{
- Object *drc_container, *obj;
+ Object *drc_container;
ObjectProperty *prop;
ObjectPropertyIterator iter;
drc_container = container_get(object_get_root(), "/dr-connector");
object_property_iter_init(&iter, drc_container);
while ((prop = object_property_iter_next(&iter))) {
+ SpaprDrc *drc;
+
if (!strstart(prop->type, "link<", NULL)) {
continue;
}
- obj = object_property_get_link(drc_container, prop->name, NULL);
- if (spapr_drc_needed(obj)) {
+ drc = SPAPR_DR_CONNECTOR(object_property_get_link(drc_container,
+ prop->name, NULL));
+
+ if (spapr_drc_transient(drc)) {
return true;
}
}
@@ -1830,7 +1834,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
spapr_irq_update_active_intc(spapr);
- if (spapr_hotplugged_dev_before_cas()) {
+ if (spapr_transient_dev_before_cas()) {
spapr->cas_reboot = true;
}
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
new file mode 100644
index 0000000000..74eeb8bb74
--- /dev/null
+++ b/hw/ppc/spapr_nvdimm.c
@@ -0,0 +1,475 @@
+/*
+ * QEMU PAPR Storage Class Memory Interfaces
+ *
+ * Copyright (c) 2019-2020, IBM Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/ppc/spapr_drc.h"
+#include "hw/ppc/spapr_nvdimm.h"
+#include "hw/mem/nvdimm.h"
+#include "qemu/nvdimm-utils.h"
+#include "hw/ppc/fdt.h"
+#include "qemu/range.h"
+
+void spapr_nvdimm_validate_opts(NVDIMMDevice *nvdimm, uint64_t size,
+ Error **errp)
+{
+ char *uuidstr = NULL;
+ QemuUUID uuid;
+
+ if (size % SPAPR_MINIMUM_SCM_BLOCK_SIZE) {
+ error_setg(errp, "NVDIMM memory size excluding the label area"
+ " must be a multiple of %" PRIu64 "MB",
+ SPAPR_MINIMUM_SCM_BLOCK_SIZE / MiB);
+ return;
+ }
+
+ uuidstr = object_property_get_str(OBJECT(nvdimm), NVDIMM_UUID_PROP, NULL);
+ qemu_uuid_parse(uuidstr, &uuid);
+ g_free(uuidstr);
+
+ if (qemu_uuid_is_null(&uuid)) {
+ error_setg(errp, "NVDIMM device requires the uuid to be set");
+ return;
+ }
+}
+
+
+void spapr_add_nvdimm(DeviceState *dev, uint64_t slot, Error **errp)
+{
+ SpaprDrc *drc;
+ bool hotplugged = spapr_drc_hotplugged(dev);
+ Error *local_err = NULL;
+
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PMEM, slot);
+ g_assert(drc);
+
+ spapr_drc_attach(drc, dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (hotplugged) {
+ spapr_hotplug_req_add_by_index(drc);
+ }
+}
+
+int spapr_pmem_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
+ void *fdt, int *fdt_start_offset, Error **errp)
+{
+ NVDIMMDevice *nvdimm = NVDIMM(drc->dev);
+
+ *fdt_start_offset = spapr_dt_nvdimm(fdt, 0, nvdimm);
+
+ return 0;
+}
+
+void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr)
+{
+ MachineState *machine = MACHINE(spapr);
+ int i;
+
+ for (i = 0; i < machine->ram_slots; i++) {
+ spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i);
+ }
+}
+
+
+int spapr_dt_nvdimm(void *fdt, int parent_offset,
+ NVDIMMDevice *nvdimm)
+{
+ int child_offset;
+ char *buf;
+ SpaprDrc *drc;
+ uint32_t drc_idx;
+ uint32_t node = object_property_get_uint(OBJECT(nvdimm), PC_DIMM_NODE_PROP,
+ &error_abort);
+ uint64_t slot = object_property_get_uint(OBJECT(nvdimm), PC_DIMM_SLOT_PROP,
+ &error_abort);
+ uint32_t associativity[] = {
+ cpu_to_be32(0x4), /* length */
+ cpu_to_be32(0x0), cpu_to_be32(0x0),
+ cpu_to_be32(0x0), cpu_to_be32(node)
+ };
+ uint64_t lsize = nvdimm->label_size;
+ uint64_t size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP,
+ NULL);
+
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PMEM, slot);
+ g_assert(drc);
+
+ drc_idx = spapr_drc_index(drc);
+
+ buf = g_strdup_printf("ibm,pmemory@%x", drc_idx);
+ child_offset = fdt_add_subnode(fdt, parent_offset, buf);
+ g_free(buf);
+
+ _FDT(child_offset);
+
+ _FDT((fdt_setprop_cell(fdt, child_offset, "reg", drc_idx)));
+ _FDT((fdt_setprop_string(fdt, child_offset, "compatible", "ibm,pmemory")));
+ _FDT((fdt_setprop_string(fdt, child_offset, "device_type", "ibm,pmemory")));
+
+ _FDT((fdt_setprop(fdt, child_offset, "ibm,associativity", associativity,
+ sizeof(associativity))));
+
+ buf = qemu_uuid_unparse_strdup(&nvdimm->uuid);
+ _FDT((fdt_setprop_string(fdt, child_offset, "ibm,unit-guid", buf)));
+ g_free(buf);
+
+ _FDT((fdt_setprop_cell(fdt, child_offset, "ibm,my-drc-index", drc_idx)));
+
+ _FDT((fdt_setprop_u64(fdt, child_offset, "ibm,block-size",
+ SPAPR_MINIMUM_SCM_BLOCK_SIZE)));
+ _FDT((fdt_setprop_u64(fdt, child_offset, "ibm,number-of-blocks",
+ size / SPAPR_MINIMUM_SCM_BLOCK_SIZE)));
+ _FDT((fdt_setprop_cell(fdt, child_offset, "ibm,metadata-size", lsize)));
+
+ _FDT((fdt_setprop_string(fdt, child_offset, "ibm,pmem-application",
+ "operating-system")));
+ _FDT(fdt_setprop(fdt, child_offset, "ibm,cache-flush-required", NULL, 0));
+
+ return child_offset;
+}
+
+void spapr_dt_persistent_memory(void *fdt)
+{
+ int offset = fdt_subnode_offset(fdt, 0, "persistent-memory");
+ GSList *iter, *nvdimms = nvdimm_get_device_list();
+
+ if (offset < 0) {
+ offset = fdt_add_subnode(fdt, 0, "persistent-memory");
+ _FDT(offset);
+ _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1)));
+ _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0)));
+ _FDT((fdt_setprop_string(fdt, offset, "device_type",
+ "ibm,persistent-memory")));
+ }
+
+ /* Create DT entries for cold plugged NVDIMM devices */
+ for (iter = nvdimms; iter; iter = iter->next) {
+ NVDIMMDevice *nvdimm = iter->data;
+
+ spapr_dt_nvdimm(fdt, offset, nvdimm);
+ }
+ g_slist_free(nvdimms);
+
+ return;
+}
+
+static target_ulong h_scm_read_metadata(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ uint32_t drc_index = args[0];
+ uint64_t offset = args[1];
+ uint64_t len = args[2];
+ SpaprDrc *drc = spapr_drc_by_index(drc_index);
+ NVDIMMDevice *nvdimm;
+ NVDIMMClass *ddc;
+ uint64_t data = 0;
+ uint8_t buf[8] = { 0 };
+
+ if (!drc || !drc->dev ||
+ spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) {
+ return H_PARAMETER;
+ }
+
+ if (len != 1 && len != 2 &&
+ len != 4 && len != 8) {
+ return H_P3;
+ }
+
+ nvdimm = NVDIMM(drc->dev);
+ if ((offset + len < offset) ||
+ (nvdimm->label_size < len + offset)) {
+ return H_P2;
+ }
+
+ ddc = NVDIMM_GET_CLASS(nvdimm);
+ ddc->read_label_data(nvdimm, buf, len, offset);
+
+ switch (len) {
+ case 1:
+ data = ldub_p(buf);
+ break;
+ case 2:
+ data = lduw_be_p(buf);
+ break;
+ case 4:
+ data = ldl_be_p(buf);
+ break;
+ case 8:
+ data = ldq_be_p(buf);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ args[0] = data;
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_scm_write_metadata(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ uint32_t drc_index = args[0];
+ uint64_t offset = args[1];
+ uint64_t data = args[2];
+ uint64_t len = args[3];
+ SpaprDrc *drc = spapr_drc_by_index(drc_index);
+ NVDIMMDevice *nvdimm;
+ NVDIMMClass *ddc;
+ uint8_t buf[8] = { 0 };
+
+ if (!drc || !drc->dev ||
+ spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) {
+ return H_PARAMETER;
+ }
+
+ if (len != 1 && len != 2 &&
+ len != 4 && len != 8) {
+ return H_P4;
+ }
+
+ nvdimm = NVDIMM(drc->dev);
+ if ((offset + len < offset) ||
+ (nvdimm->label_size < len + offset)) {
+ return H_P2;
+ }
+
+ switch (len) {
+ case 1:
+ if (data & 0xffffffffffffff00) {
+ return H_P2;
+ }
+ stb_p(buf, data);
+ break;
+ case 2:
+ if (data & 0xffffffffffff0000) {
+ return H_P2;
+ }
+ stw_be_p(buf, data);
+ break;
+ case 4:
+ if (data & 0xffffffff00000000) {
+ return H_P2;
+ }
+ stl_be_p(buf, data);
+ break;
+ case 8:
+ stq_be_p(buf, data);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ ddc = NVDIMM_GET_CLASS(nvdimm);
+ ddc->write_label_data(nvdimm, buf, len, offset);
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_scm_bind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ uint32_t drc_index = args[0];
+ uint64_t starting_idx = args[1];
+ uint64_t no_of_scm_blocks_to_bind = args[2];
+ uint64_t target_logical_mem_addr = args[3];
+ uint64_t continue_token = args[4];
+ uint64_t size;
+ uint64_t total_no_of_scm_blocks;
+ SpaprDrc *drc = spapr_drc_by_index(drc_index);
+ hwaddr addr;
+ NVDIMMDevice *nvdimm;
+
+ if (!drc || !drc->dev ||
+ spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) {
+ return H_PARAMETER;
+ }
+
+ /*
+ * Currently continue token should be zero qemu has already bound
+ * everything and this hcall doesnt return H_BUSY.
+ */
+ if (continue_token > 0) {
+ return H_P5;
+ }
+
+ /* Currently qemu assigns the address. */
+ if (target_logical_mem_addr != 0xffffffffffffffff) {
+ return H_OVERLAP;
+ }
+
+ nvdimm = NVDIMM(drc->dev);
+
+ size = object_property_get_uint(OBJECT(nvdimm),
+ PC_DIMM_SIZE_PROP, &error_abort);
+
+ total_no_of_scm_blocks = size / SPAPR_MINIMUM_SCM_BLOCK_SIZE;
+
+ if (starting_idx > total_no_of_scm_blocks) {
+ return H_P2;
+ }
+
+ if (((starting_idx + no_of_scm_blocks_to_bind) < starting_idx) ||
+ ((starting_idx + no_of_scm_blocks_to_bind) > total_no_of_scm_blocks)) {
+ return H_P3;
+ }
+
+ addr = object_property_get_uint(OBJECT(nvdimm),
+ PC_DIMM_ADDR_PROP, &error_abort);
+
+ addr += starting_idx * SPAPR_MINIMUM_SCM_BLOCK_SIZE;
+
+ /* Already bound, Return target logical address in R5 */
+ args[1] = addr;
+ args[2] = no_of_scm_blocks_to_bind;
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_scm_unbind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ uint32_t drc_index = args[0];
+ uint64_t starting_scm_logical_addr = args[1];
+ uint64_t no_of_scm_blocks_to_unbind = args[2];
+ uint64_t continue_token = args[3];
+ uint64_t size_to_unbind;
+ Range blockrange = range_empty;
+ Range nvdimmrange = range_empty;
+ SpaprDrc *drc = spapr_drc_by_index(drc_index);
+ NVDIMMDevice *nvdimm;
+ uint64_t size, addr;
+
+ if (!drc || !drc->dev ||
+ spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) {
+ return H_PARAMETER;
+ }
+
+ /* continue_token should be zero as this hcall doesn't return H_BUSY. */
+ if (continue_token > 0) {
+ return H_P4;
+ }
+
+ /* Check if starting_scm_logical_addr is block aligned */
+ if (!QEMU_IS_ALIGNED(starting_scm_logical_addr,
+ SPAPR_MINIMUM_SCM_BLOCK_SIZE)) {
+ return H_P2;
+ }
+
+ size_to_unbind = no_of_scm_blocks_to_unbind * SPAPR_MINIMUM_SCM_BLOCK_SIZE;
+ if (no_of_scm_blocks_to_unbind == 0 || no_of_scm_blocks_to_unbind !=
+ size_to_unbind / SPAPR_MINIMUM_SCM_BLOCK_SIZE) {
+ return H_P3;
+ }
+
+ nvdimm = NVDIMM(drc->dev);
+ size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP,
+ &error_abort);
+ addr = object_property_get_int(OBJECT(nvdimm), PC_DIMM_ADDR_PROP,
+ &error_abort);
+
+ range_init_nofail(&nvdimmrange, addr, size);
+ range_init_nofail(&blockrange, starting_scm_logical_addr, size_to_unbind);
+
+ if (!range_contains_range(&nvdimmrange, &blockrange)) {
+ return H_P3;
+ }
+
+ args[1] = no_of_scm_blocks_to_unbind;
+
+ /* let unplug take care of actual unbind */
+ return H_SUCCESS;
+}
+
+#define H_UNBIND_SCOPE_ALL 0x1
+#define H_UNBIND_SCOPE_DRC 0x2
+
+static target_ulong h_scm_unbind_all(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ uint64_t target_scope = args[0];
+ uint32_t drc_index = args[1];
+ uint64_t continue_token = args[2];
+ NVDIMMDevice *nvdimm;
+ uint64_t size;
+ uint64_t no_of_scm_blocks_unbound = 0;
+
+ /* continue_token should be zero as this hcall doesn't return H_BUSY. */
+ if (continue_token > 0) {
+ return H_P4;
+ }
+
+ if (target_scope == H_UNBIND_SCOPE_DRC) {
+ SpaprDrc *drc = spapr_drc_by_index(drc_index);
+
+ if (!drc || !drc->dev ||
+ spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) {
+ return H_P2;
+ }
+
+ nvdimm = NVDIMM(drc->dev);
+ size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP,
+ &error_abort);
+
+ no_of_scm_blocks_unbound = size / SPAPR_MINIMUM_SCM_BLOCK_SIZE;
+ } else if (target_scope == H_UNBIND_SCOPE_ALL) {
+ GSList *list, *nvdimms;
+
+ nvdimms = nvdimm_get_device_list();
+ for (list = nvdimms; list; list = list->next) {
+ nvdimm = list->data;
+ size = object_property_get_int(OBJECT(nvdimm), PC_DIMM_SIZE_PROP,
+ &error_abort);
+
+ no_of_scm_blocks_unbound += size / SPAPR_MINIMUM_SCM_BLOCK_SIZE;
+ }
+ g_slist_free(nvdimms);
+ } else {
+ return H_PARAMETER;
+ }
+
+ args[1] = no_of_scm_blocks_unbound;
+
+ /* let unplug take care of actual unbind */
+ return H_SUCCESS;
+}
+
+static void spapr_scm_register_types(void)
+{
+ /* qemu/scm specific hcalls */
+ spapr_register_hypercall(H_SCM_READ_METADATA, h_scm_read_metadata);
+ spapr_register_hypercall(H_SCM_WRITE_METADATA, h_scm_write_metadata);
+ spapr_register_hypercall(H_SCM_BIND_MEM, h_scm_bind_mem);
+ spapr_register_hypercall(H_SCM_UNBIND_MEM, h_scm_unbind_mem);
+ spapr_register_hypercall(H_SCM_UNBIND_ALL, h_scm_unbind_all);
+}
+
+type_init(spapr_scm_register_types)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 883fe28465..656fdd2216 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -345,6 +345,13 @@ static void rtas_ibm_os_term(PowerPCCPU *cpu,
target_ulong args,
uint32_t nret, target_ulong rets)
{
+ target_ulong msgaddr = rtas_ld(args, 0);
+ char msg[512];
+
+ cpu_physical_memory_read(msgaddr, msg, sizeof(msg) - 1);
+ msg[sizeof(msg) - 1] = 0;
+
+ error_report("OS terminated: %s", msg);
qemu_system_guest_panicked(NULL);
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 91dd00ee91..0dacfcd236 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -188,12 +188,12 @@ static int xilinx_load_device_tree(hwaddr addr,
if (r < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n");
cpu_physical_memory_write(addr, fdt, fdt_size);
+ g_free(fdt);
return fdt_size;
}
static void virtex_init(MachineState *machine)
{
- ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
hwaddr initrd_base = 0;
@@ -204,7 +204,6 @@ static void virtex_init(MachineState *machine)
CPUPPCState *env;
hwaddr ram_base = 0;
DriveInfo *dinfo;
- MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
int kernel_size;
int i;
@@ -221,8 +220,7 @@ static void virtex_init(MachineState *machine)
qemu_register_reset(main_cpu_reset, cpu);
- memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
- memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
+ memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
@@ -265,7 +263,7 @@ static void virtex_init(MachineState *machine)
/* If we failed loading ELF's try a raw image. */
kernel_size = load_image_targphys(kernel_filename,
boot_offset,
- ram_size);
+ machine->ram_size);
boot_info.bootstrap_pc = boot_offset;
high = boot_info.bootstrap_pc + kernel_size + 8192;
}
@@ -276,7 +274,7 @@ static void virtex_init(MachineState *machine)
if (machine->initrd_filename) {
initrd_base = high = ROUND_UP(high, 4);
initrd_size = load_image_targphys(machine->initrd_filename,
- high, ram_size - high);
+ high, machine->ram_size - high);
if (initrd_size < 0) {
error_report("couldn't load ram disk '%s'",
@@ -290,7 +288,7 @@ static void virtex_init(MachineState *machine)
boot_info.fdt = high + (8192 * 2);
boot_info.fdt &= ~8191;
- xilinx_load_device_tree(boot_info.fdt, ram_size,
+ xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
initrd_base, initrd_size,
kernel_cmdline);
}
@@ -302,6 +300,7 @@ static void virtex_machine_init(MachineClass *mc)
mc->desc = "Xilinx Virtex ML507 reference design";
mc->init = virtex_init;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
+ mc->default_ram_id = "ram";
}
DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-04 14:46:22 +0100