diff options
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/Makefile.objs | 16 | ||||
| -rw-r--r-- | hw/riscv/meson.build | 19 | ||||
| -rw-r--r-- | hw/riscv/trace.h | 1 |
3 files changed, 20 insertions, 16 deletions
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs deleted file mode 100644 index 57cc708f5d..0000000000 --- a/hw/riscv/Makefile.objs +++ /dev/null @@ -1,16 +0,0 @@ -obj-y += boot.o -obj-$(CONFIG_SPIKE) += riscv_htif.o -obj-$(CONFIG_HART) += riscv_hart.o -obj-$(CONFIG_OPENTITAN) += opentitan.o -obj-$(CONFIG_SIFIVE_E) += sifive_e.o -obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o -obj-$(CONFIG_SIFIVE) += sifive_clint.o -obj-$(CONFIG_SIFIVE) += sifive_gpio.o -obj-$(CONFIG_SIFIVE) += sifive_plic.o -obj-$(CONFIG_SIFIVE) += sifive_test.o -obj-$(CONFIG_SIFIVE_U) += sifive_u.o -obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o -obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o -obj-$(CONFIG_SIFIVE) += sifive_uart.o -obj-$(CONFIG_SPIKE) += spike.o -obj-$(CONFIG_RISCV_VIRT) += virt.o diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build new file mode 100644 index 0000000000..2de8e5a2fe --- /dev/null +++ b/hw/riscv/meson.build @@ -0,0 +1,19 @@ +riscv_ss = ss.source_set() +riscv_ss.add(files('boot.c')) +riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) +riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) +riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) +riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) +riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) + +hw_arch += {'riscv': riscv_ss} diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h new file mode 100644 index 0000000000..8c0e3ca1f3 --- /dev/null +++ b/hw/riscv/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_riscv.h" |