diff options
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/Kconfig | 1 | ||||
| -rw-r--r-- | hw/riscv/meson.build | 1 | ||||
| -rw-r--r-- | hw/riscv/sifive_test.c | 100 | ||||
| -rw-r--r-- | hw/riscv/virt.c | 2 |
4 files changed, 2 insertions, 102 deletions
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a0461578a6..8e0710001b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -61,6 +61,7 @@ config RISCV_VIRT select SIFIVE select SIFIVE_CLINT select SIFIVE_PLIC + select SIFIVE_TEST config MICROCHIP_PFSOC bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 967572d4f6..f762623288 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c deleted file mode 100644 index 8c70dd69df..0000000000 --- a/hw/riscv/sifive_test.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * QEMU SiFive Test Finisher - * - * Copyright (c) 2018 SiFive, Inc. - * - * Test finisher memory mapped device used to exit simulation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include "qemu/osdep.h" -#include "hw/sysbus.h" -#include "qapi/error.h" -#include "qemu/log.h" -#include "qemu/module.h" -#include "sysemu/runstate.h" -#include "hw/hw.h" -#include "hw/riscv/sifive_test.h" - -static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) -{ - return 0; -} - -static void sifive_test_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) -{ - if (addr == 0) { - int status = val64 & 0xffff; - int code = (val64 >> 16) & 0xffff; - switch (status) { - case FINISHER_FAIL: - exit(code); - case FINISHER_PASS: - exit(0); - case FINISHER_RESET: - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - return; - default: - break; - } - } - qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n", - __func__, (int)addr, val64); -} - -static const MemoryRegionOps sifive_test_ops = { - .read = sifive_test_read, - .write = sifive_test_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 2, - .max_access_size = 4 - } -}; - -static void sifive_test_init(Object *obj) -{ - SiFiveTestState *s = SIFIVE_TEST(obj); - - memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s, - TYPE_SIFIVE_TEST, 0x1000); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); -} - -static const TypeInfo sifive_test_info = { - .name = TYPE_SIFIVE_TEST, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SiFiveTestState), - .instance_init = sifive_test_init, -}; - -static void sifive_test_register_types(void) -{ - type_register_static(&sifive_test_info); -} - -type_init(sifive_test_register_types) - - -/* - * Create Test device. - */ -DeviceState *sifive_test_create(hwaddr addr) -{ - DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); - return dev; -} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0caab8e050..41bd2f38ba 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,12 +30,12 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" +#include "hw/misc/sifive_test.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" |