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-rw-r--r--hw/block/vhost-user-blk.c6
-rw-r--r--hw/display/meson.build25
-rw-r--r--hw/display/tcx.c18
-rw-r--r--hw/display/virtio-gpu-3d.c4
-rw-r--r--hw/dma/sparc32_dma.c49
-rw-r--r--hw/i386/acpi-build.c12
-rw-r--r--hw/i386/intel_iommu.c4
-rw-r--r--hw/i386/pc.c61
-rw-r--r--hw/i386/pc_piix.c2
-rw-r--r--hw/pci-host/sabre.c28
-rw-r--r--hw/pci/pci.c23
-rw-r--r--hw/pci/pcie.c5
-rw-r--r--hw/sparc/sun4m.c21
-rw-r--r--hw/sparc64/sun4u.c7
-rw-r--r--hw/virtio/vhost-vdpa.c4
-rw-r--r--hw/virtio/vhost-vsock.c10
-rw-r--r--hw/virtio/vhost.c28
-rw-r--r--hw/virtio/virtio.c13
18 files changed, 201 insertions, 119 deletions
diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c
index a076b1e54d..f67b29bbf3 100644
--- a/hw/block/vhost-user-blk.c
+++ b/hw/block/vhost-user-blk.c
@@ -131,6 +131,12 @@ static int vhost_user_blk_start(VirtIODevice *vdev)
s->dev.acked_features = vdev->guest_features;
+ ret = vhost_dev_prepare_inflight(&s->dev);
+ if (ret < 0) {
+ error_report("Error set inflight format: %d", -ret);
+ goto err_guest_notifiers;
+ }
+
if (!s->inflight->addr) {
ret = vhost_dev_get_inflight(&s->dev, s->queue_size, s->inflight);
if (ret < 0) {
diff --git a/hw/display/meson.build b/hw/display/meson.build
index 0d5ddecd65..dad3bd2b41 100644
--- a/hw/display/meson.build
+++ b/hw/display/meson.build
@@ -57,15 +57,30 @@ softmmu_ss.add(when: [pixman, 'CONFIG_ATI_VGA'], if_true: files('ati.c', 'ati_2d
if config_all_devices.has_key('CONFIG_VIRTIO_GPU')
virtio_gpu_ss = ss.source_set()
virtio_gpu_ss.add(when: 'CONFIG_VIRTIO_GPU',
- if_true: [files('virtio-gpu-base.c', 'virtio-gpu.c', 'virtio-gpu-3d.c'), pixman, virgl])
+ if_true: [files('virtio-gpu-base.c', 'virtio-gpu.c'), pixman, virgl])
+ virtio_gpu_ss.add(when: ['CONFIG_VIRTIO_GPU', 'CONFIG_VIRGL'],
+ if_true: [files('virtio-gpu-3d.c'), pixman, virgl])
virtio_gpu_ss.add(when: 'CONFIG_VHOST_USER_GPU', if_true: files('vhost-user-gpu.c'))
hw_display_modules += {'virtio-gpu': virtio_gpu_ss}
endif
-softmmu_ss.add(when: ['CONFIG_VIRTIO_GPU', 'CONFIG_VIRTIO_PCI'], if_true: files('virtio-gpu-pci.c'))
-softmmu_ss.add(when: ['CONFIG_VHOST_USER_GPU', 'CONFIG_VIRTIO_PCI'], if_true: files('vhost-user-gpu-pci.c'))
-softmmu_ss.add(when: 'CONFIG_VIRTIO_VGA', if_true: files('virtio-vga.c'))
-softmmu_ss.add(when: 'CONFIG_VHOST_USER_VGA', if_true: files('vhost-user-vga.c'))
+if config_all_devices.has_key('CONFIG_VIRTIO_PCI')
+ virtio_gpu_pci_ss = ss.source_set()
+ virtio_gpu_pci_ss.add(when: ['CONFIG_VIRTIO_GPU', 'CONFIG_VIRTIO_PCI'],
+ if_true: [files('virtio-gpu-pci.c'), pixman])
+ virtio_gpu_pci_ss.add(when: ['CONFIG_VHOST_USER_GPU', 'CONFIG_VIRTIO_PCI'],
+ if_true: files('vhost-user-gpu-pci.c'))
+ hw_display_modules += {'virtio-gpu-pci': virtio_gpu_pci_ss}
+endif
+
+if config_all_devices.has_key('CONFIG_VIRTIO_VGA')
+ virtio_vga_ss = ss.source_set()
+ virtio_vga_ss.add(when: 'CONFIG_VIRTIO_VGA',
+ if_true: [files('virtio-vga.c'), pixman])
+ virtio_vga_ss.add(when: 'CONFIG_VHOST_USER_VGA',
+ if_true: files('vhost-user-vga.c'))
+ hw_display_modules += {'virtio-vga': virtio_vga_ss}
+endif
specific_ss.add(when: [x11, opengl, 'CONFIG_MILKYMIST_TMU2'], if_true: files('milkymist-tmu2.c'))
specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_lcdc.c'))
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index c9d5e45cd1..878ecc8c50 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -549,20 +549,28 @@ static const MemoryRegionOps tcx_stip_ops = {
.read = tcx_stip_readl,
.write = tcx_stip_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
+ .impl = {
.min_access_size = 4,
.max_access_size = 4,
},
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
};
static const MemoryRegionOps tcx_rstip_ops = {
.read = tcx_stip_readl,
.write = tcx_rstip_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
+ .impl = {
.min_access_size = 4,
.max_access_size = 4,
},
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
};
static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
@@ -651,10 +659,14 @@ static const MemoryRegionOps tcx_rblit_ops = {
.read = tcx_blit_readl,
.write = tcx_rblit_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
+ .impl = {
.min_access_size = 4,
.max_access_size = 4,
},
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
};
static void tcx_invalidate_cursor_position(TCXState *s)
diff --git a/hw/display/virtio-gpu-3d.c b/hw/display/virtio-gpu-3d.c
index 1bd33d7aed..0b0c11474d 100644
--- a/hw/display/virtio-gpu-3d.c
+++ b/hw/display/virtio-gpu-3d.c
@@ -17,8 +17,6 @@
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-gpu.h"
-#ifdef CONFIG_VIRGL
-
#include <virglrenderer.h>
static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
@@ -633,5 +631,3 @@ int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g)
return capset2_max_ver ? 2 : 1;
}
-
-#endif /* CONFIG_VIRGL */
diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c
index d20a5bc065..b643b413c5 100644
--- a/hw/dma/sparc32_dma.c
+++ b/hw/dma/sparc32_dma.c
@@ -290,27 +290,26 @@ static const TypeInfo sparc32_dma_device_info = {
static void sparc32_espdma_device_init(Object *obj)
{
DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
+ ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"espdma-mmio", DMA_SIZE);
+
+ object_initialize_child(obj, "esp", &es->esp, TYPE_ESP);
}
static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
{
- DeviceState *d;
- SysBusESPState *sysbus;
- ESPState *esp;
-
- d = qdev_new(TYPE_ESP);
- object_property_add_child(OBJECT(dev), "esp", OBJECT(d));
- sysbus = ESP(d);
- esp = &sysbus->esp;
+ ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev);
+ SysBusESPState *sysbus = ESP(&es->esp);
+ ESPState *esp = &sysbus->esp;
+
esp->dma_memory_read = espdma_memory_read;
esp->dma_memory_write = espdma_memory_write;
esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
sysbus->it_shift = 2;
esp->dma_enabled = 1;
- sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(sysbus), &error_fatal);
}
static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
@@ -331,24 +330,21 @@ static const TypeInfo sparc32_espdma_device_info = {
static void sparc32_ledma_device_init(Object *obj)
{
DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
+ LEDMADeviceState *ls = SPARC32_LEDMA_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"ledma-mmio", DMA_SIZE);
+
+ object_initialize_child(obj, "lance", &ls->lance, TYPE_LANCE);
}
static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
{
- DeviceState *d;
- NICInfo *nd = &nd_table[0];
+ LEDMADeviceState *s = SPARC32_LEDMA_DEVICE(dev);
+ SysBusPCNetState *lance = SYSBUS_PCNET(&s->lance);
- /* FIXME use qdev NIC properties instead of nd_table[] */
- qemu_check_nic_model(nd, TYPE_LANCE);
-
- d = qdev_new(TYPE_LANCE);
- object_property_add_child(OBJECT(dev), "lance", OBJECT(d));
- qdev_set_nic_properties(d, nd);
- object_property_set_link(OBJECT(d), "dma", OBJECT(dev), &error_abort);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
+ object_property_set_link(OBJECT(lance), "dma", OBJECT(dev), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(lance), &error_fatal);
}
static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
@@ -379,10 +375,9 @@ static void sparc32_dma_realize(DeviceState *dev, Error **errp)
return;
}
- espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE);
+ espdma = DEVICE(&s->espdma);
object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort);
- object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma));
- sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(espdma), &error_fatal);
esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
sbd = SYS_BUS_DEVICE(esp);
@@ -394,10 +389,9 @@ static void sparc32_dma_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->dmamem, 0x0,
sysbus_mmio_get_region(sbd, 0));
- ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE);
+ ledma = DEVICE(&s->ledma);
object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort);
- object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma));
- sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(ledma), &error_fatal);
lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
sbd = SYS_BUS_DEVICE(lance);
@@ -421,6 +415,11 @@ static void sparc32_dma_init(Object *obj)
memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
sysbus_init_mmio(sbd, &s->dmamem);
+
+ object_initialize_child(obj, "espdma", &s->espdma,
+ TYPE_SPARC32_ESPDMA_DEVICE);
+ object_initialize_child(obj, "ledma", &s->ledma,
+ TYPE_SPARC32_LEDMA_DEVICE);
}
static void sparc32_dma_class_init(ObjectClass *klass, void *data)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index e3a4bc206c..4f66642d88 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -786,8 +786,14 @@ static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
crs_range_insert(temp_range_set.io_ranges,
range_base, range_limit);
} else { /* "memory" */
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges, range_base,
+ range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
}
}
@@ -866,6 +872,8 @@ static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
crs_range_merge(temp_range_set.mem_ranges);
for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
+ assert(entry->limit <= UINT32_MAX &&
+ (entry->limit - entry->base + 1) <= UINT32_MAX);
aml_append(crs,
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED, AML_NON_CACHEABLE,
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 749eb6ad63..70ac837733 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2665,7 +2665,7 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
if (addr + size > DMAR_REG_SIZE) {
error_report_once("%s: MMIO over range: addr=0x%" PRIx64
- " size=0x%u", __func__, addr, size);
+ " size=0x%x", __func__, addr, size);
return (uint64_t)-1;
}
@@ -2716,7 +2716,7 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
if (addr + size > DMAR_REG_SIZE) {
error_report_once("%s: MMIO over range: addr=0x%" PRIx64
- " size=0x%u", __func__, addr, size);
+ " size=0x%x", __func__, addr, size);
return;
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0d9bd7d635..5e6c0023e0 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1142,28 +1142,31 @@ void pc_basic_device_init(struct PCMachineState *pcms,
* Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
* when the HPET wants to take over. Thus we have to disable the latter.
*/
- if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
+ if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
+ kvm_has_pit_state2())) {
hpet = qdev_try_new(TYPE_HPET);
- if (hpet) {
- /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
- * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
- * IRQ8 and IRQ2.
- */
- uint8_t compat = object_property_get_uint(OBJECT(hpet),
- HPET_INTCAP, NULL);
- if (!compat) {
- qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
- }
- sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
+ if (!hpet) {
+ error_report("couldn't create HPET device");
+ exit(1);
+ }
+ /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
+ * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
+ * IRQ8 and IRQ2.
+ */
+ uint8_t compat = object_property_get_uint(OBJECT(hpet),
+ HPET_INTCAP, NULL);
+ if (!compat) {
+ qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
+ }
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
- for (i = 0; i < GSI_NUM_PINS; i++) {
- sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
- }
- pit_isa_irq = -1;
- pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
- rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
+ for (i = 0; i < GSI_NUM_PINS; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
}
+ pit_isa_irq = -1;
+ pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
+ rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
}
*rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
@@ -1529,6 +1532,20 @@ static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
pcms->pit_enabled = value;
}
+static bool pc_machine_get_hpet(Object *obj, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+
+ return pcms->hpet_enabled;
+}
+
+static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+
+ pcms->hpet_enabled = value;
+}
+
static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
@@ -1579,6 +1596,9 @@ static void pc_machine_initfn(Object *obj)
pcms->smbus_enabled = true;
pcms->sata_enabled = true;
pcms->pit_enabled = true;
+#ifdef CONFIG_HPET
+ pcms->hpet_enabled = true;
+#endif
pc_system_flash_create(pcms);
pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
@@ -1699,6 +1719,9 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
object_class_property_add_bool(oc, PC_MACHINE_PIT,
pc_machine_get_pit, pc_machine_set_pit);
+
+ object_class_property_add_bool(oc, "hpet",
+ pc_machine_get_hpet, pc_machine_set_hpet);
}
static const TypeInfo pc_machine_info = {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 0cf22a57ad..13d1628f13 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -216,7 +216,7 @@ static void pc_init1(MachineState *machine,
i440fx_state = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
&error_abort);
- no_hpet = 1;
+ pcms->hpet_enabled = false;
}
isa_bus_irqs(isa_bus, x86ms->gsi);
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 5ac6283623..f41a0cc301 100644
--- a/hw/pci-host/sabre.c
+++ b/hw/pci-host/sabre.c
@@ -44,7 +44,7 @@
/*
* Chipset docs:
* PBM: "UltraSPARC IIi User's Manual",
- * http://www.sun.com/processors/manuals/805-0087.pdf
+ * https://web.archive.org/web/20030403110020/http://www.sun.com/processors/manuals/805-0087.pdf
*/
#define PBM_PCI_IMR_MASK 0x7fffffff
@@ -120,7 +120,7 @@ static void sabre_config_write(void *opaque, hwaddr addr,
trace_sabre_config_write(addr, val);
- switch (addr & 0xffff) {
+ switch (addr) {
case 0x30 ... 0x4f: /* DMA error registers */
/* XXX: not implemented yet */
break;
@@ -195,32 +195,25 @@ static uint64_t sabre_config_read(void *opaque,
hwaddr addr, unsigned size)
{
SabreState *s = opaque;
- uint32_t val;
+ uint32_t val = 0;
- switch (addr & 0xffff) {
+ switch (addr) {
case 0x30 ... 0x4f: /* DMA error registers */
- val = 0;
/* XXX: not implemented yet */
break;
case 0xc00 ... 0xc3f: /* PCI interrupt control */
if (addr & 4) {
val = s->pci_irq_map[(addr & 0x3f) >> 3];
- } else {
- val = 0;
}
break;
case 0x1000 ... 0x107f: /* OBIO interrupt control */
if (addr & 4) {
val = s->obio_irq_map[(addr & 0xff) >> 3];
- } else {
- val = 0;
}
break;
case 0x1080 ... 0x108f: /* PCI bus error */
if (addr & 4) {
val = s->pci_err_irq_map[(addr & 0xf) >> 3];
- } else {
- val = 0;
}
break;
case 0x2000 ... 0x202f: /* PCI control */
@@ -229,8 +222,6 @@ static uint64_t sabre_config_read(void *opaque,
case 0xf020 ... 0xf027: /* Reset control */
if (addr & 4) {
val = s->reset_control;
- } else {
- val = 0;
}
break;
case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
@@ -239,7 +230,6 @@ static uint64_t sabre_config_read(void *opaque,
case 0xf000 ... 0xf01f: /* FFB config, memory control */
/* we don't care */
default:
- val = 0;
break;
}
trace_sabre_config_read(addr, val);
@@ -378,16 +368,8 @@ static void sabre_realize(DeviceState *dev, Error **errp)
{
SabreState *s = SABRE(dev);
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
- SysBusDevice *sbd = SYS_BUS_DEVICE(s);
PCIDevice *pci_dev;
- /* sabre_config */
- sysbus_mmio_map(sbd, 0, s->special_base);
- /* PCI configuration space */
- sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
- /* pci_ioport */
- sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL);
-
memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
memory_region_add_subregion(get_system_memory(), s->mem_base,
&s->pci_mmio);
@@ -396,7 +378,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
pci_sabre_set_irq, pci_sabre_map_irq, s,
&s->pci_mmio,
&s->pci_ioport,
- 0, 32, TYPE_PCI_BUS);
+ 0, 0x40, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 100c9381c2..0131d9d02c 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -248,6 +248,14 @@ static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
d->irq_state |= level << irq_num;
}
+static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change)
+{
+ assert(irq_num >= 0);
+ assert(irq_num < bus->nirq);
+ bus->irq_count[irq_num] += change;
+ bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
+}
+
static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
{
PCIBus *bus;
@@ -258,8 +266,7 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
break;
pci_dev = bus->parent_dev;
}
- bus->irq_count[irq_num] += change;
- bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
+ pci_bus_change_irq_level(bus, irq_num, change);
}
int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
@@ -1141,14 +1148,16 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
uint32_t addr; /* offset in pci config space */
uint64_t wmask;
pcibus_t size = memory_region_size(memory);
+ uint8_t hdr_type;
assert(region_num >= 0);
assert(region_num < PCI_NUM_REGIONS);
- if (size & (size-1)) {
- error_report("ERROR: PCI region size must be pow2 "
- "type=0x%x, size=0x%"FMT_PCIBUS"", type, size);
- exit(1);
- }
+ assert(is_power_of_2(size));
+
+ /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
+ hdr_type =
+ pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
+ assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2);
r = &pci_dev->io_regions[region_num];
r->addr = PCI_BAR_UNMAPPED;
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 5b48bae0f6..d4010cf8f3 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -971,8 +971,9 @@ void pcie_ats_init(PCIDevice *dev, uint16_t offset)
dev->exp.ats_cap = offset;
- /* Invalidate Queue Depth 0, Page Aligned Request 0 */
- pci_set_word(dev->config + offset + PCI_ATS_CAP, 0);
+ /* Invalidate Queue Depth 0, Page Aligned Request 1 */
+ pci_set_word(dev->config + offset + PCI_ATS_CAP,
+ PCI_ATS_CAP_PAGE_ALIGNED);
/* STU 0, Disabled by default */
pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 38d1e0fd12..66fecb152a 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -319,7 +319,7 @@ static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
static void *sparc32_dma_init(hwaddr dma_base,
hwaddr esp_base, qemu_irq espdma_irq,
- hwaddr le_base, qemu_irq ledma_irq)
+ hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd)
{
DeviceState *dma;
ESPDMADeviceState *espdma;
@@ -328,16 +328,11 @@ static void *sparc32_dma_init(hwaddr dma_base,
SysBusPCNetState *lance;
dma = qdev_new(TYPE_SPARC32_DMA);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
-
espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "espdma"));
sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
- sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
- scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "ledma"));
@@ -345,6 +340,14 @@ static void *sparc32_dma_init(hwaddr dma_base,
lance = SYSBUS_PCNET(object_resolve_path_component(
OBJECT(ledma), "lance"));
+ qdev_set_nic_properties(DEVICE(lance), nd);
+
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
+ scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
+
sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
return dma;
@@ -850,6 +853,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
unsigned int max_cpus = machine->smp.max_cpus;
Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
TYPE_MEMORY_BACKEND, NULL);
+ NICInfo *nd = &nd_table[0];
if (machine->ram_size > hwdef->max_mem) {
error_report("Too much memory for this machine: %" PRId64 ","
@@ -910,9 +914,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
hwdef->iommu_pad_base, hwdef->iommu_pad_len);
}
+ qemu_check_nic_model(nd, TYPE_LANCE);
sparc32_dma_init(hwdef->dma_base,
hwdef->esp_base, slavio_irq[18],
- hwdef->le_base, slavio_irq[16]);
+ hwdef->le_base, slavio_irq[16], nd);
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
@@ -1049,7 +1054,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
machine->initrd_filename,
machine->ram_size, &initrd_size);
- nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
+ nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline,
machine->boot_order, machine->ram_size, kernel_size,
graphic_width, graphic_height, graphic_depth,
hwdef->nvram_machine_id, "Sun4m");
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 05e659c8a4..2f8fc670cf 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -588,6 +588,13 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
+ /* sabre_config */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
+ /* PCI configuration space */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
+ /* pci_ioport */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
+
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 4f1039910a..01d2101d09 100644
--- a/hw/virtio/vhost-vdpa.c
+++ b/hw/virtio/vhost-vdpa.c
@@ -90,7 +90,7 @@ static void vhost_vdpa_listener_begin(MemoryListener *listener)
{
struct vhost_vdpa *v = container_of(listener, struct vhost_vdpa, listener);
struct vhost_dev *dev = v->dev;
- struct vhost_msg_v2 msg;
+ struct vhost_msg_v2 msg = {};
int fd = v->device_fd;
if (!(dev->backend_cap & (0x1ULL << VHOST_BACKEND_F_IOTLB_BATCH))) {
@@ -110,7 +110,7 @@ static void vhost_vdpa_listener_commit(MemoryListener *listener)
{
struct vhost_vdpa *v = container_of(listener, struct vhost_vdpa, listener);
struct vhost_dev *dev = v->dev;
- struct vhost_msg_v2 msg;
+ struct vhost_msg_v2 msg = {};
int fd = v->device_fd;
if (!(dev->backend_cap & (0x1ULL << VHOST_BACKEND_F_IOTLB_BATCH))) {
diff --git a/hw/virtio/vhost-vsock.c b/hw/virtio/vhost-vsock.c
index f9db4beb47..8ddfb9abfe 100644
--- a/hw/virtio/vhost-vsock.c
+++ b/hw/virtio/vhost-vsock.c
@@ -16,6 +16,7 @@
#include "qapi/error.h"
#include "hw/virtio/virtio-access.h"
#include "qemu/error-report.h"
+#include "qemu/sockets.h"
#include "hw/qdev-properties.h"
#include "hw/virtio/vhost-vsock.h"
#include "monitor/monitor.h"
@@ -148,6 +149,13 @@ static void vhost_vsock_device_realize(DeviceState *dev, Error **errp)
error_prepend(errp, "vhost-vsock: unable to parse vhostfd: ");
return;
}
+
+ ret = qemu_try_set_nonblock(vhostfd);
+ if (ret < 0) {
+ error_setg_errno(errp, -ret,
+ "vhost-vsock: unable to set non-blocking mode");
+ return;
+ }
} else {
vhostfd = open("/dev/vhost-vsock", O_RDWR);
if (vhostfd < 0) {
@@ -155,6 +163,8 @@ static void vhost_vsock_device_realize(DeviceState *dev, Error **errp)
"vhost-vsock: failed to open vhost device");
return;
}
+
+ qemu_set_nonblock(vhostfd);
}
vhost_vsock_common_realize(vdev, "vhost-vsock");
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 3077fa6ef5..f2482378c6 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -172,16 +172,6 @@ static uint64_t vhost_get_log_size(struct vhost_dev *dev)
reg->memory_size);
log_size = MAX(log_size, last / VHOST_LOG_CHUNK + 1);
}
- for (i = 0; i < dev->nvqs; ++i) {
- struct vhost_virtqueue *vq = dev->vqs + i;
-
- if (!vq->used_phys && !vq->used_size) {
- continue;
- }
-
- uint64_t last = vq->used_phys + vq->used_size - 1;
- log_size = MAX(log_size, last / VHOST_LOG_CHUNK + 1);
- }
return log_size;
}
@@ -1655,6 +1645,24 @@ int vhost_dev_load_inflight(struct vhost_inflight *inflight, QEMUFile *f)
return 0;
}
+int vhost_dev_prepare_inflight(struct vhost_dev *hdev)
+{
+ int r;
+
+ if (hdev->vhost_ops->vhost_get_inflight_fd == NULL ||
+ hdev->vhost_ops->vhost_set_inflight_fd == NULL) {
+ return 0;
+ }
+
+ r = vhost_dev_set_features(hdev, hdev->log_enabled);
+ if (r < 0) {
+ VHOST_OPS_DEBUG("vhost_dev_prepare_inflight failed");
+ return r;
+ }
+
+ return 0;
+}
+
int vhost_dev_set_inflight(struct vhost_dev *dev,
struct vhost_inflight *inflight)
{
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 6f8f865aff..ceb58fda6c 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -17,6 +17,7 @@
#include "trace.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
+#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "hw/virtio/virtio.h"
@@ -3160,12 +3161,12 @@ int virtio_load(VirtIODevice *vdev, QEMUFile *f, int version_id)
nheads = vring_avail_idx(&vdev->vq[i]) - vdev->vq[i].last_avail_idx;
/* Check it isn't doing strange things with descriptor numbers. */
if (nheads > vdev->vq[i].vring.num) {
- error_report("VQ %d size 0x%x Guest index 0x%x "
- "inconsistent with Host index 0x%x: delta 0x%x",
- i, vdev->vq[i].vring.num,
- vring_avail_idx(&vdev->vq[i]),
- vdev->vq[i].last_avail_idx, nheads);
- return -1;
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "VQ %d size 0x%x Guest index 0x%x "
+ "inconsistent with Host index 0x%x: delta 0x%x",
+ i, vdev->vq[i].vring.num,
+ vring_avail_idx(&vdev->vq[i]),
+ vdev->vq[i].last_avail_idx, nheads);
}
vdev->vq[i].used_idx = vring_used_idx(&vdev->vq[i]);
vdev->vq[i].shadow_avail_idx = vring_avail_idx(&vdev->vq[i]);
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-26 13:51:24 +0200