diff options
Diffstat (limited to 'hw')
48 files changed, 158 insertions, 87 deletions
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 8d71a30617..d28f57199f 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -181,7 +181,7 @@ static void clipper_machine_init(MachineClass *mc) mc->init = clipper_init; mc->block_default_type = IF_IDE; mc->max_cpus = 4; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = ALPHA_CPU_TYPE_NAME("ev67"); mc->default_ram_id = "ram"; } diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3d86691ae0..61635f52c4 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -69,6 +69,7 @@ config INTEGRATOR select INTEGRATOR_DEBUG select PL011 # UART select PL031 # RTC + select PL041 # audio select PL050 # keyboard/mouse select PL110 # pl111 LCD controller select PL181 # display diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index cc845b8534..6d69010d06 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -642,6 +642,7 @@ static void integratorcp_init(MachineState *machine) qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); qdev_connect_gpio_out(dev, 1, qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); + sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL); if (nd_table[0].used) smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 1cba9fc302..8409ba853d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -39,6 +39,7 @@ #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "hw/usb.h" +#include "hw/char/pl011.h" #include "net/net.h" #define RAMLIMIT_GB 8192 @@ -409,7 +410,7 @@ static void create_uart(const SBSAMachineState *sms, int uart, { hwaddr base = sbsa_ref_memmap[uart].base; int irq = sbsa_ref_irqmap[uart]; - DeviceState *dev = qdev_create(NULL, "pl011"); + DeviceState *dev = qdev_create(NULL, TYPE_PL011); SysBusDevice *s = SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", chr); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a8191a3e75..856808599d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -74,6 +74,7 @@ #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" #include "hw/virtio/virtio-iommu.h" +#include "hw/char/pl011.h" #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -727,7 +728,7 @@ static void create_uart(const VirtMachineState *vms, int uart, int irq = vms->irqmap[uart]; const char compat[] = "arm,pl011\0arm,primecell"; const char clocknames[] = "uartclk\0apb_pclk"; - DeviceState *dev = qdev_create(NULL, "pl011"); + DeviceState *dev = qdev_create(NULL, TYPE_PL011); SysBusDevice *s = SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", chr); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3d439a45d5..571cdcd599 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -29,6 +29,7 @@ #include "hw/loader.h" #include "hw/misc/zynq-xadc.h" #include "hw/ssi/ssi.h" +#include "hw/usb/chipidea.h" #include "qemu/error-report.h" #include "hw/sd/sdhci.h" #include "hw/char/cadence_uart.h" @@ -225,8 +226,8 @@ static void zynq_init(MachineState *machine) zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); - sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); - sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 1cf3daaf4f..403fc7b881 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -22,6 +22,7 @@ #include "hw/misc/unimp.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/arm/xlnx-versal.h" +#include "hw/char/pl011.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define GEM_REVISION 0x40070106 @@ -144,7 +145,7 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic) DeviceState *dev; MemoryRegion *mr; - dev = qdev_create(NULL, "pl011"); + dev = qdev_create(NULL, TYPE_PL011); s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", serial_hd(i)); object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c index 3b9caeb2fa..288a87a814 100644 --- a/hw/block/dataplane/xen-block.c +++ b/hw/block/dataplane/xen-block.c @@ -685,12 +685,24 @@ void xen_block_dataplane_stop(XenBlockDataPlane *dataplane) return; } + xendev = dataplane->xendev; + aio_context_acquire(dataplane->ctx); + if (dataplane->event_channel) { + /* Only reason for failure is a NULL channel */ + xen_device_set_event_channel_context(xendev, dataplane->event_channel, + qemu_get_aio_context(), + &error_abort); + } /* Xen doesn't have multiple users for nodes, so this can't fail */ blk_set_aio_context(dataplane->blk, qemu_get_aio_context(), &error_abort); aio_context_release(dataplane->ctx); - xendev = dataplane->xendev; + /* + * Now that the context has been moved onto the main thread, cancel + * further processing. + */ + qemu_bh_cancel(dataplane->bh); if (dataplane->event_channel) { Error *local_err = NULL; @@ -807,7 +819,7 @@ void xen_block_dataplane_start(XenBlockDataPlane *dataplane, } dataplane->event_channel = - xen_device_bind_event_channel(xendev, dataplane->ctx, event_channel, + xen_device_bind_event_channel(xendev, event_channel, xen_block_dataplane_event, dataplane, &local_err); if (local_err) { @@ -818,7 +830,11 @@ void xen_block_dataplane_start(XenBlockDataPlane *dataplane, aio_context_acquire(dataplane->ctx); /* If other users keep the BlockBackend in the iothread, that's ok */ blk_set_aio_context(dataplane->blk, dataplane->ctx, NULL); + /* Only reason for failure is a NULL channel */ + xen_device_set_event_channel_context(xendev, dataplane->event_channel, + dataplane->ctx, &error_abort); aio_context_release(dataplane->ctx); + return; stop: diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 7f93bfeb88..2047114fca 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -8,6 +8,7 @@ #include "qapi/qmp/qerror.h" #include "qemu/ctype.h" #include "qemu/error-report.h" +#include "qapi/qapi-types-migration.h" #include "hw/block/block.h" #include "net/hub.h" #include "qapi/visitor.h" @@ -639,6 +640,18 @@ const PropertyInfo qdev_prop_fdc_drive_type = { .set_default_value = set_default_value_enum, }; +/* --- MultiFDCompression --- */ + +const PropertyInfo qdev_prop_multifd_compression = { + .name = "MultiFDCompression", + .description = "multifd_compression values, " + "none/zlib/zstd", + .enum_table = &MultiFDCompression_lookup, + .get = get_enum, + .set = set_enum, + .set_default_value = set_default_value_enum, +}; + /* --- pci address --- */ /* diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 1f8bc8a196..b4f6a7e8a5 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -16,6 +16,8 @@ #include "hw/qdev-properties.h" #include "hw/core/cpu.h" +#define A9_GIC_NUM_PRIORITY_BITS 5 + static void a9mp_priv_set_irq(void *opaque, int irq, int level) { A9MPPrivState *s = (A9MPPrivState *)opaque; @@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + A9_GIC_NUM_PRIORITY_BITS); /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 2e3e87cc1b..ab9fadb67c 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" +#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 static void mpcore_priv_set_irq(void *opaque, int irq, int level) { @@ -86,6 +87,10 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + ARM11MPCORE_NUM_GIC_PRIORITY_BITS); + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index cf6790fd6f..75e5c993b5 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -344,7 +344,7 @@ static void axisdev88_machine_init(MachineClass *mc) { mc->desc = "AXIS devboard 88"; mc->init = axisdev88_init; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32"); mc->default_ram_id = "axisdev88.ram"; } diff --git a/hw/display/edid-generate.c b/hw/display/edid-generate.c index 75c945a948..e58472fde5 100644 --- a/hw/display/edid-generate.c +++ b/hw/display/edid-generate.c @@ -360,8 +360,8 @@ void qemu_edid_generate(uint8_t *edid, size_t size, edid[20] = 0xa5; /* screen size: undefined */ - edid[21] = info->prefx * info->dpi / 2540; - edid[22] = info->prefy * info->dpi / 2540; + edid[21] = info->prefx * 254 / 100 / info->dpi; + edid[22] = info->prefy * 254 / 100 / info->dpi; /* display gamma: 2.2 */ edid[23] = 220 - 100; diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 21a43a1d5e..227da69a50 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -2136,7 +2136,7 @@ static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); qxl->rom_size = qxl_rom_size(); - memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", + memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", qxl->rom_size, &error_fatal); init_qxl_rom(qxl); init_qxl_ram(qxl); diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 67181e75ba..bf18767e24 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -290,7 +290,7 @@ static void machine_hppa_machine_init(MachineClass *mc) mc->block_default_type = IF_SCSI; mc->max_cpus = HPPA_MAX_CPUS; mc->default_cpus = 1; - mc->is_default = 1; + mc->is_default = true; mc->default_ram_size = 512 * MiB; mc->default_boot_order = "cd"; mc->default_ram_id = "ram"; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index fa12203079..9088db8fb6 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -423,7 +423,7 @@ static void pc_i440fx_5_0_machine_options(MachineClass *m) PCMachineClass *pcmc = PC_MACHINE_CLASS(m); pc_i440fx_machine_options(m); m->alias = "pc"; - m->is_default = 1; + m->is_default = true; pcmc->default_cpu_version = 1; } @@ -434,7 +434,7 @@ static void pc_i440fx_4_2_machine_options(MachineClass *m) { pc_i440fx_5_0_machine_options(m); m->alias = NULL; - m->is_default = 0; + m->is_default = false; compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len); compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len); } @@ -446,7 +446,7 @@ static void pc_i440fx_4_1_machine_options(MachineClass *m) { pc_i440fx_4_2_machine_options(m); m->alias = NULL; - m->is_default = 0; + m->is_default = false; compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len); compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len); } @@ -459,7 +459,7 @@ static void pc_i440fx_4_0_machine_options(MachineClass *m) PCMachineClass *pcmc = PC_MACHINE_CLASS(m); pc_i440fx_4_1_machine_options(m); m->alias = NULL; - m->is_default = 0; + m->is_default = false; pcmc->default_cpu_version = CPU_VERSION_LEGACY; compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); @@ -473,7 +473,7 @@ static void pc_i440fx_3_1_machine_options(MachineClass *m) PCMachineClass *pcmc = PC_MACHINE_CLASS(m); pc_i440fx_4_0_machine_options(m); - m->is_default = 0; + m->is_default = false; pcmc->do_not_add_smb_acpi = true; m->smbus_no_migration_support = true; m->alias = NULL; diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1d7da7baa2..c60dc6b5e6 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) return ret; } +static uint32_t gic_fullprio_mask(GICState *s, int cpu) +{ + /* + * Return a mask word which clears the unimplemented priority + * bits from a priority value for an interrupt. (Not to be + * confused with the group priority, whose mask depends on BPR.) + */ + int priBits; + + if (gic_is_vcpu(cpu)) { + priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS; + } else { + priBits = s->n_prio_bits; + } + return ~0U << (8 - priBits); +} + void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs) { @@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, val = 0x80 | (val >> 1); /* Non-secure view */ } + val &= gic_fullprio_mask(s, cpu); + if (irq < GIC_INTERNAL) { s->priority1[irq][cpu] = val; } else { @@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, } prio = (prio << 1) & 0xff; /* Non-secure view */ } - return prio; + return prio & gic_fullprio_mask(s, cpu); } static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, @@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, return; } } - s->priority_mask[cpu] = pmask; + s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); } static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) @@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) return; } + if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS || + (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS : + s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) { + error_setg(errp, "num-priority-bits cannot be greater than %d" + " or less than %d", GIC_MAX_PRIORITY_BITS, + s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS : + GIC_MIN_PRIORITY_BITS); + return; + } + /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if * enabled, virtualization extensions related interfaces (main virtual * interface (s->vifaceiomem[0]) and virtual CPU interface). diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index e6c4fe7a5a..7b44d5625b 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = { DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), /* True if the GIC should implement the virtualization extensions */ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), + DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9deb15e7e6..d7df423a7a 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -551,7 +551,16 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); } + } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) { + error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); + error_append_hint(errp, + "Perhaps the host CPU does not support GICv2?\n"); } else if (ret != -ENODEV && ret != -ENOTSUP) { + /* + * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that + * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE", + * and that we will get a GICv2 via KVM_CREATE_IRQCHIP. + */ error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); return; } diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22a43e4984..a62587eb3f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 */ cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 */ cpu->env.v7m.nsacr = value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &= ~7; cpu->env.v7m.fpcar[attrs.secure] = value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &= 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] = value; } diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c index 4e0a98c117..b842f74344 100644 --- a/hw/lm32/lm32_boards.c +++ b/hw/lm32/lm32_boards.c @@ -295,7 +295,7 @@ static void lm32_evr_class_init(ObjectClass *oc, void *data) mc->desc = "LatticeMico32 EVR32 eval system"; mc->init = lm32_evr_init; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); mc->default_ram_size = 64 * MiB; mc->default_ram_id = "lm32_evr.sdram"; @@ -313,7 +313,6 @@ static void lm32_uclinux_class_init(ObjectClass *oc, void *data) mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems"; mc->init = lm32_uclinux_init; - mc->is_default = 0; mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); mc->default_ram_size = 64 * MiB; mc->default_ram_id = "lm32_uclinux.sdram"; diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c index 5c72266e58..85913bb68b 100644 --- a/hw/lm32/milkymist.c +++ b/hw/lm32/milkymist.c @@ -219,7 +219,6 @@ static void milkymist_machine_init(MachineClass *mc) { mc->desc = "Milkymist One"; mc->init = milkymist_init; - mc->is_default = 0; mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); mc->default_ram_size = 128 * MiB; mc->default_ram_id = "milkymist.sdram"; diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 31622c71cb..b84c152ce3 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -350,7 +350,7 @@ static void mcf5208evb_machine_init(MachineClass *mc) { mc->desc = "MCF5208EVB"; mc->init = mcf5208evb_init; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); mc->default_ram_id = "mcf5208.ram"; } diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index a4c4bc14cb..c5699f6f3e 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -438,7 +438,6 @@ static void q800_machine_class_init(ObjectClass *oc, void *data) mc->init = q800_init; mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); mc->max_cpus = 1; - mc->is_default = 0; mc->block_default_type = IF_SCSI; mc->default_ram_id = "m68k_mac.ram"; } diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 09486bc8bf..0a2640c40b 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -216,7 +216,6 @@ static void petalogix_ml605_machine_init(MachineClass *mc) { mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian"; mc->init = petalogix_ml605_init; - mc->is_default = 0; } DEFINE_MACHINE("petalogix-ml605", petalogix_ml605_machine_init) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 849bafc186..0bb6cdea8d 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -132,7 +132,7 @@ static void petalogix_s3adsp1800_machine_init(MachineClass *mc) { mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800"; mc->init = petalogix_s3adsp1800_init; - mc->is_default = 1; + mc->is_default = true; } DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init) diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index c373ab066b..4727b1d3a4 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -319,9 +319,8 @@ static void mips_fulong2e_init(MachineState *machine) } /* allocate RAM */ - memory_region_init_ram(bios, NULL, "fulong2e.bios", BIOS_SIZE, + memory_region_init_rom(bios, NULL, "fulong2e.bios", BIOS_SIZE, &error_fatal); - memory_region_set_readonly(bios, true); memory_region_add_subregion(address_space_mem, 0, machine->ram); memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 863ed45659..796730b11d 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -77,7 +77,7 @@ void cpu_mips_irq_init_cpu(MIPSCPU *cpu) qemu_irq *qi; int i; - qi = qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8); + qi = qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8); for (i = 0; i < 8; i++) { env->irq[i] = qi[i]; } diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 32fbd10b4e..afea52b41b 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -197,9 +197,8 @@ static void mips_jazz_init(MachineState *machine, /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); - memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, + memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, &error_fatal); - memory_region_set_readonly(bios, true); memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, 0, MAGNUM_BIOS_SIZE); memory_region_add_subregion(address_space, 0x1fc00000LL, bios); @@ -265,9 +264,8 @@ static void mips_jazz_init(MachineState *machine, { /* Simple ROM, so user doesn't have to provide one */ MemoryRegion *rom_mr = g_new(MemoryRegion, 1); - memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, + memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000, &error_fatal); - memory_region_set_readonly(rom_mr, true); uint8_t *rom = memory_region_get_ram_ptr(rom_mr); memory_region_add_subregion(address_space, 0x60000000, rom_mr); rom[0] = 0x10; /* Mips G364 */ diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 6e7ba9235d..d380f73d7b 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1439,7 +1439,7 @@ static void mips_malta_machine_init(MachineClass *mc) mc->init = mips_malta_init; mc->block_default_type = IF_IDE; mc->max_cpus = 16; - mc->is_default = 1; + mc->is_default = true; #ifdef TARGET_MIPS64 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); #else diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index b2555ddb89..d220318939 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -165,9 +165,8 @@ mips_mipssim_init(MachineState *machine) qemu_register_reset(main_cpu_reset, reset_info); /* Allocate RAM. */ - memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE, + memory_region_init_rom(bios, NULL, "mips_mipssim.bios", BIOS_SIZE, &error_fatal); - memory_region_set_readonly(bios, true); memory_region_add_subregion(address_space_mem, 0, machine->ram); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 258cd91578..ad8b75e286 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -237,9 +237,8 @@ void mips_r4k_init(MachineState *machine) dinfo = drive_get(IF_PFLASH, 0, 0); if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { bios = g_new(MemoryRegion, 1); - memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE, + memory_region_init_rom(bios, NULL, "mips_r4k.bios", BIOS_SIZE, &error_fatal); - memory_region_set_readonly(bios, true); memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios); load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index 1d06e39fcb..51a98287b5 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -150,7 +150,7 @@ static void moxiesim_machine_init(MachineClass *mc) { mc->desc = "Moxie simulator platform"; mc->init = moxiesim_init; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = MOXIE_CPU_TYPE_NAME("MoxieLite"); } diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index ad8b2fc670..33dc2bf511 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -120,7 +120,7 @@ static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc) { mc->desc = "Altera 10M50 GHRD Nios II design"; mc->init = nios2_10m50_ghrd_init; - mc->is_default = 1; + mc->is_default = true; } DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init); diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index ad5371250f..d08ce61811 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -176,7 +176,7 @@ static void openrisc_sim_machine_init(MachineClass *mc) mc->desc = "or1k simulation"; mc->init = openrisc_sim_init; mc->max_cpus = 2; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); } diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 66e434bba3..440c406eb4 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -435,7 +435,7 @@ static void heathrow_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_IDE; mc->max_cpus = MAX_CPUS; #ifndef TARGET_PPC64 - mc->is_default = 1; + mc->is_default = true; #endif /* TOFIX "cad" when Mac floppy is implemented */ mc->default_boot_order = "cd"; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c03ce6afb9..cc10798be4 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4560,7 +4560,7 @@ static const TypeInfo spapr_machine_info = { static void spapr_machine_latest_class_options(MachineClass *mc) { mc->alias = "pseries"; - mc->is_default = 1; + mc->is_default = true; } #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 6e5723a171..5053fe4590 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -451,7 +451,7 @@ static void spike_machine_init(MachineClass *mc) mc->desc = "RISC-V Spike Board"; mc->init = spike_board_init; mc->max_cpus = 1; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = SPIKE_V1_10_0_CPU; } diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 0817874b48..9c1ecd423c 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -179,7 +179,7 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp) /* if not Linux load the address of the (short) IPL PSW */ ipl_psw = rom_ptr(4, 4); if (ipl_psw) { - pentry = be32_to_cpu(*ipl_psw) & 0x7fffffffUL; + pentry = be32_to_cpu(*ipl_psw) & PSW_MASK_SHORT_ADDR; } else { error_setg(&err, "Could not get IPL PSW"); goto error; diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index a89cf4c129..895498cca6 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -630,7 +630,7 @@ bool css_migration_enabled(void) mc->desc = "VirtIO-ccw based S390 machine v" verstr; \ if (latest) { \ mc->alias = "s390-ccw-virtio"; \ - mc->is_default = 1; \ + mc->is_default = true; \ } \ } \ static void ccw_machine_##suffix##_instance_init(Object *obj) \ diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index 2fc2915428..68b14ee5e7 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -82,7 +82,7 @@ static void shix_machine_init(MachineClass *mc) { mc->desc = "shix card"; mc->init = shix_init; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = TYPE_SH7750R_CPU; } diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index f5bf95fc9f..36ee1a0a3d 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -1402,7 +1402,7 @@ static void ss5_class_init(ObjectClass *oc, void *data) mc->desc = "Sun4m platform, SPARCstation 5"; mc->init = ss5_init; mc->block_default_type = IF_SCSI; - mc->is_default = 1; + mc->is_default = true; mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index b7ac42f7a5..d33e84f831 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -816,7 +816,7 @@ static void sun4u_class_init(ObjectClass *oc, void *data) mc->init = sun4u_init; mc->block_default_type = IF_IDE; mc->max_cpus = 1; /* XXX for now */ - mc->is_default = 1; + mc->is_default = true; mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); mc->ignore_boot_device_suffixes = true; diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c index 20c9ccb3ce..8ec2b5bddd 100644 --- a/hw/tricore/tricore_testboard.c +++ b/hw/tricore/tricore_testboard.c @@ -105,7 +105,6 @@ static void ttb_machine_init(MachineClass *mc) { mc->desc = "a minimal TriCore board"; mc->init = tricoreboard_init; - mc->is_default = 0; mc->default_cpu_type = TRICORE_CPU_TYPE_NAME("tc1796"); } diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index 7e933de228..7f9c0238fe 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -140,7 +140,7 @@ static void puv3_machine_init(MachineClass *mc) { mc->desc = "PKUnity Version-3 based on UniCore32"; mc->init = puv3_init; - mc->is_default = 1; + mc->is_default = true; mc->default_cpu_type = UNICORE32_CPU_TYPE_NAME("UniCore-II"); } diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index b22fb258be..5b7991cffe 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -115,22 +115,6 @@ static const TypeInfo ehci_platform_type_info = { .class_init = ehci_platform_class_init, }; -static void ehci_xlnx_class_init(ObjectClass *oc, void *data) -{ - SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); - DeviceClass *dc = DEVICE_CLASS(oc); - - set_bit(DEVICE_CATEGORY_USB, dc->categories); - sec->capsbase = 0x100; - sec->opregbase = 0x140; -} - -static const TypeInfo ehci_xlnx_type_info = { - .name = "xlnx,ps7-usb", - .parent = TYPE_SYS_BUS_EHCI, - .class_init = ehci_xlnx_class_init, -}; - static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -267,7 +251,6 @@ static void ehci_sysbus_register_types(void) { type_register_static(&ehci_type_info); type_register_static(&ehci_platform_type_info); - type_register_static(&ehci_xlnx_type_info); type_register_static(&ehci_exynos4210_type_info); type_register_static(&ehci_tegra2_type_info); type_register_static(&ehci_ppc4xx_type_info); diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c index 919e66162a..18237b34ea 100644 --- a/hw/xen/xen-bus.c +++ b/hw/xen/xen-bus.c @@ -1089,8 +1089,26 @@ static void xen_device_event(void *opaque) } } +void xen_device_set_event_channel_context(XenDevice *xendev, + XenEventChannel *channel, + AioContext *ctx, + Error **errp) +{ + if (!channel) { + error_setg(errp, "bad channel"); + return; + } + + if (channel->ctx) + aio_set_fd_handler(channel->ctx, xenevtchn_fd(channel->xeh), true, + NULL, NULL, NULL, NULL); + + channel->ctx = ctx; + aio_set_fd_handler(channel->ctx, xenevtchn_fd(channel->xeh), true, + xen_device_event, NULL, xen_device_poll, channel); +} + XenEventChannel *xen_device_bind_event_channel(XenDevice *xendev, - AioContext *ctx, unsigned int port, XenEventHandler handler, void *opaque, Error **errp) @@ -1116,9 +1134,10 @@ XenEventChannel *xen_device_bind_event_channel(XenDevice *xendev, channel->handler = handler; channel->opaque = opaque; - channel->ctx = ctx; - aio_set_fd_handler(channel->ctx, xenevtchn_fd(channel->xeh), true, - xen_device_event, NULL, xen_device_poll, channel); + /* Only reason for failure is a NULL channel */ + xen_device_set_event_channel_context(xendev, channel, + qemu_get_aio_context(), + &error_abort); QLIST_INSERT_HEAD(&xendev->event_channels, channel, list); diff --git a/hw/xen/xen_pt_load_rom.c b/hw/xen/xen_pt_load_rom.c index 307a5c93e2..a50a80837e 100644 --- a/hw/xen/xen_pt_load_rom.c +++ b/hw/xen/xen_pt_load_rom.c @@ -3,12 +3,8 @@ */ #include "qemu/osdep.h" #include "qapi/error.h" -#include "hw/i386/pc.h" #include "qemu/error-report.h" -#include "ui/console.h" #include "hw/loader.h" -#include "monitor/monitor.h" -#include "qemu/range.h" #include "hw/pci/pci.h" #include "xen_pt.h" |