summaryrefslogtreecommitdiffstats
path: root/include/hw
diff options
context:
space:
mode:
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/pci-host/spapr.h22
-rw-r--r--include/hw/ppc/mac_dbdma.h5
-rw-r--r--include/hw/ppc/ppc.h2
-rw-r--r--include/hw/ppc/spapr.h22
-rw-r--r--include/hw/ppc/xics.h2
5 files changed, 45 insertions, 8 deletions
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 970b4a9e4a..0934518bbd 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -34,7 +34,21 @@
#define SPAPR_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
-typedef struct sPAPRPHBState {
+#define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE)
+#define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
+
+typedef struct sPAPRPHBClass sPAPRPHBClass;
+typedef struct sPAPRPHBState sPAPRPHBState;
+
+struct sPAPRPHBClass {
+ PCIHostBridgeClass parent_class;
+
+ void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
+};
+
+struct sPAPRPHBState {
PCIHostState parent_obj;
int32_t index;
@@ -46,10 +60,8 @@ typedef struct sPAPRPHBState {
MemoryRegion memwindow, iowindow;
uint32_t dma_liobn;
- uint64_t dma_window_start;
- uint64_t dma_window_size;
- sPAPRTCETable *tcet;
AddressSpace iommu_as;
+ MemoryRegion iommu_root;
struct spapr_pci_lsi {
uint32_t irq;
@@ -62,7 +74,7 @@ typedef struct sPAPRPHBState {
} msi_table[SPAPR_MSIX_MAX_DEVS];
QLIST_ENTRY(sPAPRPHBState) list;
-} sPAPRPHBState;
+};
#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h
index 90efd277e4..d7db06c031 100644
--- a/include/hw/ppc/mac_dbdma.h
+++ b/include/hw/ppc/mac_dbdma.h
@@ -42,6 +42,11 @@ struct DBDMA_io {
/* unaligned last sector of a request */
uint8_t remainder[0x200];
int remainder_len;
+ QEMUIOVector iov;
+ bool finish_remain_read;
+ hwaddr finish_addr;
+ hwaddr finish_len;
+ int requests;
};
/*
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index d71bd07497..7e16e2e06c 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -92,6 +92,8 @@ enum {
#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
+/* OpenBIOS has FW_CFG_PPC_NVRAM_ADDR as +0x08 */
+#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
#define PPC_SERIAL_MM_BAUDBASE 399193
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 5fdac1e009..08c301f38d 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -29,6 +29,7 @@ typedef struct sPAPREnvironment {
target_ulong entry_point;
uint32_t next_irq;
uint64_t rtc_offset;
+ struct PPCTimebase tb;
bool has_graphics;
uint32_t epow_irq;
@@ -163,6 +164,11 @@ typedef struct sPAPREnvironment {
#define H_SET_MODE_ENDIAN_BIG 0
#define H_SET_MODE_ENDIAN_LITTLE 1
+/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
+#define H_SET_MODE_ADDR_TRANS_NONE 0
+#define H_SET_MODE_ADDR_TRANS_0001_8000 2
+#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
+
/* VASI States */
#define H_VASI_INVALID 0
#define H_VASI_ENABLED 1
@@ -302,10 +308,16 @@ typedef struct sPAPREnvironment {
#define KVMPPC_HCALL_BASE 0xf000
#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
-#define KVMPPC_HCALL_MAX KVMPPC_H_LOGICAL_MEMOP
+/* Client Architecture support */
+#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
+#define KVMPPC_HCALL_MAX KVMPPC_H_CAS
extern sPAPREnvironment *spapr;
+typedef struct sPAPRDeviceTreeUpdateHeader {
+ uint32_t version_id;
+} sPAPRDeviceTreeUpdateHeader;
+
/*#define DEBUG_SPAPR_HCALLS*/
#ifdef DEBUG_SPAPR_HCALLS
@@ -390,8 +402,9 @@ typedef struct sPAPRTCETable sPAPRTCETable;
struct sPAPRTCETable {
DeviceState parent;
uint32_t liobn;
- uint32_t window_size;
uint32_t nb_table;
+ uint64_t bus_offset;
+ uint32_t page_shift;
uint64_t *table;
bool bypass;
int fd;
@@ -401,8 +414,11 @@ struct sPAPRTCETable {
void spapr_events_init(sPAPREnvironment *spapr);
void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
+int spapr_h_cas_compose_response(target_ulong addr, target_ulong size);
sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
- size_t window_size);
+ uint64_t bus_offset,
+ uint32_t page_shift,
+ uint32_t nb_table);
MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass);
int spapr_dma_dt(void *fdt, int node_off, const char *propname,
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 0d7673de94..85e4c8a3dd 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -152,6 +152,8 @@ struct ICSIRQState {
uint8_t status;
};
+#define XICS_IRQS 1024
+
qemu_irq xics_get_qirq(XICSState *icp, int irq);
void xics_set_irq_type(XICSState *icp, int irq, bool lsi);