diff options
Diffstat (limited to 'target-arm/op_helper.c')
| -rw-r--r-- | target-arm/op_helper.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 3f5b9ab596..7fa32c4707 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -81,9 +81,10 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - int ret; + bool ret; + uint32_t fsr = 0; - ret = arm_tlb_fill(cs, addr, is_write, mmu_idx); + ret = arm_tlb_fill(cs, addr, is_write, mmu_idx, &fsr); if (unlikely(ret)) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -96,7 +97,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, } /* AArch64 syndrome does not have an LPAE bit */ - syn = ret & ~(1 << 9); + syn = fsr & ~(1 << 9); /* For insn and data aborts we assume there is no instruction syndrome * information; this is always true for exceptions reported to EL1. @@ -107,13 +108,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, } else { syn = syn_data_abort(same_el, 0, 0, 0, is_write == 1, syn); if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) { - ret |= (1 << 11); + fsr |= (1 << 11); } exc = EXCP_DATA_ABORT; } env->exception.vaddress = addr; - env->exception.fsr = ret; + env->exception.fsr = fsr; raise_exception(env, exc, syn, exception_target_el(env)); } } @@ -421,7 +422,7 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome) /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is * a bug in the access function. */ - assert(!arm_is_secure(env) && !arm_current_el(env) == 3); + assert(!arm_is_secure(env) && arm_current_el(env) != 3); target_el = 2; break; case CP_ACCESS_TRAP_EL3: |