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-rw-r--r--target-openrisc/cpu.c34
-rw-r--r--target-openrisc/cpu.h10
-rw-r--r--target-openrisc/exception.c6
-rw-r--r--target-openrisc/interrupt.c14
-rw-r--r--target-openrisc/interrupt_helper.c2
-rw-r--r--target-openrisc/mmu.c17
-rw-r--r--target-openrisc/mmu_helper.c8
-rw-r--r--target-openrisc/sys_helper.c6
-rw-r--r--target-openrisc/translate.c5
9 files changed, 51 insertions, 51 deletions
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 813794300b..08e724c126 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -27,6 +27,12 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool openrisc_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & (CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_TIMER);
+}
+
/* CPUClass::reset() */
static void openrisc_cpu_reset(CPUState *s)
{
@@ -35,14 +41,18 @@ static void openrisc_cpu_reset(CPUState *s)
occ->parent_reset(s);
- memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
+#ifndef CONFIG_USER_ONLY
+ memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb));
+#else
+ memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
+#endif
- tlb_flush(&cpu->env, 1);
+ tlb_flush(s, 1);
/*tb_flush(&cpu->env); FIXME: Do we need it? */
cpu->env.pc = 0x100;
cpu->env.sr = SR_FO | SR_SM;
- cpu->env.exception_index = -1;
+ s->exception_index = -1;
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
@@ -153,12 +163,15 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = openrisc_cpu_reset;
cc->class_by_name = openrisc_cpu_class_by_name;
+ cc->has_work = openrisc_cpu_has_work;
cc->do_interrupt = openrisc_cpu_do_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
#endif
@@ -201,18 +214,7 @@ static void openrisc_cpu_register_types(void)
OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
{
- OpenRISCCPU *cpu;
- ObjectClass *oc;
-
- oc = openrisc_cpu_class_by_name(cpu_model);
- if (oc == NULL) {
- return NULL;
- }
- cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
-
- object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
-
- return cpu;
+ return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
}
/* Sort alphabetically by type name, except for "any". */
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 51d6afd153..4512f459bf 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -304,6 +304,7 @@ typedef struct CPUOpenRISCState {
CPU_COMMON
+ /* Fields from here on are preserved across CPU reset. */
#ifndef CONFIG_USER_ONLY
CPUOpenRISCTLBContext * tlb;
@@ -353,15 +354,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
-int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
- target_ulong address,
+int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
int rw, int mmu_idx);
int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_list cpu_openrisc_list
#define cpu_exec cpu_openrisc_exec
#define cpu_gen_code cpu_openrisc_gen_code
-#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
#define cpu_signal_handler cpu_openrisc_signal_handler
#ifndef CONFIG_USER_ONLY
@@ -419,11 +418,6 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env)
}
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & (CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_TIMER);
-}
#include "exec/exec-all.h"
diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c
index 58e53c6c98..74652a58f6 100644
--- a/target-openrisc/exception.c
+++ b/target-openrisc/exception.c
@@ -22,6 +22,8 @@
void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp)
{
- cpu->env.exception_index = excp;
- cpu_loop_exit(&cpu->env);
+ CPUState *cs = CPU(cpu);
+
+ cs->exception_index = excp;
+ cpu_loop_exit(cs);
}
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 2153e7ea7e..3de567eee8 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -27,9 +27,9 @@
void openrisc_cpu_do_interrupt(CPUState *cs)
{
+#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
-#ifndef CONFIG_USER_ONLY
env->epcr = env->pc;
if (env->flags & D_FLAG) {
@@ -37,13 +37,13 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->sr |= SR_DSX;
env->epcr -= 4;
}
- if (env->exception_index == EXCP_SYSCALL) {
+ if (cs->exception_index == EXCP_SYSCALL) {
env->epcr += 4;
}
/* For machine-state changed between user-mode and supervisor mode,
we need flush TLB when we enter&exit EXCP. */
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
env->esr = env->sr;
env->sr &= ~SR_DME;
@@ -54,12 +54,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
- if (env->exception_index > 0 && env->exception_index < EXCP_NR) {
- env->pc = (env->exception_index << 8);
+ if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
+ env->pc = (cs->exception_index << 8);
} else {
- cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+ cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}
#endif
- env->exception_index = -1;
+ cs->exception_index = -1;
}
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 844648f780..819405701d 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
}
if (need_flush_tlb) {
- tlb_flush(&cpu->env, 1);
+ tlb_flush(cs, 1);
}
#endif
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index dd487bd0d1..750a93636b 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -139,6 +139,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
target_ulong address,
int rw, int tlb_error)
{
+ CPUState *cs = CPU(cpu);
int exception = 0;
switch (tlb_error) {
@@ -169,24 +170,24 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
#endif
}
- cpu->env.exception_index = exception;
+ cs->exception_index = exception;
cpu->env.eear = address;
}
#ifndef CONFIG_USER_ONLY
-int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
- target_ulong address, int rw, int mmu_idx)
+int openrisc_cpu_handle_mmu_fault(CPUState *cs,
+ vaddr address, int rw, int mmu_idx)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
int ret = 0;
hwaddr physical = 0;
int prot = 0;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,
address, rw);
if (ret == TLBRET_MATCH) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
@@ -198,11 +199,11 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
return ret;
}
#else
-int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
- target_ulong address, int rw, int mmu_idx)
+int openrisc_cpu_handle_mmu_fault(CPUState *cs,
+ vaddr address, int rw, int mmu_idx)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
int ret = 0;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
ret = 1;
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index e46b092984..fb457c76af 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -36,20 +36,20 @@
#define SHIFT 3
#include "exec/softmmu_template.h"
-void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
int ret;
- ret = cpu_openrisc_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault. */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
/* Raise Exception. */
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
#endif
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index be06c4565b..fedcbed4f7 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 17): /* SR */
if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
(rb & (SR_IME | SR_DME | SR_SM))) {
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
}
env->sr = rb;
env->sr |= SR_FO; /* FO is const equal to 1 */
@@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb & 1)) {
- tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
}
env->tlb->dtlb[0][idx].mr = rb;
break;
@@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
if (!(rb & 1)) {
- tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
}
env->tlb->itlb[0][idx].mr = rb;
break;
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 776cb6eece..852b5e6107 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1619,10 +1619,11 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc)
{
+ CPUState *cs = CPU(cpu);
CPUBreakpoint *bp;
- if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) {
- QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_DEBUG);
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-04-27 07:36:08 +0200