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-rw-r--r--target-sparc/cpu.c3
-rw-r--r--target-sparc/cpu.h5
2 files changed, 6 insertions, 2 deletions
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index e4089f2074..800a25aa57 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -117,8 +117,7 @@ static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model)
return -1;
}
- env->def = g_new0(sparc_def_t, 1);
- memcpy(env->def, def, sizeof(*def));
+ env->def = g_memdup(def, sizeof(*def));
featurestr = strtok(NULL, ",");
sparc_cpu_parse_features(CPU(cpu), featurestr, &err);
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index a3d64a4e52..646a103513 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -102,6 +102,11 @@
#define CC_DST (env->cc_dst)
#define CC_OP (env->cc_op)
+/* Even though lazy evaluation of CPU condition codes tends to be less
+ * important on RISC systems where condition codes are only updated
+ * when explicitly requested, SPARC uses it to update 32-bit and 64-bit
+ * condition codes.
+ */
enum {
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
CC_OP_FLAGS, /* all cc are back in status register */