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-rw-r--r--target/mips/cpu.c5
-rw-r--r--target/mips/cpu.h1
2 files changed, 6 insertions, 0 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 76d50b00b4..687e2680dd 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -310,3 +310,8 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
return MIPS_CPU(cpu);
}
+
+bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
+{
+ return (env->cpu_model->insn_flags & isa_mask) != 0;
+}
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9c65c87bf9..e8bca75f23 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1287,6 +1287,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
bool cpu_type_supports_cps_smp(const char *cpu_type);
+bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
void cpu_set_exception_base(int vp_index, target_ulong address);