diff options
Diffstat (limited to 'tcg/mips/tcg-target.c')
| -rw-r--r-- | tcg/mips/tcg-target.c | 137 |
1 files changed, 135 insertions, 2 deletions
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 8fcb5c99c3..ec687ad6f6 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -274,6 +274,8 @@ enum { OPC_BEQ = 0x04 << 26, OPC_BNE = 0x05 << 26, OPC_ADDIU = 0x09 << 26, + OPC_SLTI = 0x0A << 26, + OPC_SLTIU = 0x0B << 26, OPC_ANDI = 0x0C << 26, OPC_ORI = 0x0D << 26, OPC_XORI = 0x0E << 26, @@ -583,6 +585,128 @@ static void tcg_out_brcond2(TCGContext *s, int cond, int arg1, reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr); } +static void tcg_out_setcond(TCGContext *s, int cond, int ret, + int arg1, int arg2) +{ + switch (cond) { + case TCG_COND_EQ: + if (arg1 == 0) { + tcg_out_opc_imm(s, OPC_SLTIU, ret, arg2, 1); + } else if (arg2 == 0) { + tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); + } else { + tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); + } + break; + case TCG_COND_NE: + if (arg1 == 0) { + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg2); + } else if (arg2 == 0) { + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); + } else { + tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); + } + break; + case TCG_COND_LT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); + break; + case TCG_COND_LTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); + break; + case TCG_COND_GE: + tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_GEU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_LE: + tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_LEU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_GT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); + break; + case TCG_COND_GTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); + break; + default: + tcg_abort(); + break; + } +} + +/* XXX: we implement it at the target level to avoid having to + handle cross basic blocks temporaries */ +static void tcg_out_setcond2(TCGContext *s, int cond, int ret, + int arg1, int arg2, int arg3, int arg4) +{ + switch (cond) { + case TCG_COND_EQ: + tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_AT, arg2, arg4); + tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, arg1, arg3); + tcg_out_opc_reg(s, OPC_AND, ret, TCG_REG_AT, TCG_REG_T0); + return; + case TCG_COND_NE: + tcg_out_setcond(s, TCG_COND_NE, TCG_REG_AT, arg2, arg4); + tcg_out_setcond(s, TCG_COND_NE, TCG_REG_T0, arg1, arg3); + tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_AT, TCG_REG_T0); + return; + case TCG_COND_LT: + case TCG_COND_LE: + tcg_out_setcond(s, TCG_COND_LT, TCG_REG_AT, arg2, arg4); + break; + case TCG_COND_GT: + case TCG_COND_GE: + tcg_out_setcond(s, TCG_COND_GT, TCG_REG_AT, arg2, arg4); + break; + case TCG_COND_LTU: + case TCG_COND_LEU: + tcg_out_setcond(s, TCG_COND_LTU, TCG_REG_AT, arg2, arg4); + break; + case TCG_COND_GTU: + case TCG_COND_GEU: + tcg_out_setcond(s, TCG_COND_GTU, TCG_REG_AT, arg2, arg4); + break; + default: + tcg_abort(); + break; + } + + tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, arg2, arg4); + + switch(cond) { + case TCG_COND_LT: + case TCG_COND_LTU: + tcg_out_setcond(s, TCG_COND_LTU, ret, arg1, arg3); + break; + case TCG_COND_LE: + case TCG_COND_LEU: + tcg_out_setcond(s, TCG_COND_LEU, ret, arg1, arg3); + break; + case TCG_COND_GT: + case TCG_COND_GTU: + tcg_out_setcond(s, TCG_COND_GTU, ret, arg1, arg3); + break; + case TCG_COND_GE: + case TCG_COND_GEU: + tcg_out_setcond(s, TCG_COND_GEU, ret, arg1, arg3); + break; + default: + tcg_abort(); + } + + tcg_out_opc_reg(s, OPC_AND, ret, ret, TCG_REG_T0); + tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_AT); +} + #if defined(CONFIG_SOFTMMU) #include "../../softmmu_defs.h" @@ -731,9 +855,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, /* label1: fast path */ reloc_pc16(label1_ptr, (tcg_target_long) s->code_ptr); - tcg_out_opc_imm(s, OPC_LW, TCG_REG_V0, TCG_REG_A0, + tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0, offsetof(CPUState, tlb_table[mem_index][0].addend) + addr_meml); - tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_V0, addr_regl); + tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_A0, addr_regl); addr_reg1 = TCG_REG_V0; #endif @@ -1155,6 +1279,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]); break; + case INDEX_op_setcond_i32: + tcg_out_setcond(s, args[3], args[0], args[1], args[2]); + break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args[5], args[0], args[1], args[2], args[3], args[4]); + break; + case INDEX_op_qemu_ld8u: tcg_out_qemu_ld(s, args, 0); break; @@ -1228,6 +1359,8 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_sar_i32, { "r", "rZ", "riZ" } }, { INDEX_op_brcond_i32, { "rZ", "rZ" } }, + { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, + { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } }, { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } }, |