bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

summary refs log tree commit diff stats

path: root/tcg

diff options

Diffstat (limited to 'tcg')

0 files changed, 0 insertions, 0 deletions

7773e45d87109a17'>riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-102-0/+17 * riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel2020-02-101-4/+22 * hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic2020-01-291-2/+2 * Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2020-01-274-4/+4 |\ | * qdev: set properties with device_class_set_props()Marc-André Lureau2020-01-244-4/+4 * | riscv/sifive_u: fix a memory leak in soc_realize()Pan Nengyuan2020-01-161-0/+1 |/ * chardev: Use QEMUChrEvent enum in IOEventHandler typedefPhilippe Mathieu-Daudé2020-01-082-2/+2 * hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-255-9/+12 * RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt2019-11-251-1/+4 * riscv/virt: Increase flash sizeAlistair Francis2019-11-141-1/+1 * riscv/boot: Fix possible memory leakAlistair Francis2019-10-281-7/+4

* riscv/virt: Jump to pflash if specifiedAlistair Francis2019-10-281-1/+10 * riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2019-10-282-0/+87 * riscv/virt: Manually define the machineAlistair Francis2019-10-281-6/+24 * riscv/sifive_u: Add the start-in-flash propertyAlistair Francis2019-10-281-1/+29 * riscv/sifive_u: Manually define the machineAlistair Francis2019-10-281-13/+31 * riscv/sifive_u: Add QSPI memory regionAlistair Francis2019-10-281-0/+8 * riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis2019-10-281-0/+16 * riscv: sifive_u: Add ethernet0 to the aliases nodeBin Meng2019-10-281-1/+4 * riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-283-6/+0

* riscv: sifive_u: Update model and compatible strings in device treeBin Meng2019-09-171-2/+3 * riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-171-23/+1

* riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-172-4/+21 * riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-171-0/+9 * riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2019-09-172-0/+192 * riscv: sifive_u: Change UART node name in device treeBin Meng2019-09-171-1/+1 * riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-171-2/+2 * riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-171-3/+4 * riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-171-1/+23 * riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-171-0/+23 * riscv: sifive: Implement PRCI model for FU540Bin Meng2019-09-172-0/+170 * riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng2019-09-171-3/+4 * riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-17