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* block/create: Mark blockdev-create stableKevin Wolf2018-05-3015-111/+111
| | | | | | | | | We're ready to declare the blockdev-create job stable. This renames the corresponding QMP command from x-blockdev-create to blockdev-create. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* qemu-iotests: Rewrite 213 for blockdev-create jobKevin Wolf2018-05-303-413/+319Star
| | | | | | | | | | | This rewrites the test case 213 to work with the new x-blockdev-create job rather than the old synchronous version of the command. All of the test cases stay the same as before, but in order to be able to implement proper job handling, the test case is rewritten in Python. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
* qemu-iotests: Rewrite 212 for blockdev-create jobKevin Wolf2018-05-303-381/+295Star
| | | | | | | | | | | This rewrites the test case 212 to work with the new x-blockdev-create job rather than the old synchronous version of the command. All of the test cases stay the same as before, but in order to be able to implement proper job handling, the test case is rewritten in Python. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
* qemu-iotests: Rewrite 211 for blockdev-create jobKevin Wolf2018-05-303-287/+229Star
| | | | | | | | | | | This rewrites the test case 211 to work with the new x-blockdev-create job rather than the old synchronous version of the command. All of the test cases stay the same as before, but in order to be able to implement proper job handling, the test case is rewritten in Python. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
* qemu-iotests: Rewrite 210 for blockdev-create jobKevin Wolf2018-05-304-290/+314
| | | | | | | | | | | | This rewrites the test case 210 to work with the new x-blockdev-create job rather than the old synchronous version of the command. All of the test cases stay the same as before, but in order to be able to implement proper job handling, the test case is rewritten in Python. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* qemu-iotests: Rewrite 207 for blockdev-create jobKevin Wolf2018-05-303-296/+257Star
| | | | | | | | | | | | | This rewrites the test case 207 to work with the new x-blockdev-create job rather than the old synchronous version of the command. Most of the test cases stay the same as before (the exception being some improved 'size' options that allow distinguishing which command created the image), but in order to be able to implement proper job handling, the test case is rewritten in Python. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
* qemu-iotests: Rewrite 206 for blockdev-create jobKevin Wolf2018-05-303-521/+414Star
| | | | | | | | | | | This rewrites the test case 206 to work with the new x-blockdev-create job rather than the old synchronous version of the command. All of the test cases stay the same as before, but in order to be able to implement proper job handling, the test case is rewritten in Python. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
* qemu-iotests: iotests.py helper for non-file protocolsKevin Wolf2018-05-301-0/+17
| | | | | | | | | This adds two helper functions that are useful for test cases that make use of a non-file protocol (specifically ssh). Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* qemu-iotests: Add VM.run_job()Kevin Wolf2018-05-301-0/+19
| | | | | | | | | | Add an iotests.py function that runs a job and only returns when it is destroyed. An error is logged when the job failed and job-finalize and job-dismiss commands are issued if necessary. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* qemu-iotests: Add iotests.img_info_log()Kevin Wolf2018-05-301-0/+18
| | | | | | | | | | This adds a filter function to postprocess 'qemu-img info' input (similar to what _img_info does), and an img_info_log() function that calls 'qemu-img info' and logs the filtered output. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* qemu-iotests: Add VM.qmp_log()Kevin Wolf2018-05-301-0/+11
| | | | | | | | | This adds a helper function that logs both the QMP request and the received response before returning it. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
* qemu-iotests: Add VM.get_qmp_events_filtered()Kevin Wolf2018-05-301-0/+5
| | | | | | | | | This adds a helper function that returns a list of QMP events that are already filtered through filter_qmp_event(). Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* block/create: Make x-blockdev-create a jobKevin Wolf2018-05-304-33/+66
| | | | | | | | | | | | | | | | | | This changes the x-blockdev-create QMP command so that it doesn't block the monitor and the main loop any more, but starts a background job that performs the image creation. The basic job as implemented here is all that is necessary to make image creation asynchronous and to provide a QMP interface that can be marked stable, but it still lacks a few features that jobs usually provide: The job will ignore pause commands and it doesn't publish more than very basic progress yet (total-progress is 1 and current-progress advances from 0 to 1 when the driver callbacks returns). These features can be added later without breaking compatibility. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* job: Add error message for failing jobsKevin Wolf2018-05-3010-17/+29
| | | | | | | | | | | | | | | | | So far we relied on job->ret and strerror() to produce an error message for failed jobs. Not surprisingly, this tends to result in completely useless messages. This adds a Job.error field that can contain an error string for a failing job, and a parameter to job_completed() that sets the field. As a default, if NULL is passed, we continue to use strerror(job->ret). All existing callers are changed to pass NULL. They can be improved in separate patches. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* vhdx: Fix vhdx_co_create() return valueKevin Wolf2018-05-291-1/+1
| | | | | | | | | .bdrv_co_create() is supposed to return 0 on success, but vhdx could return a positive value instead. Fix this. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* vdi: Fix vdi_co_do_create() return valueKevin Wolf2018-05-291-0/+1
| | | | | | | | | .bdrv_co_create() is supposed to return 0 on success, but vdi could return a positive value instead. Fix this. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com>
* qcow2: Fix Coverity warning when calculating the refcount cache sizeAlberto Garcia2018-05-291-3/+2Star
| | | | | | | | | | | | | | | | | | | | | MIN_REFCOUNT_CACHE_SIZE is 4 and the cluster size is guaranteed to be at most 2MB, so the minimum refcount cache size (in bytes) is always going to fit in a 32-bit integer. Coverity doesn't know that, and since we're storing the result in a uint64_t (*refcount_cache_size) it thinks that we need the 64 bits and that we probably want to do a 64-bit multiplication to prevent the result from being truncated. This is a false positive in this case, but it's a fair warning. We could do a 64-bit multiplication to get rid of it, but since we know that a 32-bit variable is enough to store this value let's simply reuse min_refcount_cache, make it a normal int and stop doing casts. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2018-05-2910-569/+598
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream' into staging Tag edgar/xilinx-next-2018-05-29-v1.for-upstream # gpg: Signature made Tue 29 May 2018 09:58:30 BST # gpg: using RSA key 29C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream: (38 commits) target-microblaze: Consolidate MMU enabled checks target-microblaze: cpu_mmu_index: Fixup indentation target-microblaze: Use tcg_gen_movcond in eval_cond_jmp target-microblaze: Convert env_btarget to i64 target-microblaze: Remove argument b in eval_cc() target-microblaze: Use table based condition-codes conversion target-microblaze: mmu: Cleanup debug log messages target-microblaze: Simplify address computation using tcg_gen_addi_i32() target-microblaze: Allow address sizes between 32 and 64 bits target-microblaze: Add support for extended access to TLBLO target-microblaze: dec_msr: Plug a temp leak target-microblaze: mmu: Add a configurable output address mask target-microblaze: mmu: Prepare for 64-bit addresses target-microblaze: mmu: Remove unused register state target-microblaze: mmu: Add R_TBLX_MISS macros target-microblaze: Implement MFSE EAR target-microblaze: Add Extended Addressing target-microblaze: Setup for 64bit addressing target-microblaze: Make special registers 64-bit target-microblaze: dec_msr: Fix MTS to FSR ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-microblaze: Consolidate MMU enabled checksEdgar E. Iglesias2018-05-292-4/+6
| | | | | | | | | | | | | | | | | | | | Consolidate MMU enabled checks to cpu_mmu_index(). No functional changes. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: cpu_mmu_index: Fixup indentationEdgar E. Iglesias2018-05-291-7/+9
| | | | | | | | | | | | | | | | | | | | Fixup the indentation of cpu_mmu_index in preparation for future edits. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Use tcg_gen_movcond in eval_cond_jmpEdgar E. Iglesias2018-05-291-6/+10
| | | | | | | | | | | | | | | | | | | | Cleanup eval_cond_jmp to use tcg_gen_movcond_i64(). No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Convert env_btarget to i64Edgar E. Iglesias2018-05-293-15/+25
| | | | | | | | | | | | | | | | | | Convert env_btarget to i64. No functional change. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Remove argument b in eval_cc()Edgar E. Iglesias2018-05-291-3/+3
| | | | | | | | | | | | | | | | Remove argument b in eval_cc() as it is always set to zero. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Use table based condition-codes conversionEdgar E. Iglesias2018-05-291-21/+20Star
| | | | | | | | | | | | | | | | | | Use a table based conversion to map condition-codes between MicroBlaze ISA encoding and TCG. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: mmu: Cleanup debug log messagesEdgar E. Iglesias2018-05-291-20/+19Star
| | | | | | | | | | | | | | | | | | | | | | | | Cleanup debug log messages: * Avoid long 80+ character lines. * Remove D() macro and use qemu_log_mask. * Remove logs that are not very useful Suggested-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Simplify address computation using tcg_gen_addi_i32()Edgar E. Iglesias2018-05-291-6/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Allow address sizes between 32 and 64 bitsEdgar E. Iglesias2018-05-291-3/+2Star
| | | | | | | | | | | | | | | | Allow address sizes between 32 and 64 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Add support for extended access to TLBLOEdgar E. Iglesias2018-05-295-18/+35
| | | | | | | | | | | | | | Add support for extended access to TLBLO's upper 32 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: dec_msr: Plug a temp leakEdgar E. Iglesias2018-05-291-4/+9
| | | | | | | | | | | | | | | | Plug a temp leak. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: mmu: Add a configurable output address maskEdgar E. Iglesias2018-05-293-0/+3
| | | | | | | | | | | | | | | | | | Add a configurable output address mask, used to mimic the configurable physical address bit width. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: mmu: Prepare for 64-bit addressesEdgar E. Iglesias2018-05-292-10/+10
| | | | | | | | | | | | | | | | | | Prepare for 64-bit addresses. This makes no functional difference as the upper parts of the 64-bit addresses are not yet reachable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: mmu: Remove unused register stateEdgar E. Iglesias2018-05-292-3/+6
| | | | | | | | | | | | | | | | | | | | Add explicit handling for MMU_R_TLBX and log accesses to invalid MMU registers. We can now remove the state for all regs but PID, ZPR and TLBX (0 - 2). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: mmu: Add R_TBLX_MISS macrosEdgar E. Iglesias2018-05-292-2/+7
| | | | | | | | | | | | | | | | Add a R_TBLX_MISS MASK and SHIFT macros. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Implement MFSE EAREdgar E. Iglesias2018-05-291-1/+8
| | | | | | | | | | | | | | Implement MFSE EAR to enable access to the upper part of EAR. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Add Extended AddressingEdgar E. Iglesias2018-05-293-13/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Extended Addressing. Load/stores with EA enabled concatenate two 32bit registers to form an extended address. We don't allow users to enable address sizes larger than 32 bits quite yet though. Once the MMU support is in, we'll turn it on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Setup for 64bit addressingEdgar E. Iglesias2018-05-292-3/+4
| | | | | | | | | | | | | | | | | | Setup MicroBlaze builds for 64bit addressing. No functional change since the translator does not yet emit 64bit addresses. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Make special registers 64-bitEdgar E. Iglesias2018-05-296-60/+72
| | | | | | | | | | | | | | | | Extend special registers to 64-bits. This is in preparation for MFSE/MTSE, moves to and from extended special registers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: dec_msr: Fix MTS to FSREdgar E. Iglesias2018-05-291-3/+1Star
| | | | | | | | | | | | | | | | Fix moves to FSR. Not only bit 31 is accessible. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: dec_msr: Reuse more code when reg-decodingEdgar E. Iglesias2018-05-291-29/+9Star
| | | | | | | | | | | | | | | | | | | | Reuse more code when decoding register numbers. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: dec_msr: Use bool and extract32Edgar E. Iglesias2018-05-291-6/+9
| | | | | | | | | | | | | | | | | | | | | | Use bool and extract32 to represent the to, clr and clrset flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Break out trap_illegal()Edgar E. Iglesias2018-05-291-48/+27Star
| | | | | | | | | | | | | | | | | | | | Break out trap_illegal() to handle illegal operation traps. We now generally stop translation of the current insn if it's not valid. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Break out trap_userspace()Edgar E. Iglesias2018-05-291-49/+27Star
| | | | | | | | | | | | | | | | | | | | Break out trap_userspace() to avoid open coding it everywhere. For privileged insns, we now always stop translation of the current insn for cores without exceptions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Name special registers we supportEdgar E. Iglesias2018-05-291-2/+2
| | | | | | | | | | | | | | Name special registers we support. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Use TCGv for load/store addressesEdgar E. Iglesias2018-05-294-42/+53
| | | | | | | | | | | | | | | | | | | | | | Use TCGv for load/store addresses, allowing for future computation of 64-bit load/store address. No functional change. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Remove pointer indirection for ld/st addressesEdgar E. Iglesias2018-05-291-12/+12
| | | | | | | | | | | | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Make compute_ldst_addr always use a tempEdgar E. Iglesias2018-05-291-74/+37Star
| | | | | | | | | | | | | | | | | | | | | | | | Make compute_ldst_addr always use a temp. This simplifies the code a bit in preparation for adding support for 64bit addresses. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Bypass MMU with MMU_NOMMU_IDXEdgar E. Iglesias2018-05-291-1/+2
| | | | | | | | | | | | | | | | Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Conditionalize setting of PVR11_USE_MMUEdgar E. Iglesias2018-05-291-1/+2
| | | | | | | | | | | | | | | | | | | | Conditionalize setting of PVR11_USE_MMU on the use_mmu CPU property, otherwise we may incorrectly advertise an MMU via PVR when the core in fact has none. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Remove USE_MMU PVR checksEdgar E. Iglesias2018-05-291-11/+1Star
| | | | | | | | | | | | | | | | | | | | We already have a CPU property to control if a core has an MMU or not. Remove USE_MMU PVR checks in favor of looking at the property. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * target-microblaze: Tighten up TCGv_i32 vs TCGv type usageEdgar E. Iglesias2018-05-292-288/+295
| | | | | | | | | | | | | | | | | | | | | | | | Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when TCGv_i32 should be used. This is in preparation for adding 64bit addressing support. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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