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| * l2tpv3: fix RFC number typo in qemu-options.hxStefan Hajnoczi2020-03-031-2/+2
| * colo: Update Documentation for continuous replicationLukas Straub2020-03-032-68/+184
| * net/filter.c: Add Options to insert filters anywhere in the filter listLukas Straub2020-03-033-6/+119
| * tests/test-replication.c: Add test for for secondary node continuing replicationLukas Straub2020-03-031-0/+52
| * block/replication.c: Ignore requests after failoverLukas Straub2020-03-031-1/+34
| * hw: net: cadence_gem: Fix build errors in DB_PRINT()Bin Meng2020-03-031-5/+6
| * NetRxPkt: fix hash calculation of IPV6 TCPYuri Benditovich2020-03-032-2/+2
| * NetRxPkt: Introduce support for additional hash typesYuri Benditovich2020-03-033-1/+51
| * e1000e: Avoid hw_error if legacy mode usedYuri Benditovich2020-03-031-5/+8
| * dp8393x: Don't stop reception upon RBE interrupt assertionFinn Thain2020-03-031-13/+22
| * dp8393x: Don't reset Silicon Revision registerFinn Thain2020-03-031-1/+1
| * dp8393x: Always update RRA pointers and sequence numbersFinn Thain2020-03-031-5/+7
| * dp8393x: Clear descriptor in_use field to release packetFinn Thain2020-03-031-0/+10
| * dp8393x: Pad frames to word or long word boundaryFinn Thain2020-03-031-11/+28
| * dp8393x: Use long-word-aligned RRA pointers in 32-bit modeFinn Thain2020-03-031-2/+6
| * dp8393x: Don't clobber packet checksumFinn Thain2020-03-031-0/+1
| * dp8393x: Implement packet size limit and RBAE interruptFinn Thain2020-03-031-0/+9
| * dp8393x: Clear RRRA command register bit only when appropriateFinn Thain2020-03-031-4/+3Star
| * dp8393x: Update LLFA and CRDA registers from rx descriptorFinn Thain2020-03-031-4/+7
| * dp8393x: Have dp8393x_receive() return the packet sizeFinn Thain2020-03-031-4/+5
| * dp8393x: Clean up endianness hacksFinn Thain2020-03-031-11/+6Star
| * dp8393x: Always use 32-bit accessesFinn Thain2020-03-031-18/+29
| * dp8393x: Mask EOL bit from descriptor addressesFinn Thain2020-03-021-6/+11
* | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell2020-03-0316-141/+1240
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| * | hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-276-8/+16
| * | target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-273-4/+92
| * | riscv: virt: Allow PCI address 0Bin Meng2020-02-271-0/+1
| * | target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-272-0/+6
| * | target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-274-4/+15
| * | target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-276-0/+62
| * | target/riscv: Set htval and mtval2 on execptionsAlistair Francis2020-02-271-0/+10
| * | target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis2020-02-271-6/+18
| * | target/riscv: Implement second stage MMUAlistair Francis2020-02-272-19/+175
| * | target/riscv: Allow specifying MMU stageAlistair Francis2020-02-271-9/+28
| * | target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis2020-02-271-1/+15
| * | target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis2020-02-271-0/+13
| * | target/riscv: Disable guest FP support based on virtual statusAlistair Francis2020-02-271-0/+3
| * | target/riscv: Only set TB flags with FP status if enabledAlistair Francis2020-02-271-1/+4
| * | target/riscv: Remove the hret instructionAlistair Francis2020-02-272-6/+0Star
| * | target/riscv: Add hfence instructionsAlistair Francis2020-02-272-9/+54
| * | target/riscv: Add Hypervisor trap return supportAlistair Francis2020-02-271-10/+52
| * | target/riscv: Add hypvervisor trap supportAlistair Francis2020-02-271-10/+59
| * | target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis2020-02-271-2/+3
| * | target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis2020-02-271-0/+5
| * | target/riscv: Add support for virtual interrupt settingAlistair Francis2020-02-271-5/+28
| * | target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis2020-02-271-1/+12
| * | target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis2020-02-271-4/+20
| * | target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis2020-02-271-0/+3
| * | target/riscv: Add virtual register swapping functionAlistair Francis2020-02-273-0/+79
| * | target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis2020-02-271-0/+27
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