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| * apic: save apic_delivered flagPavel Dovgalyuk2017-01-272-0/+35
| | | | | | | | | | | | | | | | | | | | This patch implements saving/restoring of static apic_delivered variable. v8: saving static variable only for one of the APICs Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20170126123429.5412.94368.stgit@PASHA-ISP> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * replay: exception replay fixPavel Dovgalyuk2017-01-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes replaying the exception when TB cache is full. It breaks cpu loop execution through setting exception_index to process such queued work as TB flush. v8: moved setting of exeption_index to tb_gen_code Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20170126123418.5412.33815.stgit@PASHA-ISP> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * replay: save/load initial statePavel Dovgalyuk2017-01-276-3/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements initial vmstate creation or loading at the start of record/replay. It is needed for rewinding the execution in the replay mode. v4 changes: - snapshots are not created by default anymore v3 changes: - added rrsnapshot option Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20170124071746.4572.61449.stgit@PASHA-ISP> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * savevm: add public save_vmstate functionPavel Dovgalyuk2017-01-272-11/+23
| | | | | | | | | | | | | | | | | | This patch introduces save_vmstate function to allow saving and loading vmstates from the replay module. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20170124071741.4572.13714.stgit@PASHA-ISP> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * replay: don't use rtc clock on loadvm phasePavel Dovgalyuk2017-01-271-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | This patch disables the update of the periodic timer of mc146818rtc in record/replay mode. State of this timer is saved and therefore does not need to be updated in record/replay mode. Read of RTC breaks the replay because all rtc reads have to be the same as in record mode. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20170124071730.4572.41874.stgit@PASHA-ISP> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * replay: improve interrupt handlingPavel Dovgalyuk2017-01-272-1/+2
| | | | | | | | | | | | | | | | | | | | This patch improves interrupt handling in record/replay mode. Now "interrupt" event is saved only when cc->cpu_exec_interrupt returns true. This patch also adds missing return to cpu_exec_interrupt function. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20170124071708.4572.64023.stgit@PASHA-ISP> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * icount: update instruction counter on apic patchingPavel Dovgalyuk2017-01-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | kvmvapic patches the code when some instructions are executed. E.g. mov 0xff, 0xfffe0080 is interpreted as push 0xff/call ... This patching is also followed by some side effects (changing apic and guest memory state). Therefore deterministic execution should take this operation into account. This patch decreases icount when original mov instruction is trying to execute. Therefore patching becomes deterministic and can be replayed correctly. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20170124071702.4572.17294.stgit@PASHA-ISP> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2017-01-2718-169/+386
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20170127' into staging target-arm queue: * various minor M profile bugfixes * aspeed/smc: handle dummy bytes when doing fast reads in command mode * pflash_cfi01: fix per-device sector length in CFI table * arm: stellaris: make MII accesses complete immediately * hw/char/exynos4210_uart: Drop unused local variable frame_size * arm_gicv3: Fix broken logic in ELRSR calculation * dma: omap: check dma channel data_type # gpg: Signature made Fri 27 Jan 2017 15:29:39 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170127: (22 commits) dma: omap: check dma channel data_type arm_gicv3: Fix broken logic in ELRSR calculation hw/char/exynos4210_uart: Drop unused local variable frame_size arm: stellaris: make MII accesses complete immediately armv7m: R14 should reset to 0xffffffff armv7m: FAULTMASK should be 0 on reset armv7m: Honour CCR.USERSETMPEND armv7m: Report no-coprocessor faults correctly armv7m: set CFSR.UNDEFINSTR on undefined instructions armv7m: honour CCR.STACKALIGN on exception entry armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR armv7m_nvic: keep a pointer to the CPU target/arm: Drop IS_M() macro pflash_cfi01: fix per-device sector length in CFI table armv7m: Clear FAULTMASK on return from non-NMI exceptions armv7m: Fix reads of CONTROL register bit 1 hw/registerfields.h: Pull FIELD etc macros out of hw/register.h armv7m: Explicit error for bad vector table armv7m: Replace armv7m.hack with unassigned_access handler ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * dma: omap: check dma channel data_typePrasad J Pandit2017-01-271-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | When setting dma channel 'data_type', if (value & 3) == 3, the set 'data_type' is said to be bad. This also leads to an OOB access in 'omap_dma_transfer_generic', while doing cpu_physical_memory_r/w operations. Add check to avoid it. Reported-by: Jiang Xin <jiangxin1@huawei.com> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-id: 20170127120528.30959-1-ppandit@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * arm_gicv3: Fix broken logic in ELRSR calculationPeter Maydell2017-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix a broken expression in the calculation of ELRSR register bits: instead of "(lr & ICH_LR_EL2_HW) == 1" we want to check for != 0, because the HW bit is not bit 0 so a test for == 1 is always false. Fixes: https://bugs.launchpad.net/bugs/1658506 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 1485255993-6322-1-git-send-email-peter.maydell@linaro.org
| * hw/char/exynos4210_uart: Drop unused local variable frame_sizePeter Maydell2017-01-271-5/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The frame_size local variable in exynos4210_uart_update_parameters() is calculated but never used (and has been this way since the device was introduced in commit e5a4914efc7). The qemu_chr_fe_ioctl() doesn't need this information (if it really wanted it it could calculate it from the parity/data_bits/stop_bits), so just drop the variable entirely. Fixes: https://bugs.launchpad.net/bugs/1655702 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1484589515-26353-1-git-send-email-peter.maydell@linaro.org
| * arm: stellaris: make MII accesses complete immediatelyMichael Davidsaver2017-01-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the guest attempts to start an MII register access via the MCTL register, clear the START bit, so that when the guest reads it back the register transaction will be signalled as having completed. This avoids the guest spinning as it polls the START bit waiting for it to clear (which it previously never would). The MII registers themselves still aren't implemented, but at least we can avoid guests spending quite so much time busy waiting. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1484938222-1423-1-git-send-email-peter.maydell@linaro.org [PMM: expand commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: R14 should reset to 0xffffffffPeter Maydell2017-01-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For M profile (unlike A profile) the reset value of R14 is specified as 0xffffffff. (The rationale is that this is an illegal exception return value, so if guest code tries to return to it it will result in a helpful exception.) Registers r0 to r12 and the flags are architecturally UNKNOWN on reset, so we leave those at zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-11-git-send-email-peter.maydell@linaro.org
| * armv7m: FAULTMASK should be 0 on resetMichael Davidsaver2017-01-271-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK. QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the I bit) we have to clear these to undo the A profile default of 1. Update the comment accordingly and move it so that it's closer to the code it's referring to. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-10-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message, moved comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: Honour CCR.USERSETMPENDMichael Davidsaver2017-01-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | The CCR.USERSETMPEND bit has to be set to permit unprivileged code to write to the Software Triggered Interrupt register; honour this bit rather than letting any code write to the register. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-9-git-send-email-peter.maydell@linaro.org [PMM: Tweak commit message, comment, phrasing of condition] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: Report no-coprocessor faults correctlyPeter Maydell2017-01-274-0/+14
| | | | | | | | | | | | | | | | | | | | | | For v7M attempts to access a nonexistent coprocessor are reported differently from plain undefined instructions (as UsageFaults of type NOCP rather than type UNDEFINSTR). Split them out into a new EXCP_NOCP so we can report the FSR value correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-8-git-send-email-peter.maydell@linaro.org
| * armv7m: set CFSR.UNDEFINSTR on undefined instructionsMichael Davidsaver2017-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | When we take an exception for an undefined instruction, set the appropriate CFSR bit. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-7-git-send-email-peter.maydell@linaro.org [PMM: tweaked commit message, comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: honour CCR.STACKALIGN on exception entryMichael Davidsaver2017-01-271-4/+2Star
| | | | | | | | | | | | | | | | | | | | The CCR.STACKALIGN bit controls whether the CPU is supposed to force 8-alignment of the stack pointer on entry to the exception handler. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Message-id: 1485285380-10565-6-git-send-email-peter.maydell@linaro.org [PMM: commit message and comment tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFARMichael Davidsaver2017-01-271-10/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the v7M system registers CCR, CFSR, HFSR, DFSR, BFAR and MMFAR. For the moment these simply read as written (with some basic handling of RAZ/WI bits and W1C semantics). Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-5-git-send-email-peter.maydell@linaro.org [PMM: drop warning about setting unimplemented CCR bits; tweak commit message; add DFSR] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFARPeter Maydell2017-01-273-2/+69
| | | | | | | | | | | | | | | | | | | | Add the structure fields, VMState fields, reset code and macros for the v7M system control registers CCR, CFSR, HFSR, DFSR, MMFAR and BFAR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-4-git-send-email-peter.maydell@linaro.org
| * armv7m_nvic: keep a pointer to the CPUMichael Davidsaver2017-01-271-6/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many NVIC operations access the CPU state, so store a pointer in struct nvic_state rather than fetching it via qemu_get_cpu() every time we need it. As with the arm_gicv3_common code, we currently just call qemu_get_cpu() in the NVIC's realize method, but in future we might want to use a QOM property to pass the CPU to the NVIC. This imposes an ordering requirement that the CPU is realized before the NVIC, but that is always true since both are dealt with in armv7m_init(). Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-3-git-send-email-peter.maydell@linaro.org [PMM: Use qemu_get_cpu(0) rather than first_cpu; expand commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Drop IS_M() macroPeter Maydell2017-01-273-8/+2Star
| | | | | | | | | | | | | | | | | | | | We only use the IS_M() macro in two places, and it's a bit of a namespace grab to put in cpu.h. Drop it in favour of just explicitly calling arm_feature() in the places where it was used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-2-git-send-email-peter.maydell@linaro.org
| * pflash_cfi01: fix per-device sector length in CFI tablePeter Maydell2017-01-272-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For configurations of the pflash_cfi01 device which set it up with a device-width not equal to the width (ie where we are emulating multiple narrow flash devices wired up in parallel), we were giving incorrect values in the CFI data table: (1) the sector length entry should specify the sector length for a single device, not the length for the overall collection of devices (2) the number of blocks per device must not be divided by the number of devices because the resulting device size would not match the overall size (3) this then means that the overall write block size must be modified depending on the number of devices because the entry is per device and when the guest writes into the flash it calculates the write size by using the CFI entry (write size per device) multiplied by the number of chips. (It would alternatively be possible to modify the write block size in the CFI table (currently hardcoded at 2048) and leave the overall write block size alone.) This commit corrects these bugs, and adds a hw-compat property to retain the old behaviour on 2.8 and earlier versions. (The only board we have which uses this sort of flash config and has machine versioning is the "virt" board -- the PC uses a single flash device and so behaviour is unaffected whether using old-multiple-chip-handling or not.) Here is a configuration example from the vexpress board: VEXPRESS_FLASH_SIZE = 64M VEXPRESS_FLASH_SECT_SIZE 256K num-blocks = VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE = 256 sector-length = 256K width = 4 device-width = 2 The code will fill the CFI entry with the following entries: num-blocks = 256 sector-length = 128K writeblock_size = 2048 This results in two chips, each with 256 * 128K = 32M device size and a write block size of 2048. A sector erase will be sent to both chips, thus 256K must be erased. When the guest sends a block write command, it will write 4096 bytes data at once (2048 per device). Signed-off-by: David Engraf <david.engraf@sysgo.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: cleaned up and expanded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: Clear FAULTMASK on return from non-NMI exceptionsMichael Davidsaver2017-01-271-1/+6
| | | | | | | | | | | | | | | | | | | | | | FAULTMASK must be cleared on return from all exceptions other than NMI. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-7-git-send-email-peter.maydell@linaro.org
| * armv7m: Fix reads of CONTROL register bit 1Michael Davidsaver2017-01-274-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The v7m CONTROL register bit 1 is SPSEL, which indicates the stack being used. We were storing this information not in v7m.control but in the separate v7m.other_sp structure field. Unfortunately, the code handling reads of the CONTROL register didn't take account of this, and so if SPSEL was updated by an exception entry or exit then a subsequent guest read of CONTROL would get the wrong value. Using a separate structure field doesn't really gain us anything in efficiency, so drop this unnecessary complexity in favour of simply storing all the bits in v7m.control. This is a migration compatibility break for M profile CPUs only. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-6-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message; use deposit32(); use FIELD to define constants for masking and shifting of CONTROL register fields ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/registerfields.h: Pull FIELD etc macros out of hw/register.hPeter Maydell2017-01-272-46/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hw/register.h provides macros like FIELD which make it easy to define shift, mask and length constants for the fields within a register. Unfortunately register.h also includes a lot of other things, some of which will only compile in the softmmu build. Pull the FIELD macro and friends out into a separate header file, so they can be used in places like target/arm files which also get built in the user-only configs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-5-git-send-email-peter.maydell@linaro.org
| * armv7m: Explicit error for bad vector tableMichael Davidsaver2017-01-271-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Give an explicit error and abort when a load from the vector table fails. Architecturally this should HardFault (which will then immediately fail to load the HardFault vector and go into Lockup). Since we don't model Lockup, just report this guest error via cpu_abort(). This is more helpful than the previous behaviour of reading a zero, which is the address of the reset stack pointer and not a sensible location to jump to. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-4-git-send-email-peter.maydell@linaro.org [PMM: expanded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: Replace armv7m.hack with unassigned_access handlerMichael Davidsaver2017-01-273-14/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For v7m we need to catch attempts to execute from special addresses at 0xfffffff0 and above. Previously we did this with the aid of a hacky special purpose lump of memory in the address space and a check in translate.c for whether we were translating code at those addresses. We can implement this more cleanly using a CPU unassigned access handler which throws the exception if the unassigned access is for one of the special addresses. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-3-git-send-email-peter.maydell@linaro.org [PMM: * drop the deletion of the "don't interrupt if PC is magic" code in arm_v7m_cpu_exec_interrupt() -- this is still required * don't generate an exception for unassigned accesses which aren't to the magic address -- although doing this is in theory correct in practice it will break currently working guests which rely on the RAZ/WI behaviour when they touch devices which we haven't modelled. * trigger EXCP_EXCEPTION_EXIT on is_exec, not !is_write ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armv7m: MRS/MSR: handle unprivileged accessMichael Davidsaver2017-01-271-42/+37Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MRS and MSR instruction handling has a number of flaws: * unprivileged accesses should only be able to read CONTROL and the xPSR subfields, and only write APSR (others RAZ/WI) * privileged access should not be able to write xPSR subfields other than APSR * accesses to unimplemented registers should log as guest errors, not abort QEMU Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1484937883-1068-2-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * aspeed/smc: handle dummy bytes when doing fast reads in command modeCédric Le Goater2017-01-271-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing fast read, a certain amount of dummy bytes should be sent before the read. This number is configurable in the controler CE0 Control Register and needs to be modeled using fake transfers to the flash module. This only supports command mode. User mode requires more work and a possible extension of the m25p80 device model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Marcin Krzemiński <mar.krzeminski@gmail.com> Message-id: 1484751701-2646-1-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-01-27' into ↵Peter Maydell2017-01-275-15/+15
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging QAPI/QMP patches for 2017-01-27 # gpg: Signature made Fri 27 Jan 2017 07:24:02 GMT # gpg: using RSA key 0x3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2017-01-27: qmp: Fix argument name in error message of device-list-properties qapi: Remove unwanted commas after #optional keyword build-sys: Minor qapi doc generation target cleanups Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * qmp: Fix argument name in error message of device-list-propertiesLin Ma2017-01-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | The argument is called "typename", not "name". [Thanks to Markus for correcting the commit message] Signed-off-by: Lin Ma <lma@suse.com> Message-Id: <20170125052703.23571-1-lma@suse.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
| * qapi: Remove unwanted commas after #optional keywordStefan Weil2017-01-273-10/+10
| | | | | | | | | | | | | | | | | | | | We don't want that commas to be part of the generated documentation, so remove them. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20170122145407.27476-1-sw@weilnetz.de> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
| * build-sys: Minor qapi doc generation target cleanupsMarkus Armbruster2017-01-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | Move makeinfo flags from MAKEINFO to MAKEINFOFLAGS. Fix the call of quiet-command for target qemu-ga-qapi.texi. Both messed up in commit 56e8bdd. Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1484816804-12598-1-git-send-email-armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
* | Merge remote-tracking branch 'remotes/berrange/tags/pull-qio-2017-01-26-1' ↵Peter Maydell2017-01-272-1/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Merge io/ 2017/01/26 # gpg: Signature made Thu 26 Jan 2017 10:26:48 GMT # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/pull-qio-2017-01-26-1: io: fix possible double free of task error object Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | io: fix possible double free of task error objectDaniel P. Berrange2017-01-262-1/+4
| |/ | | | | | | | | | | | | | | | | | | | | If a QIOTask has an error set and the calling code uses qio_task_propagate_error() to steal the reference to that Error object, the task would not clear its own reference. This would lead to a double-free when qio_task_free runs, if the caller had (correctly) freed the Error object they now owned. Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170126' into stagingPeter Maydell2017-01-271-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One compile fix for s390x with kvm enabled. # gpg: Signature made Thu 26 Jan 2017 10:57:55 GMT # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20170126: s390x/flic: fix compilation of kvm flic Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | s390x/flic: fix compilation of kvm flicCornelia Huck2017-01-261-1/+1
| |/ | | | | | | | | | | | | | | | | 2c21ee7 ("migration: extend VMStateInfo") missed a void -> int return conversion for kvm_flic_save(). Fixes: 2c21ee7 ("migration: extend VMStateInfo") Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* | Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell2017-01-271-1/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging # gpg: Signature made Thu 26 Jan 2017 10:19:35 GMT # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: aio-posix: honor is_external in AioContext polling Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | aio-posix: honor is_external in AioContext pollingStefan Hajnoczi2017-01-261-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AioHandlers marked ->is_external must be skipped when aio_node_check() fails. bdrv_drained_begin() needs this to prevent dataplane from submitting new I/O requests while another thread accesses the device and relies on it being quiesced. This patch fixes the following segfault: Program terminated with signal SIGSEGV, Segmentation fault. #0 0x00005577f6127dad in bdrv_io_plug (bs=0x5577f7ae52f0) at qemu/block/io.c:2650 2650 bdrv_io_plug(child->bs); [Current thread is 1 (Thread 0x7ff5c4bd1c80 (LWP 10917))] (gdb) bt #0 0x00005577f6127dad in bdrv_io_plug (bs=0x5577f7ae52f0) at qemu/block/io.c:2650 #1 0x00005577f6114363 in blk_io_plug (blk=0x5577f7b8ba20) at qemu/block/block-backend.c:1561 #2 0x00005577f5d4091d in virtio_blk_handle_vq (s=0x5577f9ada030, vq=0x5577f9b3d2a0) at qemu/hw/block/virtio-blk.c:589 #3 0x00005577f5d4240d in virtio_blk_data_plane_handle_output (vdev=0x5577f9ada030, vq=0x5577f9b3d2a0) at qemu/hw/block/dataplane/virtio-blk.c:158 #4 0x00005577f5d88acd in virtio_queue_notify_aio_vq (vq=0x5577f9b3d2a0) at qemu/hw/virtio/virtio.c:1304 #5 0x00005577f5d8aaaf in virtio_queue_host_notifier_aio_poll (opaque=0x5577f9b3d308) at qemu/hw/virtio/virtio.c:2134 #6 0x00005577f60ca077 in run_poll_handlers_once (ctx=0x5577f79ddbb0) at qemu/aio-posix.c:493 #7 0x00005577f60ca268 in try_poll_mode (ctx=0x5577f79ddbb0, blocking=true) at qemu/aio-posix.c:569 #8 0x00005577f60ca331 in aio_poll (ctx=0x5577f79ddbb0, blocking=true) at qemu/aio-posix.c:601 #9 0x00005577f612722a in bdrv_flush (bs=0x5577f7c20970) at qemu/block/io.c:2403 #10 0x00005577f60c1b2d in bdrv_close (bs=0x5577f7c20970) at qemu/block.c:2322 #11 0x00005577f60c20e7 in bdrv_delete (bs=0x5577f7c20970) at qemu/block.c:2465 #12 0x00005577f60c3ecf in bdrv_unref (bs=0x5577f7c20970) at qemu/block.c:3425 #13 0x00005577f60bf951 in bdrv_root_unref_child (child=0x5577f7a2de70) at qemu/block.c:1361 #14 0x00005577f6112162 in blk_remove_bs (blk=0x5577f7b8ba20) at qemu/block/block-backend.c:491 #15 0x00005577f6111b1b in blk_remove_all_bs () at qemu/block/block-backend.c:245 #16 0x00005577f60c1db6 in bdrv_close_all () at qemu/block.c:2382 #17 0x00005577f5e60cca in main (argc=20, argv=0x7ffea6eb8398, envp=0x7ffea6eb8440) at qemu/vl.c:4684 The key thing is that bdrv_close() uses bdrv_drained_begin() and virtio_queue_host_notifier_aio_poll() must not be called. Thanks to Fam Zheng <famz@redhat.com> for identifying the root cause of this crash. Reported-by: Alberto Garcia <berto@igalia.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Tested-by: Alberto Garcia <berto@igalia.com> Message-id: 20170124095350.16679-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* | Merge remote-tracking branch 'remotes/famz/tags/for-upstream' into stagingPeter Maydell2017-01-273-3/+43
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | # gpg: Signature made Thu 26 Jan 2017 02:44:47 GMT # gpg: using RSA key 0xCA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/for-upstream: test-hbitmap: Add hbitmap_is_serializable() calls hbitmap: Add hbitmap_is_serializable() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * test-hbitmap: Add hbitmap_is_serializable() callsMax Reitz2017-01-261-0/+11
| | | | | | | | | | | | | | | | | | | | | | Add calls to hbitmap_is_serializable() (asserting that it returns true) where necessary (i.e. before every series of (de-)serialization function invocations). Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20161115225746.3590-3-mreitz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
| * hbitmap: Add hbitmap_is_serializable()Max Reitz2017-01-262-3/+32
|/ | | | | | | | | | | | | Bitmaps with a granularity of 58 or above can be neither serialized nor deserialized (see the comment in the function added in this series for an explanation). This patch adds a function so that we can check whether a bitmap actually can be (de-)serialized at all, thus avoiding failing the necessary assertion in hbitmap_serialization_granularity(). Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20161115225746.3590-2-mreitz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
* Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into stagingPeter Maydell2017-01-253-13/+26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pull request fixes a 2.9 regression and a long standing bug that can cause 9p clients to hang. Other patches are minor enhancements. # gpg: Signature made Wed 25 Jan 2017 10:12:27 GMT # gpg: using DSA key 0x02FC3AEB0101DBC2 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" # gpg: aka "Greg Kurz <groug@free.fr>" # gpg: aka "Greg Kurz <gkurz@fr.ibm.com>" # gpg: aka "Greg Kurz <gkurz@linux.vnet.ibm.com>" # gpg: aka "Gregory Kurz (Groug) <groug@free.fr>" # gpg: aka "Gregory Kurz (Cimai Technology) <gkurz@cimai.com>" # gpg: aka "Gregory Kurz (Meiosys Technology) <gkurz@meiosys.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2BD4 3B44 535E C0A7 9894 DBA2 02FC 3AEB 0101 DBC2 * remotes/gkurz/tags/for-upstream: 9pfs: fix offset error in v9fs_xattr_read() 9pfs: local: trivial cosmetic fix in pwritev op 9pfs: fix off-by-one error in PDU free list tests: virtio-9p: improve error reporting 9pfs: add missing coroutine_fn annotations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * 9pfs: fix offset error in v9fs_xattr_read()Greg Kurz2017-01-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code tries to copy `read_count' bytes starting at offset `offset' from a `read_count`-sized iovec. This causes v9fs_pack() to fail with ENOBUFS. Since the PDU iovec is already partially filled with `offset' bytes, let's skip them when creating `qiov_full' and have v9fs_pack() to copy the whole of it. Moreover, this is consistent with the other places where v9fs_init_qiov_from_pdu() is called. This fixes commit "bcb8998fac16 9pfs: call v9fs_init_qiov_from_pdu before v9fs_pack". Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
| * 9pfs: local: trivial cosmetic fix in pwritev opGreg Kurz2017-01-251-2/+1Star
| | | | | | | | Signed-off-by: Greg Kurz <groug@kaod.org>
| * 9pfs: fix off-by-one error in PDU free listGreg Kurz2017-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The server can handle MAX_REQ - 1 PDUs at a time and the virtio-9p device has a MAX_REQ sized virtqueue. If the client manages to fill up the virtqueue, pdu_alloc() will fail and the request won't be processed without any notice to the client (it actually causes the linux 9p client to hang). This has been there since the beginning (commit 9f10751365b2 "virtio-9p: Add a virtio 9p device to qemu"), but it needs an agressive workload to run in the guest to show up. We actually allocate MAX_REQ PDUs and I see no reason not to link them all into the free list, so let's fix the init loop. Reported-by: Tuomas Tynkkynen <tuomas@tuxera.com> Suggested-by: Al Viro <viro@ZenIV.linux.org.uk> Signed-off-by: Greg Kurz <groug@kaod.org>
| * tests: virtio-9p: improve error reportingGreg Kurz2017-01-251-5/+19
| | | | | | | | Signed-off-by: Greg Kurz <groug@kaod.org>
| * 9pfs: add missing coroutine_fn annotationsGreg Kurz2017-01-251-2/+2
| | | | | | | | Signed-off-by: Greg Kurz <groug@kaod.org>
* | Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into stagingPeter Maydell2017-01-2512-203/+456
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | target/xtensa updates: - refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting); - support icount; run target/xtensa TCG tests with icount; - implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER. # gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170124-xtensa: target-xtensa: implement RER/WER instructions target/xtensa: tests: clean up interrupt tests target/xtensa: tests: add memctl test target/xtensa: implement MEMCTL SR target/xtensa: fix ICACHE/DCACHE options detection target/xtensa: tests: add ccount write tests target/xtensa: tests: replace hardcoded interrupt masks target/xtensa: tests: fix timer tests target/xtensa: tests: run tests with icount target/xtensa: don't continue translation after exception target/xtensa: support icount target/xtensa: refactor CCOUNT/CCOMPARE target/xtensa: implement RUNSTALL target/xtensa: add static vectors selection Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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