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* Merge remote-tracking branch 'remotes/kwolf-gitlab/tags/for-upstream' into ↵Peter Maydell2022-02-144-10/+52
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Block layer patches - Fix crash in blockdev-reopen with iothreads - fdc-isa: Respect QOM properties when building AML # gpg: Signature made Fri 11 Feb 2022 17:44:52 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kwolf-gitlab/tags/for-upstream: hw/block/fdc-isa: Respect QOM properties when building AML iotests: Test blockdev-reopen with iothreads and throttling block: Lock AioContext for drain_end in blockdev-reopen Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/block/fdc-isa: Respect QOM properties when building AMLBernhard Beschow2022-02-111-4/+7
| | | | | | | | | | | | | | | | | | | | Other ISA devices such as serial-isa use the properties in their build_aml functions. fdc-isa not using them is probably an oversight. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20220209191558.30393-1-shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * iotests: Test blockdev-reopen with iothreads and throttlingKevin Wolf2022-02-112-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | The 'throttle' block driver implements .bdrv_co_drain_end, so blockdev-reopen will have to wait for it to complete in the polling loop at the end of qmp_blockdev_reopen(). This makes AIO_WAIT_WHILE() release the AioContext lock, which causes a crash if the lock hasn't correctly been taken. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20220203140534.36522-3-kwolf@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * block: Lock AioContext for drain_end in blockdev-reopenKevin Wolf2022-02-111-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bdrv_subtree_drained_end() requires the caller to hold the AioContext lock for the drained node. Not doing this for nodes outside of the main AioContext leads to crashes when AIO_WAIT_WHILE() needs to wait and tries to temporarily release the lock. Fixes: 3908b7a8994fa5ef7a89aa58cd5a02fc58141592 Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2046659 Reported-by: Qing Wang <qinwang@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20220203140534.36522-2-kwolf@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220211' ↵Peter Maydell2022-02-1436-495/+1561
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Fix safe_syscall_base for sparc64. Fix host signal handling for sparc64-linux. Speedups for jump cache and work list probing. Fix for exception replays. Raise guest SIGBUS for user-only misaligned accesses. # gpg: Signature made Fri 11 Feb 2022 01:27:16 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20220211: (34 commits) tests/tcg/multiarch: Add sigbus.c tcg/sparc: Support unaligned access for user-only tcg/sparc: Add tcg_out_jmpl_const for better tail calls tcg/sparc: Use the constant pool for 64-bit constants tcg/sparc: Convert patch_reloc to return bool tcg/sparc: Improve code gen for shifted 32-bit constants tcg/sparc: Add scratch argument to tcg_out_movi_int tcg/sparc: Split out tcg_out_movi_imm32 tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64 tcg/mips: Support unaligned access for softmmu tcg/mips: Support unaligned access for user-only tcg/arm: Support raising sigbus for user-only tcg/arm: Reserve a register for guest_base tcg/arm: Support unaligned access for softmmu tcg/arm: Check alignment for ldrd and strd tcg/arm: Remove use_armv6_instructions tcg/arm: Remove use_armv5t_instructions tcg/arm: Drop support for armv4 and armv5 hosts tcg/loongarch64: Support raising sigbus for user-only tcg/tci: Support raising sigbus for user-only ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/tcg/multiarch: Add sigbus.cRichard Henderson2022-02-081-0/+68
| | | | | | | | | | | | | | | | | | | | | A mostly generic test for unaligned access raising SIGBUS. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Support unaligned access for user-onlyRichard Henderson2022-02-081-8/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. This inline code expansion is somewhat large, but it takes quite a few instructions to make a function call to a helper anyway. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Add tcg_out_jmpl_const for better tail callsRichard Henderson2022-02-081-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to mapping changes, we now rarely place the code_gen_buffer near the main executable. Which means that direct calls will now rarely be in range. So, always use indirect calls for tail calls, which allows us to avoid clobbering %o7, and therefore we need not save and restore it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Use the constant pool for 64-bit constantsRichard Henderson2022-02-081-0/+15
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Convert patch_reloc to return boolRichard Henderson2022-02-081-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 7ecd02a06f8, if patch_reloc fails we restart translation with a smaller TB. SPARC had its function signature changed, but not the logic. Replace assert with return false. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Improve code gen for shifted 32-bit constantsRichard Henderson2022-02-081-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We had code for checking for 13 and 21-bit shifted constants, but we can do better and allow 32-bit shifted constants. This is still 2 insns shorter than the full 64-bit sequence. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Add scratch argument to tcg_out_movi_intRichard Henderson2022-02-081-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | This will allow us to control exactly what scratch register is used for loading the constant. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Split out tcg_out_movi_imm32Richard Henderson2022-02-081-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle 32-bit constants with a separate function, so that tcg_out_movi_int does not need to recurse. This slightly rearranges the order of tests for small constants, but produces the same output. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64Richard Henderson2022-02-081-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When BH is constant, it is constrained to 11 bits for use in MOVCC. For the cases in which we must load the constant BH into a register, we do not need the full logic of tcg_out_movi; we can use the simpler function for emitting a 13 bit constant. This eliminates the only case in which TCG_REG_T2 was passed to tcg_out_movi, which will shortly become invalid. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/mips: Support unaligned access for softmmuRichard Henderson2022-02-081-40/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can use the routines just added for user-only to emit unaligned accesses in softmmu mode too. Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/mips: Support unaligned access for user-onlyRichard Henderson2022-02-082-8/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. Fortunately, the ISA contains pairs of instructions that are used to implement unaligned memory accesses. Use them. Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Support raising sigbus for user-onlyRichard Henderson2022-02-082-4/+81
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Reserve a register for guest_baseRichard Henderson2022-02-081-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | Reserve a register for the guest_base using aarch64 for reference. By doing so, we do not have to recompute it for every memory load. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Support unaligned access for softmmuRichard Henderson2022-02-081-20/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | From armv6, the architecture supports unaligned accesses. All we need to do is perform the correct alignment check in tcg_out_tlb_read. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Check alignment for ldrd and strdRichard Henderson2022-02-081-15/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | We will shortly allow the use of unaligned memory accesses, and these require proper alignment. Use get_alignment_bits to verify and remove USING_SOFTMMU. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Remove use_armv6_instructionsRichard Henderson2022-02-082-166/+27Star
| | | | | | | | | | | | | | | | | | | | | This is now always true, since we require armv6. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Remove use_armv5t_instructionsRichard Henderson2022-02-082-31/+7Star
| | | | | | | | | | | | | | | | | | | | | This is now always true, since we require armv6. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Drop support for armv4 and armv5 hostsRichard Henderson2022-02-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support for unaligned accesses is difficult for pre-v6 hosts. While debian still builds for armv4, we cannot use a compile time test, so test the architecture at runtime and error out. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/loongarch64: Support raising sigbus for user-onlyWANG Xuerui2022-02-082-4/+69
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220106134238.3936163-1-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tci: Support raising sigbus for user-onlyRichard Henderson2022-02-081-6/+14
| | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Support raising sigbus for user-onlyRichard Henderson2022-02-082-4/+57
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/riscv: Support raising sigbus for user-onlyRichard Henderson2022-02-082-4/+61
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/ppc: Support raising sigbus for user-onlyRichard Henderson2022-02-082-10/+90
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/aarch64: Support raising sigbus for user-onlyRichard Henderson2022-02-082-19/+74
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Support raising sigbus for user-onlyRichard Henderson2022-02-082-7/+98
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/loongarch64: Fix fallout from recent MO_Q renamingWANG Xuerui2022-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently we were left behind; just renaming MO_Q to MO_UQ is enough. Fixes: fc313c64345453c7 ("exec/memop: Adding signedness to quad definitions") Signed-off-by: WANG Xuerui <git@xen0n.name> Message-Id: <20220206162106.1092364-1-i.qemu@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | replay: use CF_NOIRQ for special exception-replaying TBPavel Dovgalyuk2022-02-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit aff0e204cb1f1c036a496c94c15f5dfafcd9b4b4 introduced CF_NOIRQ usage, but one case was forgotten. Record/replay uses one special TB which is not really executed, but used to cause a correct exception in replay mode. This patch adds CF_NOIRQ flag for such block. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <164362834054.1754532.7678416881159817273.stgit@pasha-ThinkPad-X280> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | softmmu/cpus: Check if the cpu work list is empty atomicallyIdan Horowitz2022-02-081-6/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of taking the lock of the cpu work list in order to check if it's empty, we can just read the head pointer atomically. This decreases cpu_work_list_empty's share from 5% to 1.3% in a profile of icount-enabled aarch64-softmmu. Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com> Message-Id: <20220114004358.299534-1-idan.horowitz@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/tcg: Optimize jump cache flush during tlb range flushIdan Horowitz2022-02-081-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the length of the range is large enough, clearing the whole cache is faster than iterating over the (possibly extremely large) set of pages contained in the range. This mimics the pre-existing similar optimization done on the flush of the tlb itself. Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com> Message-Id: <20220110164754.1066025-1-idan.horowitz@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | linux-user/include/host/sparc64: Fix host_sigcontextRichard Henderson2022-02-081-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparc64 is unique on linux in *not* passing ucontext_t as the third argument to a SA_SIGINFO handler. It passes the old struct sigcontext instead. Set both pc and npc in host_signal_set_pc. Fixes: 8b5bd461935b ("linux-user/host/sparc: Populate host_signal.h") Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | linux-user: Move sparc/host-signal.h to sparc64/host-signal.hRichard Henderson2022-02-082-72/+63Star
| | | | | | | | | | | | | | | | | | | | | | | | We do not support sparc32 as a host, so there's no point in sparc64 redirecting to sparc. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | linux-user: Introduce host_sigcontextRichard Henderson2022-02-0812-47/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | Do not directly access ucontext_t as the third signal parameter. This is preparation for a sparc64 fix. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | linux-user: Introduce host_signal_maskRichard Henderson2022-02-0812-10/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Do not directly access the uc_sigmask member. This is preparation for a sparc64 fix. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | common-user/host/sparc64: Fix safe_syscall_baseRichard Henderson2022-02-081-2/+3
| |/ | | | | | | | | | | | | | | | | | | | | Use the "retl" instead of "ret" instruction alias, since we do not allocate a register window in this function. Fix the offset to the first stacked parameter, which lies beyond the register window save area. Fixes: 95c021dac835 ("linux-user/host/sparc64: Add safe-syscall.inc.S") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220210' into ↵Peter Maydell2022-02-1332-2250/+592Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging ppc-7.0 queue * Exception model rework (Fabiano) * Unused CPU models removal (Fabiano and Cédric) * Fix for VOF installation (Alexey) * Misc fixes # gpg: Signature made Thu 10 Feb 2022 12:59:07 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-ppc-20220210: (42 commits) spapr/vof: Install rom and nvram binaries docs: rstfy confidential guest documentation target/ppc: Change VSX instructions behavior to fill with zeros target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail target/ppc: Assert if MSR bits differ from msr_mask during exceptions target/ppc: powerpc_excp: Move common code to the caller function target/ppc: Remove powerpc_excp_legacy target/ppc: 7xx: Set SRRs directly in exception code target/ppc: 7xx: Software TLB cleanup target/ppc: 7xx: System Reset cleanup target/ppc: 7xx: System Call exception cleanup target/ppc: 7xx: Program exception cleanup target/ppc: 7xx: External interrupt cleanup target/ppc: 7xx: Machine Check exception cleanup target/ppc: Simplify powerpc_excp_7xx target/ppc: Introduce powerpc_excp_7xx target/ppc: Merge 7x5 and 7x0 exception model IDs target/ppc: 6xx: Set SRRs directly in exception code target/ppc: 6xx: Software TLB exceptions cleanup target/ppc: 6xx: System Reset interrupt cleanup ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | spapr/vof: Install rom and nvram binariesAlexey Kardashevskiy2022-02-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This installs VOF-related binaries (the firmware and the preformatted NVRAM) as those were left out when the VOF was submitted initially. Fixes: fc8c745d5015 ("spapr: Implement Open Firmware client interface") Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20220208103751.1587902-1-aik@ozlabs.ru> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | docs: rstfy confidential guest documentationCornelia Huck2022-02-096-56/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also rstfy the documentation for AMD SEV, and link it. The documentation for PEF had been merged into the pseries doc, fix the reference. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220204161251.241877-1-cohuck@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: Change VSX instructions behavior to fill with zerosVíctor Colombo2022-02-092-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISA v3.1 changed some VSX instructions behavior by changing what the other words/doubleword in the result should contain when the result is only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and saves the result also in doubleword 0. Before, the second doubleword result was undefined according to the ISA, but now it's stated that it should be zeroed. Even tough the result was undefined before, hardware implementing these instructions already filled these fields with 0s. Changing every ISA version in QEMU to this behavior makes the results match what happens in hardware. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220204181944.65063-1-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: books: Remove excp_model argument from ppc_excp_apply_ailFabiano Rosas2022-02-091-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't really need to check for exception model while applying AIL. We can check the lpcr_mask for the presence of LPCR_AIL/LPCR_HAIL. This removes one more instance of passing the exception model ID around. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: Assert if MSR bits differ from msr_mask during exceptionsFabiano Rosas2022-02-091-58/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently abort QEMU during the dispatch of an interrupt if we try to set MSR_HV without having MSR_HVB in the msr_mask. I think we should verify this for all MSR bits. There is no reason to ever have a MSR bit set if the corresponding bit is not set in that CPU's msr_mask. Note that this is not about the emulated code setting reserved bits. We clear the new_msr when starting to dispatch an exception, so if we end up with bits not present in the msr_mask that is a QEMU programming error. I kept the HSRR verification for BookS because it is the only CPU family that has HSRRs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: powerpc_excp: Move common code to the caller functionFabiano Rosas2022-02-091-48/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the cpu-specific powerpc_excp_* functions a bit simpler by moving the bounds check and logging to powerpc_excp. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: Remove powerpc_excp_legacyFabiano Rosas2022-02-091-474/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that all CPU families have their own separate exception dispatching code we can remove powerpc_excp_legacy. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: 7xx: Set SRRs directly in exception codeFabiano Rosas2022-02-091-11/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | The 7xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: 7xx: Software TLB cleanupFabiano Rosas2022-02-091-20/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | This code applies only to the 7xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | target/ppc: 7xx: System Reset cleanupFabiano Rosas2022-02-091-16/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | Thre is no HV support in the 7xx. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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