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* Merge remote-tracking branch ↵Richard Henderson2021-10-0715-479/+516
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair23/tags/pull-riscv-to-apply-20211007' into staging Third RISC-V PR for QEMU 6.2 - Add Zb[abcs] instruction support - Remove RVB support - Bug fix of setting mstatus_hs.[SD|FS] bits - Mark some UART devices as 'input' - QOMify PolarFire MMUART - Fixes for sifive PDMA - Mark shakti_c as not user creatable # gpg: Signature made Wed 06 Oct 2021 11:42:53 PM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211007: (26 commits) hw/riscv: shakti_c: Mark as not user creatable hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed hw/dma: sifive_pdma: Fix Control.claim bit detection hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition hw/char: sifive_uart: Register device in 'input' category hw/char: shakti_uart: Register device in 'input' category hw/char: ibex_uart: Register device in 'input' category target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() disas/riscv: Add Zb[abcs] instructions target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Add a REQUIRE_32BIT macro target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Reassign instructions to the Zbb-extension target/riscv: Add instructions of the Zbc-extension target/riscv: Reassign instructions to the Zbs-extension target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/riscv: shakti_c: Mark as not user creatableAlistair Francis2021-10-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | Mark the shakti_c machine as not user creatable. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
| * hw/dma: sifive_pdma: Don't run DMA when channel is disclaimedBin Meng2021-10-071-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If Control.run bit is set while not preserving the Control.claim bit, the DMA transfer shall not be started. The following result is PDMA tested in U-Boot on Unleashed board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes) => mw.q 0x3000008 0x2 <= NextBytes = 2 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 55000000 00000002 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x2 <= Set channel 0 run bit only => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000000 55000000 00000002 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/dma: sifive_pdma: Fix Control.claim bit detectionBin Meng2021-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the codes detect whether the DMA channel is claimed by: claimed = !!s->chan[ch].control & CONTROL_CLAIM; As ! has higher precedence over & (bitwise and), this is essentially claimed = (!!s->chan[ch].control) & CONTROL_CLAIM; which is wrong, as any non-zero bit set in the control register will produce a result of a claimed channel. Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUARTPhilippe Mathieu-Daudé2021-10-072-16/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() - Add DeviceReset() method - Add vmstate structure for migration - Register device in 'input' category - Keep mchp_pfsoc_mmuart_create() behavior Note, serial_mm_init() calls qdev_set_legacy_instance_id(). This call is only needed for backwards-compatibility of incoming migration data with old versions of QEMU which implemented migration of devices with hand-rolled code. Since this device didn't previously handle migration at all, then it doesn't need to set the legacy instance ID. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210925133407.1259392-4-f4bug@amsat.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion containerPhilippe Mathieu-Daudé2021-10-072-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our device have 2 different I/O regions: - a 16550 UART mapped for 32-bit accesses - 13 extra registers Instead of mapping each region on the main bus, introduce a container, map the 2 devices regions on the container, and map the container on the main bus. Before: (qemu) info mtree ... 0000000020100000-000000002010001f (prio 0, i/o): serial 0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020102000-000000002010201f (prio 0, i/o): serial 0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020104000-000000002010401f (prio 0, i/o): serial 0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020106000-000000002010601f (prio 0, i/o): serial 0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart After: (qemu) info mtree ... 0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020100000-000000002010001f (prio 0, i/o): serial 0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs 0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020102000-000000002010201f (prio 0, i/o): serial 0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs 0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020104000-000000002010401f (prio 0, i/o): serial 0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs 0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020106000-000000002010601f (prio 0, i/o): serial 0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 20210925133407.1259392-3-f4bug@amsat.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definitionPhilippe Mathieu-Daudé2021-10-072-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the size occupied by all the registers. However all registers are 32-bit wide, and the MemoryRegionOps handlers are restricted to 32-bit: static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { .read = mchp_pfsoc_mmuart_read, .write = mchp_pfsoc_mmuart_write, .impl = { .min_access_size = 4, .max_access_size = 4, }, Avoid being triskaidekaphobic, simplify by using the number of registers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210925133407.1259392-2-f4bug@amsat.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/char: sifive_uart: Register device in 'input' categoryBin Meng2021-10-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | The category of sifive_uart device is not set. Put it into the 'input' category. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210926105003.2716-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/char: shakti_uart: Register device in 'input' categoryBin Meng2021-10-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | The category of shakti_uart device is not set. Put it into the 'input' category. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210926105003.2716-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/char: ibex_uart: Register device in 'input' categoryBin Meng2021-10-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | The category of ibex_uart device is not set. Put it into the 'input' category. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210926105003.2716-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-072-13/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=1. We can't early return for this case because we still need to set sstatus.FS to Dirty according to spec. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Vincent Chen <vincent.chen@sifive.com> Tested-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210921020234.123448-1-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich2021-10-071-3/+154
| | | | | | | | | | | | | | | | | | | | With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-073-33/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With everything classified as Zb[abcs] and pre-0.93 draft-B instructions that are not part of Zb[abcs] removed, we can remove the remaining support code for RVB. Note that RVB has been retired for good and misa.B will neither mean 'some' or 'all of' Zb*: https://lists.riscv.org/g/tech-bitmanip/message/532 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2021-10-072-77/+21Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which is handled through REQUIRE_32BIT. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-074-79/+15Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (both a sign-extending and zero-extending 32-bit version can easily be synthesized by following rev8 with either a srai or srli instruction on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are different. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich2021-10-071-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | With the changes to Zb[abcs], there's some encodings that are different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, we'll need a helper macro allowing us to select on RV32, as well. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-074-55/+18Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2021-10-072-41/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-074-1/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2021-10-072-18/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2021-10-072-78/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2021-10-072-63/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extention and have not been present in the binutils patches circulating in January 2021. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2021-10-072-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-072-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in target/riscv/cpu.[ch]. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich2021-10-071-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assume clzw being executed on a register that is not sign-extended, such as for the following sequence that uses (1ULL << 63) | 392 as the operand to clzw: bseti a2, zero, 63 addi a2, a2, 392 clzw a3, a2 The correct result of clzw would be 23, but the current implementation returns -32 (as it performs a 64bit clz, which results in 0 leading zero bits, and then subtracts 32). Fix this by changing the implementation to: 1. shift the original register up by 32 2. performs a target-length (64bit) clz 3. return 32 if no bits are set Marking this instruction as 'w-form' (i.e., setting ctx->w) would not correctly model the behaviour, as the instruction should not perform a zero-extensions on the input (after all, it is not a .uw instruction) and the result is always in the range 0..32 (so neither a sign-extension nor a zero-extension on the result will ever be needed). Consequently, we do not set ctx->w and mark the instruction as EXT_NONE. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com> Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich2021-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The refactored gen_clzw() uses ret as its argument, instead of arg1. Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary") Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich2021-10-071-2/+4
|/ | | | | | | | | | | | | | Following the recent changes in translate.c, gen_add_uw() causes failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these regressions by introducing a temporary. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*") Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into stagingRichard Henderson2021-10-069-58/+185
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change from Philippe - Use tcg_constant_* Change from Philippe - Remove unused TCG temp Change from Taylor - Probe the stores in a packet at start of commit # gpg: Signature made Wed 06 Oct 2021 08:44:13 AM PDT # gpg: using RSA key 7B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * remotes/quic/tags/pull-hex-20211006: target/hexagon: Use tcg_constant_* target/hexagon: Remove unused TCG temporary from predicated loads Hexagon (target/hexagon) probe the stores in a packet at start of commit Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/hexagon: Use tcg_constant_*Philippe Mathieu-Daudé2021-10-065-53/+25Star
| | | | | | | | | | | | | | | | | | | | Replace uses of tcg_const_* with the allocate and free close together. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211003004750.3608983-3-f4bug@amsat.org>
| * target/hexagon: Remove unused TCG temporary from predicated loadsPhilippe Mathieu-Daudé2021-10-061-2/+0Star
| | | | | | | | | | | | | | | | | | | | The gen_pred_cancel() function, introduced in commit a646e99cb90 (Hexagon macros) doesn't use the 'one' TCG temporary; remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211003004750.3608983-2-f4bug@amsat.org>
| * Hexagon (target/hexagon) probe the stores in a packet at start of commitTaylor Simpson2021-10-065-3/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a packet has 2 stores, either both commit or neither commit. At the beginning of gen_commit_packet, we check for multiple stores. If there are multiple stores, call a helper that will probe each of them before proceeding with the commit. Note that we don't call the probe helper for packets with only one store. Therefore, we call process_store_log before anything else involved in committing the packet. We also fix a typo in the comment in process_store_log. Test case added in tests/tcg/hexagon/hex_sigsegv.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1633036599-7637-1-git-send-email-tsimpson@quicinc.com>
* | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211006' into stagingRichard Henderson2021-10-0644-610/+1445
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More fixes for fedora-i386-cross Add dup_const_tl Expand MemOp MO_SIZE Move MemOpIdx out of tcg.h Vector support for tcg/s390x # gpg: Signature made Wed 06 Oct 2021 08:12:53 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-tcg-20211006: (28 commits) tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec tcg/s390x: Implement TCG_TARGET_HAS_sat_vec tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec tcg/s390x: Implement vector shift operations tcg/s390x: Implement TCG_TARGET_HAS_mul_vec tcg/s390x: Implement andc, orc, abs, neg, not vector operations tcg/s390x: Implement minimal vector operations tcg/s390x: Implement tcg_out_dup*_vec tcg/s390x: Implement tcg_out_mov for vector types tcg/s390x: Implement tcg_out_ld/st for vector types tcg/s390x: Add host vector framework tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg tcg/s390x: Change FACILITY representation tcg/s390x: Rename from tcg/s390 tcg: Expand usadd/ussub with umin/umax hw/core/cpu: Re-sort the non-pointers to the end of CPUClass trace: Split guest_mem_before plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb accel/tcg: Pass MemOpIdx to atomic_trace_*_post ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vecRichard Henderson2021-10-061-1/+23
| | | | | | | | | | | | | | | | | | This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson2021-10-063-1/+22
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2021-10-062-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2021-10-062-1/+26
| | | | | | | | | | | | | | | Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement vector shift operationsRichard Henderson2021-10-063-7/+99
| | | | | | | | | | | | | | | Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement TCG_TARGET_HAS_mul_vecRichard Henderson2021-10-062-1/+8
| | | | | | | | | | | | | | | Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement andc, orc, abs, neg, not vector operationsRichard Henderson2021-10-063-5/+39
| | | | | | | | | | | | | | | | | | | | | These logical and arithmetic operations are optional but trivial. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement minimal vector operationsRichard Henderson2021-10-061-4/+150
| | | | | | | | | | | | | | | | | | | | | | | | Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement tcg_out_dup*_vecRichard Henderson2021-10-061-3/+119
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement tcg_out_mov for vector typesRichard Henderson2021-10-061-4/+68
| | | | | | | | | | | | | | | Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement tcg_out_ld/st for vector typesRichard Henderson2021-10-061-12/+120
| | | | | | | | | | | | | | | Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Add host vector frameworkRichard Henderson2021-10-065-5/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGRegRichard Henderson2021-10-061-21/+7Star
| | | | | | | | | | | | | | | | | | | | | They are rightly values in the same enumeration. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Change FACILITY representationRichard Henderson2021-10-062-51/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Change name to HAVE_FACILITY (david)
| * | tcg/s390x: Rename from tcg/s390Richard Henderson2021-10-065-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Expand usadd/ussub with umin/umaxRichard Henderson2021-10-061-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For usadd, we only have to consider overflow. Since ~B + B == -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw/core/cpu: Re-sort the non-pointers to the end of CPUClassRichard Henderson2021-10-061-4/+7
| | | | | | | | | | | | | | | | | | | | | Despite the comment, the members were not kept at the end. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | trace: Split guest_mem_beforeRichard Henderson2021-10-067-122/+28Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in encoding load/store within a bit of the memory trace info operand. Represent atomic operations as a single read-modify-write tracepoint. Use MemOpIdx instead of inventing a form specifically for traces. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-06-18 16:12:17 +0200