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* gitlab-ci.yml: Run check-tcg with TCIThomas Huth2021-02-191-3/+3
| | | | | | | It's now possible to also run the non-x86 TCG tests with TCI. Message-Id: <20210127055903.40148-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/qtest/boot-sector: Check that the guest did not panicThomas Huth2021-02-191-0/+9
| | | | | | | | | | | | The s390-ccw bios code panics if it can not boot successfully. In this case, it does not make sense that we wait the full 600 seconds for the boot sector test to finish and can signal the failure immediately, thus let's check the status of the guest with the "query-status" QMP command here, too. Reported-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210212113141.854871-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* gitlab-ci: Disable vhost-kernel in build-disable jobPhilippe Mathieu-Daudé2021-02-191-0/+1
| | | | | | | | | | | Commit 299e6f19b3e ("vhost-net: revamp configure logic") added the --enable-vhost-kernel option. Disable it in the build-disable job. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20210131104621.221602-1-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* scripts/checkpatch: Improve the check for authors mangled by the mailing listThomas Huth2021-02-191-1/+1
| | | | | | | | | | | | | | | | | There were recently some patches on the list which had their "From:" line mangled like this: From: qemu_oss--- via <qemu-devel@nongnu.org> Since our test in the checkpatch.pl script did not trigger here, the patches finally also ended up in a pull request, with the wrong author set. So let's improve the regular expression to also complain on these new patterns, too. Message-Id: <20210216071512.1199827-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* gitlab-ci: Display Avocado log content when tests timeoutPhilippe Mathieu-Daudé2021-02-191-1/+1
| | | | | | | | | | | | | | | | | | | Since commit ba2232bae6d ("gitlab-ci: Refactor code that show logs of failed acceptances") we display the log content of failing tests (Avocado "FAIL" event). Since we are also interested in tests timeouting, update our global Avocado config to display log content for the "INTERRUPT" event, "possible when the timeout is reached" (See [*]). [*] https://avocado-framework.readthedocs.io/en/latest/guides/writer/chapters/writing.html#test-statuses Suggested-by: Willian Rampazzo <willianr@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20210215171438.935665-1-philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* gitlab: fix inconsistent indentationDaniel P. Berrangé2021-02-191-8/+8
| | | | | | | | | The standard is to use 2 space indent, not 3. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210216132954.295906-4-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* gitlab: add fine grained job deps for all build jobsDaniel P. Berrangé2021-02-192-0/+104
| | | | | | | | | | | This allows the build jobs to start running as soon as their respective container image is ready, instead of waiting for all container builds to finish. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210216132954.295906-3-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* gitlab: always build container imagesDaniel P. Berrangé2021-02-191-7/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we attempt to skip building container images if the commits do not involve changes to the dockerfiles or gitlab CI definitions. Conceptually this makes sense, but there is a challenge in the real world implementation of this in gitlab. In the case of a CI pipeline triggered from a merge request, GitLab knows the common ancestor of the merge request and the main git repo, so it can trivially determine if any of the commits associated with the MR change the dockerfiles. In the case of a CI pipeline triggered from a push to a branch, it is much more difficult. There is no concept of a common ancestor in this case. Instead GitLab looks at the set of commits in the git push event. On the surface this may sound reasonable, but it doesn't take into account that a push event does not always contain the full set of patches from a branch. For example, consider pushing 5 commits, one of which contains a dockerfile change. This will trigger a CI pipeline for the containers. Now consider you do some more work on the branch and push 3 further commits, so you now have a branch of 8 commits. For the second push GitLab will only look at the 3 most recent commits, the other 5 were already present. Thus GitLab will not realize that the branch has dockerfile changes that need to trigger the container build. This can cause real world problems: - Push 5 commits to branch "foo", including a dockerfile change => rebuilds the container images with content from "foo" => build jobs runs against containers from "foo" - Refresh your master branch with latest upstream master => rebuilds the container images with content from "master" => build jobs runs against containers from "master" - Push 3 more commits to branch "foo", with no dockerfile change => no container rebuild triggers => build jobs runs against containers from "master" The "changes" conditional in gitlab is OK, *provided* your build jobs are not relying on any external state from previous builds. This is NOT the case in QEMU, because we are building container images and these are cached. This is a scenario in which the "changes" conditional is not usuable. The only other way to avoid this problem would be to use the git branch name as the container image tag, instead of always using "latest". The downside of this approach is that the user's gitlab registry will grow significantly until it starts to trigger GitLab's automatic deletion policy. Every time the user starts a new branch they will have to trigger a rebuild of the container images. Given this, we might as well just drop the conditional and always build the container images. Most of the time docker will be able to use the layer cache to avoid the most expensive part of the rebuild process (installing all the RPMs/debs/etc) Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20210216132954.295906-2-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/qtest/boot-serial-test: Test Virt machine with 'max'Philippe Mathieu-Daudé2021-02-191-1/+1
| | | | | | | | | | | | | | | | When using KVM, using a specific cpu type will only work if the host CPU really is that exact CPU type. During testing we can simply use the 'max' CPU which will select all the features available from the host. This allow running this test on a Cavium CN8890 (ThunderX cores). Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210205144345.2068758-4-f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210218' ↵Peter Maydell2021-02-18102-2/+23183
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Initial commit for the Qualcomm Hexagon processor. # gpg: Signature made Thu 18 Feb 2021 16:26:52 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-hex-20210218: (35 commits) Hexagon build infrastructure Hexagon (tests/tcg/hexagon) TCG tests - floating point Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc Hexagon (tests/tcg/hexagon) TCG tests - multiarch Hexagon (linux-user/hexagon) Linux user emulation Hexagon (target/hexagon) translation Hexagon (target/hexagon) TCG for floating point instructions Hexagon (target/hexagon) TCG for instructions with multiple definitions Hexagon (target/hexagon) TCG generation Hexagon (target/hexagon) instruction classes Hexagon (target/hexagon) macros Hexagon (target/hexagon) opcode data structures Hexagon (target/hexagon) generater phase 4 - decode tree Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Hexagon (target/hexagon) generator phase 2 - generate header files Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Hexagon (target/hexagon/imported) arch import Hexagon (target/hexagon/fma_emu.[ch]) utility functions Hexagon (target/hexagon/conv_emu.[ch]) utility functions Hexagon (target/hexagon/arch.[ch]) utility functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Hexagon build infrastructureTaylor Simpson2021-02-185-1/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add file to default-configs Add hexagon to meson.build Add hexagon to target/meson.build Add target/hexagon/meson.build Change scripts/qemu-binfmt-conf.sh We can build a hexagon-linux-user target and run programs on the Hexagon scalar core. With hexagon-linux-clang installed, "make check-tcg" will pass. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-35-git-send-email-tsimpson@quicinc.com> [rth: Use top-level python variable] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (tests/tcg/hexagon) TCG tests - floating pointTaylor Simpson2021-02-182-0/+371
| | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-34-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/miscTaylor Simpson2021-02-187-0/+1147
| | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-33-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (tests/tcg/hexagon) TCG tests - multiarchTaylor Simpson2021-02-184-1/+1549
| | | | | | | | | | | | | | | | | | | | | | | | Enable multiarch tests for Hexagon Modify tests/tcg/configure.sh Add reference files to tests/tcg/hexagon Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-32-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (linux-user/hexagon) Linux user emulationTaylor Simpson2021-02-1815-0/+1012
| | | | | | | | | | | | | | | | | | | | | | | | Implementation of Linux user emulation for Hexagon Some common files modified in addition to new files in linux-user/hexagon Acked-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-31-git-send-email-tsimpson@quicinc.com> [rth: Fix termbits.h on review by Laurent] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) translationTaylor Simpson2021-02-182-0/+841
| | | | | | | | | | | | | | | | | | | | | | | | Read the instruction memory Create a packet data structure Generate TCG code for the start of the packet Invoke the generate function for each instruction Generate TCG code for the end of the packet Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-30-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) TCG for floating point instructionsTaylor Simpson2021-02-181-0/+121
| | | | | | | | | | | | | | | | | | | | The imported code uses host floating point. We override them to use qemu softfloat Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-29-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) TCG for instructions with multiple definitionsTaylor Simpson2021-02-181-0/+198
| | | | | | | | | | | | | | | | | | Helpers won't work if there are multiple definitions, so we override these instructions using #define fGEN_TCG_<tag>. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-28-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) TCG generationTaylor Simpson2021-02-182-0/+356
| | | | | | | | | | | | | | | | Include the generated files and set up the data structures Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-27-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) instruction classesTaylor Simpson2021-02-183-0/+174
| | | | | | | | | | | | | | | | | | Determine legal VLIW slots for each instruction Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-26-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) macrosTaylor Simpson2021-02-181-0/+592
| | | | | | | | | | | | | | | | | | | | macros to interface with the generator macros referenced in instruction semantics Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-25-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) opcode data structuresTaylor Simpson2021-02-182-0/+200
| | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-24-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) generater phase 4 - decode treeTaylor Simpson2021-02-181-0/+351
| | | | | | | | | | | | | | | | | | Python script that emits the decode tree in dectree_generated.h. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-23-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode treeTaylor Simpson2021-02-181-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | Run the C preprocessor across the instruction definition and encoding files to expand macros and prepare the iset.py file. The resulting fill contains python data structures used to build the decode tree. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-22-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) generator phase 2 - generate header filesTaylor Simpson2021-02-1810-0/+1565
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Python scripts generate the following files helper_protos_generated.h.inc For each instruction we create DEF_HELPER function prototype helper_funcs_generated.c.inc For each instruction we create the helper function definition tcg_funcs_generated.c.inc For each instruction we create TCG code to generate call to helper tcg_func_table_generated.c.inc Table of function pointers indexed by opcode shortcode_generated.h.inc Generate a table of instruction "shortcode" semantics opcodes_def_generated.h.inc Gives a list of all the opcodes op_attribs_generated.h.inc Lists all the attributes associated with each instruction op_regs_generated.h.inc Lists the register and immediate operands for each instruction printinsn_generated.h.inc Data for printing (disassembling) each instruction (format string + operands) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-21-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) generator phase 1 - C preprocessor for semanticsTaylor Simpson2021-02-181-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Run the C preprocessor across the instruction definition files and macro definition file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each macro. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-20-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon/imported) arch importTaylor Simpson2021-02-1814-0/+9236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Imported from the Hexagon architecture library imported/macros.def The macro definitions specify instruction attributes that are applied to each instruction that references the macro. The generator will recursively apply attributes to each instruction that used the macro. imported/allidefs.def Top level instruction definition file imported/*.idef Instruction definition files These files are input to the first phase of the generator (gen_semantics.c) to create a python include file with the instruction semantics and attributes. The python include file is fed to the second phase to generate various header files. imported/encode*.def Instruction encoding bit patterns for every instruction Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-19-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon/fma_emu.[ch]) utility functionsTaylor Simpson2021-02-182-0/+738
| | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-18-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon/conv_emu.[ch]) utility functionsTaylor Simpson2021-02-182-0/+208
| | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-17-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon/arch.[ch]) utility functionsTaylor Simpson2021-02-182-0/+334
| | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-16-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) instruction printingTaylor Simpson2021-02-182-0/+173
| | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-15-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) instruction/packet decodeTaylor Simpson2021-02-182-0/+989
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate subinsn's into two instructions Break compare-jumps into two instructions Create instructions for :endloop Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-14-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) instruction attributesTaylor Simpson2021-02-182-0/+132
| | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-13-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) register fieldsTaylor Simpson2021-02-183-0/+104
| | | | | | | | | | | | | | | | | | Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-12-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) instruction and packet typesTaylor Simpson2021-02-181-0/+74
| | | | | | | | | | | | | | | | | | | | The insn_t and packet_t are the interface between instruction decoding and TCG code generation Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-11-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) architecture typesTaylor Simpson2021-02-181-0/+38
| | | | | | | | | | | | | | | | | | | | Define types used in files imported from the Hexagon architecture library Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-10-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) GDB StubTaylor Simpson2021-02-182-0/+49
| | | | | | | | | | | | | | | | | | | | GDB register read and write routines Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-9-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) scalar core helpersTaylor Simpson2021-02-182-0/+1152
| | | | | | | | | | | | | | | | | | The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-8-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) register namesTaylor Simpson2021-02-181-0/+83
| | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-7-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (disas) disassemblerTaylor Simpson2021-02-183-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | Add hexagon to disas/meson.build Add disas/hexagon.c Add hexagon to include/disas/dis-asm.h Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-6-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) scalar core definitionTaylor Simpson2021-02-185-0/+599
| | | | | | | | | | | | | | | | Add target state header, target definitions and initialization routines Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-5-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (include/elf.h) ELF machine definitionTaylor Simpson2021-02-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | Define EM_HEXAGON 164 Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-4-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon (target/hexagon) READMETaylor Simpson2021-02-181-0/+235
| | | | | | | | | | | | | | | | Gives an introduction and overview to the Hexagon target Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-3-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon Update MAINTAINERS fileTaylor Simpson2021-02-181-0/+9
| | | | | | | | | | | | | | | | | | Add Taylor Simpson as the Hexagon target maintainer Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-2-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * qemu/int128: Add int128_orRichard Henderson2021-02-181-0/+10
| | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201021045149.1582203-2-richard.henderson@linaro.org>
* | Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210218-pull-request' ↵Peter Maydell2021-02-182-3/+17
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging usb: two bugfixes. # gpg: Signature made Thu 18 Feb 2021 11:51:44 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20210218-pull-request: usb/pcap: set flag_setup usb-host: use correct altsetting in usb_host_ep_update Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * usb/pcap: set flag_setupGerd Hoffmann2021-02-171-0/+2
| | | | | | | | | | | | | | | | | | Without that wireshark complains about invalid control setup data for non-control transfers. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210216144939.841873-1-kraxel@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * usb-host: use correct altsetting in usb_host_ep_updateNick Rosbrook2021-02-171-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to keep track of the alternate setting that should be used for a given interface, the USBDevice struct keeps an array of alternate setting values, which is indexed by the interface number. In usb_host_set_interface, when this array is updated, usb_host_ep_update is called as a result. However, when usb_host_ep_update accesses the active libusb_config_descriptor, it indexes udev->altsetting with the loop variable, rather than the interface number. With the simple trace backend enable, this behavior can be seen: [...] usb_xhci_xfer_start 0.440 pid=1215 xfer=0x5596a4b85930 slotid=0x1 epid=0x1 streamid=0x0 usb_packet_state_change 1.703 pid=1215 bus=0x1 port=b'1' ep=0x0 p=0x5596a4b85938 o=b'undef' n=b'setup' usb_host_req_control 2.269 pid=1215 bus=0x1 addr=0x5 p=0x5596a4b85938 req=0x10b value=0x1 index=0xd usb_host_set_interface 0.449 pid=1215 bus=0x1 addr=0x5 interface=0xd alt=0x1 usb_host_parse_config 2542.648 pid=1215 bus=0x1 addr=0x5 value=0x2 active=0x1 usb_host_parse_interface 1.804 pid=1215 bus=0x1 addr=0x5 num=0xc alt=0x0 active=0x1 usb_host_parse_endpoint 2.012 pid=1215 bus=0x1 addr=0x5 ep=0x2 dir=b'in' type=b'int' active=0x1 usb_host_parse_interface 1.598 pid=1215 bus=0x1 addr=0x5 num=0xd alt=0x0 active=0x1 usb_host_req_emulated 3.593 pid=1215 bus=0x1 addr=0x5 p=0x5596a4b85938 status=0x0 usb_packet_state_change 2.550 pid=1215 bus=0x1 port=b'1' ep=0x0 p=0x5596a4b85938 o=b'setup' n=b'complete' usb_xhci_xfer_success 4.298 pid=1215 xfer=0x5596a4b85930 bytes=0x0 [...] In particular, it is seen that although usb_host_set_interface sets the alternate setting of interface 0xd to 0x1, usb_host_ep_update uses 0x0 as the alternate setting due to using the incorrect index to udev->altsetting. Fix this problem by getting the interface number from the active libusb_config_descriptor, and then using that as the index to udev->altsetting. Signed-off-by: Nick Rosbrook <rosbrookn@ainfosec.com> Message-Id: <20210201213021.500277-1-rosbrookn@ainfosec.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2021-02-1836-215/+769
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/stsquad/tags/pull-plugin-updates-180221-1' into staging Plugin updates: - expose vdev name in PCI memory registration - new hwprofile plugin - bunch of style cleanups to contrib/plugins - fix call signature of inline instrumentation - re-factor the io_recompile code to push specialisation into hooks - add some acceptance tests for the plugins - clean-up and remove CF_NOCACHE handling from TCG - fix instrumentation of cpu_io_recompile sections - expand tests to check inline and cb count the same # gpg: Signature made Thu 18 Feb 2021 08:24:57 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-plugin-updates-180221-1: (23 commits) tests/acceptance: add a memory callback check tests/plugin: allow memory plugin to do both inline and callbacks tests/acceptance: add a new tests to detect counting errors accel/tcg: allow plugin instrumentation to be disable via cflags accel/tcg: remove CF_NOCACHE and special cases accel/tcg: re-factor non-RAM execution code accel/tcg: cache single instruction TB on pending replay exception accel/tcg: actually cache our partial icount TB tests/acceptance: add a new set of tests to exercise plugins tests/plugin: expand insn test to detect duplicate instructions target/sh4: Create superh_io_recompile_replay_branch target/mips: Create mips_io_recompile_replay_branch accel/tcg: Create io_recompile_replay_branch hook exec: Move TranslationBlock typedef to qemu/typedefs.h accel/tcg/plugin-gen: fix the call signature for inline callbacks contrib: Open brace '{' following struct go on the same line contrib: space required after that ',' contrib: Add spaces around operator contrib: Fix some code style problems, ERROR: "foo * bar" should be "foo *bar" contrib: Don't use '#' flag of printf format ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/acceptance: add a memory callback checkAlex Bennée2021-02-181-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | This test makes sure that the inline and callback based memory checks count the same number of accesses. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-24-alex.bennee@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-09 09:45:06 +0100