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| * | Hexagon (target/hexagon) opcode data structuresTaylor Simpson2021-02-182-0/+200
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-24-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) generater phase 4 - decode treeTaylor Simpson2021-02-181-0/+351
| | | | | | | | | | | | | | | | | | | | | | | | | | | Python script that emits the decode tree in dectree_generated.h. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-23-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode treeTaylor Simpson2021-02-181-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Run the C preprocessor across the instruction definition and encoding files to expand macros and prepare the iset.py file. The resulting fill contains python data structures used to build the decode tree. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-22-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) generator phase 2 - generate header filesTaylor Simpson2021-02-1810-0/+1565
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Python scripts generate the following files helper_protos_generated.h.inc For each instruction we create DEF_HELPER function prototype helper_funcs_generated.c.inc For each instruction we create the helper function definition tcg_funcs_generated.c.inc For each instruction we create TCG code to generate call to helper tcg_func_table_generated.c.inc Table of function pointers indexed by opcode shortcode_generated.h.inc Generate a table of instruction "shortcode" semantics opcodes_def_generated.h.inc Gives a list of all the opcodes op_attribs_generated.h.inc Lists all the attributes associated with each instruction op_regs_generated.h.inc Lists the register and immediate operands for each instruction printinsn_generated.h.inc Data for printing (disassembling) each instruction (format string + operands) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-21-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) generator phase 1 - C preprocessor for semanticsTaylor Simpson2021-02-181-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Run the C preprocessor across the instruction definition files and macro definition file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each macro. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-20-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon/imported) arch importTaylor Simpson2021-02-1814-0/+9236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Imported from the Hexagon architecture library imported/macros.def The macro definitions specify instruction attributes that are applied to each instruction that references the macro. The generator will recursively apply attributes to each instruction that used the macro. imported/allidefs.def Top level instruction definition file imported/*.idef Instruction definition files These files are input to the first phase of the generator (gen_semantics.c) to create a python include file with the instruction semantics and attributes. The python include file is fed to the second phase to generate various header files. imported/encode*.def Instruction encoding bit patterns for every instruction Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-19-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon/fma_emu.[ch]) utility functionsTaylor Simpson2021-02-182-0/+738
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-18-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon/conv_emu.[ch]) utility functionsTaylor Simpson2021-02-182-0/+208
| | | | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-17-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon/arch.[ch]) utility functionsTaylor Simpson2021-02-182-0/+334
| | | | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-16-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) instruction printingTaylor Simpson2021-02-182-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-15-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) instruction/packet decodeTaylor Simpson2021-02-182-0/+989
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate subinsn's into two instructions Break compare-jumps into two instructions Create instructions for :endloop Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-14-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) instruction attributesTaylor Simpson2021-02-182-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-13-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) register fieldsTaylor Simpson2021-02-183-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-12-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) instruction and packet typesTaylor Simpson2021-02-181-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The insn_t and packet_t are the interface between instruction decoding and TCG code generation Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-11-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) architecture typesTaylor Simpson2021-02-181-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define types used in files imported from the Hexagon architecture library Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-10-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) GDB StubTaylor Simpson2021-02-182-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GDB register read and write routines Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-9-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) scalar core helpersTaylor Simpson2021-02-182-0/+1152
| | | | | | | | | | | | | | | | | | | | | | | | | | | The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-8-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) register namesTaylor Simpson2021-02-181-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-7-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (disas) disassemblerTaylor Simpson2021-02-183-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add hexagon to disas/meson.build Add disas/hexagon.c Add hexagon to include/disas/dis-asm.h Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-6-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) scalar core definitionTaylor Simpson2021-02-185-0/+599
| | | | | | | | | | | | | | | | | | | | | | | | Add target state header, target definitions and initialization routines Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-5-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (include/elf.h) ELF machine definitionTaylor Simpson2021-02-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define EM_HEXAGON 164 Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-4-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon (target/hexagon) READMETaylor Simpson2021-02-181-0/+235
| | | | | | | | | | | | | | | | | | | | | | | | Gives an introduction and overview to the Hexagon target Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-3-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Hexagon Update MAINTAINERS fileTaylor Simpson2021-02-181-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Taylor Simpson as the Hexagon target maintainer Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-2-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | qemu/int128: Add int128_orRichard Henderson2021-02-181-0/+10
| |/ | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201021045149.1582203-2-richard.henderson@linaro.org>
* | Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210218-pull-request' ↵Peter Maydell2021-02-182-3/+17
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging usb: two bugfixes. # gpg: Signature made Thu 18 Feb 2021 11:51:44 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20210218-pull-request: usb/pcap: set flag_setup usb-host: use correct altsetting in usb_host_ep_update Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * usb/pcap: set flag_setupGerd Hoffmann2021-02-171-0/+2
| | | | | | | | | | | | | | | | | | Without that wireshark complains about invalid control setup data for non-control transfers. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20210216144939.841873-1-kraxel@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * usb-host: use correct altsetting in usb_host_ep_updateNick Rosbrook2021-02-171-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to keep track of the alternate setting that should be used for a given interface, the USBDevice struct keeps an array of alternate setting values, which is indexed by the interface number. In usb_host_set_interface, when this array is updated, usb_host_ep_update is called as a result. However, when usb_host_ep_update accesses the active libusb_config_descriptor, it indexes udev->altsetting with the loop variable, rather than the interface number. With the simple trace backend enable, this behavior can be seen: [...] usb_xhci_xfer_start 0.440 pid=1215 xfer=0x5596a4b85930 slotid=0x1 epid=0x1 streamid=0x0 usb_packet_state_change 1.703 pid=1215 bus=0x1 port=b'1' ep=0x0 p=0x5596a4b85938 o=b'undef' n=b'setup' usb_host_req_control 2.269 pid=1215 bus=0x1 addr=0x5 p=0x5596a4b85938 req=0x10b value=0x1 index=0xd usb_host_set_interface 0.449 pid=1215 bus=0x1 addr=0x5 interface=0xd alt=0x1 usb_host_parse_config 2542.648 pid=1215 bus=0x1 addr=0x5 value=0x2 active=0x1 usb_host_parse_interface 1.804 pid=1215 bus=0x1 addr=0x5 num=0xc alt=0x0 active=0x1 usb_host_parse_endpoint 2.012 pid=1215 bus=0x1 addr=0x5 ep=0x2 dir=b'in' type=b'int' active=0x1 usb_host_parse_interface 1.598 pid=1215 bus=0x1 addr=0x5 num=0xd alt=0x0 active=0x1 usb_host_req_emulated 3.593 pid=1215 bus=0x1 addr=0x5 p=0x5596a4b85938 status=0x0 usb_packet_state_change 2.550 pid=1215 bus=0x1 port=b'1' ep=0x0 p=0x5596a4b85938 o=b'setup' n=b'complete' usb_xhci_xfer_success 4.298 pid=1215 xfer=0x5596a4b85930 bytes=0x0 [...] In particular, it is seen that although usb_host_set_interface sets the alternate setting of interface 0xd to 0x1, usb_host_ep_update uses 0x0 as the alternate setting due to using the incorrect index to udev->altsetting. Fix this problem by getting the interface number from the active libusb_config_descriptor, and then using that as the index to udev->altsetting. Signed-off-by: Nick Rosbrook <rosbrookn@ainfosec.com> Message-Id: <20210201213021.500277-1-rosbrookn@ainfosec.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2021-02-1836-215/+769
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/stsquad/tags/pull-plugin-updates-180221-1' into staging Plugin updates: - expose vdev name in PCI memory registration - new hwprofile plugin - bunch of style cleanups to contrib/plugins - fix call signature of inline instrumentation - re-factor the io_recompile code to push specialisation into hooks - add some acceptance tests for the plugins - clean-up and remove CF_NOCACHE handling from TCG - fix instrumentation of cpu_io_recompile sections - expand tests to check inline and cb count the same # gpg: Signature made Thu 18 Feb 2021 08:24:57 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-plugin-updates-180221-1: (23 commits) tests/acceptance: add a memory callback check tests/plugin: allow memory plugin to do both inline and callbacks tests/acceptance: add a new tests to detect counting errors accel/tcg: allow plugin instrumentation to be disable via cflags accel/tcg: remove CF_NOCACHE and special cases accel/tcg: re-factor non-RAM execution code accel/tcg: cache single instruction TB on pending replay exception accel/tcg: actually cache our partial icount TB tests/acceptance: add a new set of tests to exercise plugins tests/plugin: expand insn test to detect duplicate instructions target/sh4: Create superh_io_recompile_replay_branch target/mips: Create mips_io_recompile_replay_branch accel/tcg: Create io_recompile_replay_branch hook exec: Move TranslationBlock typedef to qemu/typedefs.h accel/tcg/plugin-gen: fix the call signature for inline callbacks contrib: Open brace '{' following struct go on the same line contrib: space required after that ',' contrib: Add spaces around operator contrib: Fix some code style problems, ERROR: "foo * bar" should be "foo *bar" contrib: Don't use '#' flag of printf format ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/acceptance: add a memory callback checkAlex Bennée2021-02-181-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | This test makes sure that the inline and callback based memory checks count the same number of accesses. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-24-alex.bennee@linaro.org>
| * | tests/plugin: allow memory plugin to do both inline and callbacksAlex Bennée2021-02-181-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is going to be useful for acceptance tests that check both types are being called the same number of times, especially when icount is enabled. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-23-alex.bennee@linaro.org>
| * | tests/acceptance: add a new tests to detect counting errorsAlex Bennée2021-02-181-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The insn plugin has a simple heuristic to detect if an instruction is detected running twice in a row. Check the plugin log after the run and pass accordingly. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-22-alex.bennee@linaro.org>
| * | accel/tcg: allow plugin instrumentation to be disable via cflagsAlex Bennée2021-02-187-27/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When icount is enabled and we recompile an MMIO access we end up double counting the instruction execution. To avoid this we introduce the CF_MEMI cflag which only allows memory instrumentation for the next TB (which won't yet have been counted). As this is part of the hashed compile flags we will only execute the generated TB while coming out of a cpu_io_recompile. While we are at it delete the old TODO. We might as well keep the translation handy as it's likely you will repeatedly hit it on each MMIO access. Reported-by: Aaron Lindsay <aaron@os.amperecomputing.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-21-alex.bennee@linaro.org>
| * | accel/tcg: remove CF_NOCACHE and special casesAlex Bennée2021-02-182-39/+15Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we no longer generate CF_NOCACHE blocks we can remove a bunch of the special case handling for them. While we are at it we can remove the unused tb->orig_tb field and save a few bytes on the TB structure. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-20-alex.bennee@linaro.org>
| * | accel/tcg: re-factor non-RAM execution codeAlex Bennée2021-02-181-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no real need to use CF_NOCACHE here. As long as the TB isn't linked to other TBs or included in the QHT or jump cache then it will only get executed once. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-19-alex.bennee@linaro.org>
| * | accel/tcg: cache single instruction TB on pending replay exceptionAlex Bennée2021-02-181-40/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Again there is no reason to jump through the nocache hoops to execute a single instruction block. We do have to add an additional wrinkle to the cpu_handle_interrupt case to ensure we let through a TB where we have specifically disabled icount for the block. As the last user of cpu_exec_nocache we can now remove the function. Further clean-up will follow in subsequent patches. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-18-alex.bennee@linaro.org>
| * | accel/tcg: actually cache our partial icount TBAlex Bennée2021-02-181-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we exit a block under icount with instructions left to execute we might need a shorter than normal block to take us to the next deterministic event. Instead of creating a throwaway block on demand we use the existing compile flags mechanism to ensure we fetch (or compile and fetch) a block with exactly the number of instructions we need. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-17-alex.bennee@linaro.org>
| * | tests/acceptance: add a new set of tests to exercise pluginsAlex Bennée2021-02-182-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is just a simple test to count the instructions executed by a kernel. However a later test will detect a failure condition when icount is enabled. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-16-alex.bennee@linaro.org>
| * | tests/plugin: expand insn test to detect duplicate instructionsAlex Bennée2021-02-184-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A duplicate insn is one that is appears to be executed twice in a row. This is currently possible due to -icount and cpu_io_recompile() causing a re-translation of a block. On it's own this won't trigger any tests though. The heuristics that the plugin use can't deal with the x86 rep instruction which (validly) will look like executing the same instruction several times. To avoid problems later we tweak the rules for x86 to run the "inline" version of the plugin. This also has the advantage of increasing coverage of the plugin code (see bugfix in previous commit). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-15-alex.bennee@linaro.org>
| * | target/sh4: Create superh_io_recompile_replay_branchRichard Henderson2021-02-182-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the code from accel/tcg/translate-all.c to target/sh4/cpu.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-5-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-14-alex.bennee@linaro.org>
| * | target/mips: Create mips_io_recompile_replay_branchRichard Henderson2021-02-182-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the code from accel/tcg/translate-all.c to target/mips/cpu.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-4-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-13-alex.bennee@linaro.org>
| * | accel/tcg: Create io_recompile_replay_branch hookRichard Henderson2021-02-182-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a hook in which to split out the mips and sh4 ifdefs from cpu_io_recompile. [AJB: s/stoped/stopped/] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-3-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-12-alex.bennee@linaro.org>
| * | exec: Move TranslationBlock typedef to qemu/typedefs.hRichard Henderson2021-02-189-12/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This also means we don't need an extra declaration of the structure in hw/core/cpu.h. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210208233906.479571-2-richard.henderson@linaro.org> Message-Id: <20210213130325.14781-11-alex.bennee@linaro.org>
| * | accel/tcg/plugin-gen: fix the call signature for inline callbacksAlex Bennée2021-02-181-21/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent change to the handling of constants in TCG changed the pattern of ops emitted for a constant add. We no longer emit a mov and the constant can be applied directly to the TCG_op_add arguments. This was causing SEGVs when running the insn plugin with arg=inline. Fix this by updating copy_add_i64 to do the right thing while also adding a comment at the top of the append section as an aide memoir if something like this happens again. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Emilio G. Cota <cota@braap.org> Message-Id: <20210213130325.14781-10-alex.bennee@linaro.org>
| * | contrib: Open brace '{' following struct go on the same linezhouyang2021-02-181-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I found some style problems whil check the code using checkpatch.pl. This commit fixs the issue below: ERROR: that open brace { should be on the previous line Signed-off-by: zhouyang <zhouyang789@huawei.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210118031004.1662363-6-zhouyang789@huawei.com> Message-Id: <20210213130325.14781-9-alex.bennee@linaro.org>
| * | contrib: space required after that ','zhouyang2021-02-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I am reading contrib related code and found some style problems while check the code using checkpatch.pl. This commit fixs the issue below: ERROR: space required after that ',' Signed-off-by: zhouyang <zhouyang789@huawei.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210118031004.1662363-5-zhouyang789@huawei.com> Message-Id: <20210213130325.14781-8-alex.bennee@linaro.org>
| * | contrib: Add spaces around operatorzhouyang2021-02-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I am reading contrib related code and found some style problems while check the code using checkpatch.pl. This commit fixs the issue below: ERROR: spaces required around that '*' Signed-off-by: zhouyang <zhouyang789@huawei.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210118031004.1662363-4-zhouyang789@huawei.com> Message-Id: <20210213130325.14781-7-alex.bennee@linaro.org>
| * | contrib: Fix some code style problems, ERROR: "foo * bar" should be "foo *bar"zhouyang2021-02-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I am reading contrib related code and found some style problems while check the code using checkpatch.pl. This commit fixs the issue below: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: zhouyang <zhouyang789@huawei.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210118031004.1662363-3-zhouyang789@huawei.com> Message-Id: <20210213130325.14781-6-alex.bennee@linaro.org>
| * | contrib: Don't use '#' flag of printf formatzhouyang2021-02-184-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I am reading contrib related code and found some style problems while check the code using checkpatch.pl. This commit fixs the misuse of '#' flag of printf format Signed-off-by: zhouyang <zhouyang789@huawei.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210118031004.1662363-2-zhouyang789@huawei.com> Message-Id: <20210213130325.14781-5-alex.bennee@linaro.org>
| * | plugins: new hwprofile pluginAlex Bennée2021-02-183-0/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a plugin intended to help with profiling access to various bits of system hardware. It only really makes sense for system emulation. It takes advantage of the recently exposed helper API that allows us to see the device name (memory region name) associated with a device. You can specify arg=read or arg=write to limit the tracking to just reads or writes (by default it does both). The pattern option: -plugin ./tests/plugin/libhwprofile.so,arg=pattern will allow you to see the access pattern to devices, eg: gic_cpu @ 0xffffffc010040000 off:00000000, 8, 1, 8, 1 off:00000000, 4, 1, 4, 1 off:00000000, 2, 1, 2, 1 off:00000000, 1, 1, 1, 1 The source option: -plugin ./tests/plugin/libhwprofile.so,arg=source will track the virtual source address of the instruction making the access: pl011 @ 0xffffffc010031000 pc:ffffffc0104c785c, 1, 4, 0, 0 pc:ffffffc0104c7898, 1, 4, 0, 0 pc:ffffffc010512bcc, 2, 1867, 0, 0 You cannot mix source and pattern. Finally the match option allow you to limit the tracking to just the devices you care about. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Robert Foley <robert.foley@linaro.org> Reviewed-by: Robert Foley <robert.foley@linaro.org> Message-Id: <20210213130325.14781-4-alex.bennee@linaro.org>
| * | plugins: add API to return a name for a IO deviceAlex Bennée2021-02-182-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This may well end up being anonymous but it should always be unique. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Clement Deschamps <clement.deschamps@greensocs.com> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-3-alex.bennee@linaro.org>
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