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| * | python/machine.py: fix _popen accessJohn Snow2020-10-201-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As always, Optional[T] causes problems with unchecked access. Add a helper that asserts the pipe is present before we attempt to talk with it. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20201006235817.3280413-9-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | python/machine.py: Add _qmp access shimJohn Snow2020-10-201-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like many other Optional[] types, it's not always a given that this object will be set. Wrap it in a type-shim that raises a meaningful error and will always return a concrete type. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20201006235817.3280413-8-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | python/machine.py: use qmp.commandJohn Snow2020-10-201-12/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | machine.py and qmp.py both do the same thing here; refactor machine.py to use qmp.py's functionality more directly. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20201006235817.3280413-7-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | python/machine.py: Handle None events in events_waitJohn Snow2020-10-201-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | If the timeout is 0, we can get None back. Handle this explicitly. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20201006235817.3280413-6-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | python/machine.py: Don't modify state in _base_args()John Snow2020-10-202-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't append to the _remove_files list during _base_args; instead do so during _launch. Rework _base_args as a @property to help facilitate this impression. This has the additional benefit of making the type of _console_address easier to analyze statically. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20201006235817.3280413-5-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | python/machine.py: reorder __init__John Snow2020-10-201-19/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put the init arg handling all at the top, and mostly in order (deviating when one is dependent on another), and put what is effectively runtime state declaration at the bottom. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20201006235817.3280413-4-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | python/machine.py: Fix monitor address typingJohn Snow2020-10-201-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this, it's difficult for mypy to intuit what the concrete type of the monitor address is; it has difficulty inferring the type across two variables. Create _monitor_address as a property that always returns a valid address to simplify static type analysis. To preserve our ability to clean up, use a simple boolean to indicate whether or not we should try to clean up the sock file after execution. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20201006235817.3280413-3-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | python/qemu: use isort to lay out importsJohn Snow2020-10-206-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Borrowed from the QAPI cleanup series, use the same configuration to standardize the way we write and sort imports. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20201006235817.3280413-2-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
| * | MAINTAINERS: Add Python library stanzaJohn Snow2020-10-201-1/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I'm proposing that I split the actual Python library off from the other miscellaneous python scripts we have and declare it maintained. Add myself as a maintainer of this folder, along with Cleber. I will be actively working to add CI style guide checks, strict typing, and an actual package infrastructure to this folder specifically which differentiates it from loose, miscellaneous scripts which are generally maintained by other individuals with subject matter expertise. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Cleber Rosa <crosa@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2020-10-2029-148/+1405
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20201020-1' into staging target-arm queue: * Fix AArch32 SMLAD incorrect setting of Q bit * AArch32 VCVT fixed-point to float is always round-to-nearest * strongarm: Fix 'time to transmit a char' unit comment * Restrict APEI tables generation to the 'virt' machine * bcm2835: minor code cleanups * bcm2835: connect all IRQs from SYS_timer device * correctly flush TLBs when TBI is enabled * tests/qtest: Add npcm7xx timer test * loads-stores.rst: add footnote that clarifies GETPC usage * Fix reported EL for mte_check_fail * Ignore HCR_EL2.ATA when {E2H,TGE} != 11 * microbit_i2c: Fix coredump when dump-vmstate * nseries: Fix loading kernel image on n8x0 machines * Implement v8.1M low-overhead-loops # gpg: Signature made Tue 20 Oct 2020 21:10:35 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201020-1: (29 commits) target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile target/arm: Implement v8.1M low-overhead-loop instructions target/arm: Implement v8.1M branch-future insns (as NOPs) target/arm: Don't allow BLX imm for M-profile target/arm: Make the t32 insn[25:23]=111 group non-overlapping target/arm: Implement v8.1M conditional-select insns target/arm: Implement v8.1M NOCP handling decodetree: Fix codegen for non-overlapping group inside overlapping group hw/arm/nseries: Fix loading kernel image on n8x0 machines microbit_i2c: Fix coredump when dump-vmstate target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11 target/arm: Fix reported EL for mte_check_fail target/arm: Remove redundant mmu_idx lookup hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers loads-stores.rst: add footnote that clarifies GETPC usage tests/qtest: Add npcm7xx timer test target/arm: Use tlb_flush_page_bits_by_mmuidx* ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extensionPeter Maydell2020-10-203-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the M-profile low-overhead-branch extension is implemented, FPSCR bits [18:16] are a new field LTPSIZE. If MVE is not implemented (currently always true for us) then this field always reads as 4 and ignores writes. These bits used to be the vector-length field for the old short-vector extension, so we need to take care that they are not misinterpreted as setting vec_len. We do this with a rearrangement of the vfp_set_fpscr() code that deals with vec_len, vec_stride and also the QC bit; this obviates the need for the M-profile only masking step that we used to have at the start of the function. We provide a new field in CPUState for LTPSIZE, even though this will always be 4, in preparation for MVE, so we don't have to come back later and split it out of the vfp.xregs[FPSCR] value. (This state struct field will be saved and restored as part of the FPSCR value via the vmstate_fpscr in machine.c.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201019151301.2046-11-peter.maydell@linaro.org
| * target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16Peter Maydell2020-10-201-19/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | M-profile CPUs with half-precision floating point support should be able to write to FPSCR.FZ16, but an M-profile specific masking of the value at the top of vfp_set_fpscr() currently prevents that. This is not yet an active bug because we have no M-profile FP16 CPUs, but needs to be fixed before we can add any. The bits that the masking is effectively preventing from being set are the A-profile only short-vector Len and Stride fields, plus the Neon QC bit. Rearrange the order of the function so that those fields are handled earlier and only under a suitable guard; this allows us to drop the M-profile specific masking, making FZ16 writeable. This change also makes the QC bit correctly RAZ/WI for older no-Neon A-profile cores. This refactoring also paves the way for the low-overhead-branch LTPSIZE field, which uses some of the bits that are used for A-profile Stride and Len. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201019151301.2046-10-peter.maydell@linaro.org
| * target/arm: Fix has_vfp/has_neon ID reg squashing for M-profilePeter Maydell2020-10-201-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we squash the ID register fields so that we don't advertise it to the guest. This code was written for A-profile and needs some tweaks to work correctly on M-profile: * A-profile only fields should not be zeroed on M-profile: - MVFR0.FPSHVEC,FPTRAP - MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP - MVFR2.SIMDMISC * M-profile only fields should be zeroed on M-profile: - MVFR1.FP16 In particular, because MVFR1.SIMDHP on A-profile is the same field as MVFR1.FP16 on M-profile this code was incorrectly disabling FP16 support on an M-profile CPU (where has_neon is always false). This isn't a visible bug yet because we don't have any M-profile CPUs with FP16 support, but the change is necessary before we introduce any. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-9-peter.maydell@linaro.org
| * target/arm: Implement v8.1M low-overhead-loop instructionsPeter Maydell2020-10-202-2/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v8.1M's "low-overhead-loop" extension has three instructions for looping: * DLS (start of a do-loop) * WLS (start of a while-loop) * LE (end of a loop) The loop-start instructions are both simple operations to start a loop whose iteration count (if any) is in LR. The loop-end instruction handles "decrement iteration count and jump back to loop start"; it also caches the information about the branch back to the start of the loop to improve performance of the branch on subsequent iterations. As with the branch-future instructions, the architecture permits an implementation to discard the LO_BRANCH_INFO cache at any time, and QEMU takes the IMPDEF option to never set it in the first place (equivalent to discarding it immediately), because for us a "real" implementation would be unnecessary complexity. (This implementation only provides the simple looping constructs; the vector extension MVE (Helium) adds some extra variants to handle looping across vectors. We'll add those later when we implement MVE.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201019151301.2046-8-peter.maydell@linaro.org
| * target/arm: Implement v8.1M branch-future insns (as NOPs)Peter Maydell2020-10-203-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v8.1M implements a new 'branch future' feature, which is a set of instructions that request the CPU to perform a branch "in the future", when it reaches a particular execution address. In hardware, the expected implementation is that the information about the branch location and destination is cached and then acted upon when execution reaches the specified address. However the architecture permits an implementation to discard this cached information at any point, and so guest code must always include a normal branch insn at the branch point as a fallback. In particular, an implementation is specifically permitted to treat all BF insns as NOPs (which is equivalent to discarding the cached information immediately). For QEMU, implementing this caching of branch information would be complicated and would not improve the speed of execution at all, so we make the IMPDEF choice to implement all BF insns as NOPs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-7-peter.maydell@linaro.org
| * target/arm: Don't allow BLX imm for M-profilePeter Maydell2020-10-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The BLX immediate insn in the Thumb encoding always performs a switch from Thumb to Arm state. This would be totally useless in M-profile which has no Arm decoder, and so the instruction does not exist at all there. Make the encoding UNDEF for M-profile. (This part of the encoding space is used for the branch-future and low-overhead-loop insns in v8.1M.) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-6-peter.maydell@linaro.org
| * target/arm: Make the t32 insn[25:23]=111 group non-overlappingPeter Maydell2020-10-201-13/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The t32 decode has a group which represents a set of insns which overlap with B_cond_thumb because they have [25:23]=111 (which is an invalid condition code field for the branch insn). This group is currently defined using the {} overlap-OK syntax, but it is almost entirely non-overlapping patterns. Switch it over to use a non-overlapping group. For this to be valid syntactically, CPS must move into the same overlapping-group as the hint insns (CPS vs hints was the only actual use of the overlap facility for the group). The non-overlapping subgroup for CLREX/DSB/DMB/ISB/SB is no longer necessary and so we can remove it (promoting those insns to be members of the parent group). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-5-peter.maydell@linaro.org
| * target/arm: Implement v8.1M conditional-select insnsPeter Maydell2020-10-202-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | v8.1M brings four new insns to M-profile: * CSEL : Rd = cond ? Rn : Rm * CSINC : Rd = cond ? Rn : Rm+1 * CSINV : Rd = cond ? Rn : ~Rm * CSNEG : Rd = cond ? Rn : -Rm Implement these. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-4-peter.maydell@linaro.org
| * target/arm: Implement v8.1M NOCP handlingPeter Maydell2020-10-203-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From v8.1M, disabled-coprocessor handling changes slightly: * coprocessors 8, 9, 14 and 15 are also governed by the cp10 enable bit, like cp11 * an extra range of instruction patterns is considered to be inside the coprocessor space We previously marked these up with TODO comments; implement the correct behaviour. Unfortunately there is no ID register field which indicates this behaviour. We could in theory test an unrelated ID register which indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch >= 3 (low-overhead-loops), but it seems better to simply define a new ARM_FEATURE_V8_1M feature flag and use it for this and other new-in-v8.1M behaviour that isn't identifiable from the ID registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201019151301.2046-3-peter.maydell@linaro.org
| * decodetree: Fix codegen for non-overlapping group inside overlapping groupPeter Maydell2020-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For nested groups like: { [ pattern 1 pattern 2 ] pattern 3 } the intended behaviour is that patterns 1 and 2 must not overlap with each other; if the insn matches neither then we fall through to pattern 3 as the next thing in the outer overlapping group. Currently we generate incorrect code for this situation, because in the code path for a failed match inside the inner non-overlapping group we generate a "return" statement, which causes decode to stop entirely rather than continuing to the next thing in the outer group. Generate a "break" instead, so that decode flow behaves as required for this nested group case. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201019151301.2046-2-peter.maydell@linaro.org
| * hw/arm/nseries: Fix loading kernel image on n8x0 machinesPhilippe Mathieu-Daudé2020-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7998beb9c2e removed the ram_size initialization in the arm_boot_info structure, however it is used by arm_load_kernel(). Initialize the field to fix: $ qemu-system-arm -M n800 -append 'console=ttyS1' \ -kernel meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0 qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size 1964608, RAM size 0) Noticed while running the test introduced in commit 050a82f0c5b ("tests/acceptance: Add a test for the N800 and N810 arm machines"). Fixes: 7998beb9c2e ("arm/nseries: use memdev for RAM") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Message-id: 20201019095148.1602119-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * microbit_i2c: Fix coredump when dump-vmstatePeng Liang2020-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | VMStateDescription.fields should be end with VMSTATE_END_OF_LIST(). However, microbit_i2c_vmstate doesn't follow it. Let's change it. Fixes: 9d68bf564e ("arm: Stub out NRF51 TWI magnetometer/accelerometer detection") Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Peng Liang <liangpeng10@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20201019093401.2993833-1-liangpeng10@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11Richard Henderson2020-10-202-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike many other bits in HCR_EL2, the description for this bit does not contain the phrase "if ... this field behaves as 0 for all purposes other than", so do not squash the bit in arm_hcr_el2_eff. Instead, replicate the E2H+TGE test in the two places that require it. Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Message-id: 20201008162155.161886-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Fix reported EL for mte_check_failRichard Henderson2020-10-201-7/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reporting in AArch64.TagCheckFail only depends on PSTATE.EL, and not the AccType of the operation. There are two guest visible problems that affect LDTR and STTR because of this: (1) Selecting TCF0 vs TCF1 to decide on reporting, (2) Report "data abort same el" not "data abort lower el". Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Message-id: 20201008162155.161886-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Remove redundant mmu_idx lookupRichard Henderson2020-10-201-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already have the full ARMMMUIdx as computed from the function parameter. For the purpose of regime_has_2_ranges, we can ignore any difference between AccType_Normal and AccType_Unpriv, which would be the only difference between the passed mmu_idx and arm_mmu_idx_el. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Message-id: 20201008162155.161886-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbersPhilippe Mathieu-Daudé2020-10-201-4/+4
| | | | | | | | | | | | | | | | | | | | The IRQ values are defined few lines earlier, use them instead of the magic numbers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201017180731.1165871-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlersPhilippe Mathieu-Daudé2020-10-202-1/+7
| | | | | | | | | | | | | | | | | | Add trace events for GPU and CPU IRQs. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201017180731.1165871-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * loads-stores.rst: add footnote that clarifies GETPC usageEmanuele Giuseppe Esposito2020-10-201-1/+7
| | | | | | | | | | | | | | | | | | | | | | Current documentation is not too clear on the GETPC usage. In particular, when used outside the top level helper function it causes unexpected behavior. Signed-off-by: Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com> Message-id: 20201015095147.1691-1-e.emanuelegiuseppe@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/qtest: Add npcm7xx timer testHavard Skinnemoen2020-10-202-0/+563
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This test exercises the various modes of the npcm7xx timer. In particular, it triggers the bug found by the fuzzer, as reported here: https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg02992.html It also found several other bugs, especially related to interrupt handling. The test exercises all the timers in all the timer modules, which expands to 180 test cases in total. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20201008232154.94221-2-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use tlb_flush_page_bits_by_mmuidx*Richard Henderson2020-10-201-7/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When TBI is enabled in a given regime, 56 bits of the address are significant and we need to clear out any other matching virtual addresses with differing tags. The other uses of tlb_flush_page (without mmuidx) in this file are only used by aarch32 mode. Fixes: 38d931687fa1 Reported-by: Jordan Frank <jordanfrank@fb.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201016210754.818257-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * accel/tcg: Add tlb_flush_page_bits_by_mmuidx*Richard Henderson2020-10-202-9/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM, the Top Byte Ignore feature means that only 56 bits of the address are significant in the virtual address. We are required to give the entire 64-bit address to FAR_ELx on fault, which means that we do not "clean" the top byte early in TCG. This new interface allows us to flush all 256 possible aliases for a given page, currently missed by tlb_flush_page*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201016210754.818257-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQsPhilippe Mathieu-Daudé2020-10-201-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | The SYS_timer is not directly wired to the ARM core, but to the SoC (peripheral) interrupt controller. Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer") Reviewed-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201010203709.3116542-5-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/timer/bcm2835: Support the timer COMPARE registersPhilippe Mathieu-Daudé2020-10-203-21/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This peripheral has 1 free-running timer and 4 compare registers. Only the free-running timer is implemented. Add support the COMPARE registers (each register is wired to an IRQ). Reference: "BCM2835 ARM Peripherals" datasheet [*] chapter 12 "System Timer": The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter. Each channel has an output compare register, which is compared against the 32 least significant bits of the free running counter values. When the two values match, the system timer peripheral generates a signal to indicate a match for the appropriate channel. The match signal is then fed into the interrupt controller. This peripheral is used since Linux 3.7, commit ee4af5696720 ("ARM: bcm2835: add system timer"). [*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20201010203709.3116542-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/timer/bcm2835: Rename variable holding CTRL_STATUS registerPhilippe Mathieu-Daudé2020-10-202-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | The variable holding the CTRL_STATUS register is misnamed 'status'. Rename it 'ctrl_status' to make it more obvious this register is also used to control the peripheral. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201010203709.3116542-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definitionPhilippe Mathieu-Daudé2020-10-202-2/+5
| | | | | | | | | | | | | | | | | | | | | | Use the BCM2835_SYSTIMER_COUNT definition instead of the magic '4' value. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201010203709.3116542-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Restrict APEI tables generation to the 'virt' machinePhilippe Mathieu-Daudé2020-10-202-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While APEI is a generic ACPI feature (usable by X86 and ARM64), only the 'virt' machine uses it, by enabling the RAS Virtualization. See commit 2afa8c8519: "hw/arm/virt: Introduce a RAS machine option"). Restrict the APEI tables generation code to the single user: the virt machine. If another machine wants to use it, it simply has to 'select ACPI_APEI' in its Kconfig. Fixes: aa16508f1d ("ACPI: Build related register address fields via hardware error fw_cfg blob") Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Dongjiu Geng <gengdongjiu@huawei.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20201008161414.2672569-1-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/strongarm: Fix 'time to transmit a char' unit commentPhilippe Mathieu-Daudé2020-10-201-1/+1
| | | | | | | | | | | | | | | | | | The time to transmit a char is expressed in nanoseconds, not in ticks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201014213601.205222-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: AArch32 VCVT fixed-point to float is always round-to-nearestPeter Maydell2020-10-203-13/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For AArch32, unlike the VCVT of integer to float, which honours the rounding mode specified by the FPSCR, VCVT of fixed-point to float is always round-to-nearest. (AArch64 fixed-point-to-float conversions always honour the FPCR rounding mode.) Implement this by providing _round_to_nearest versions of the relevant helpers which set the rounding mode temporarily when making the call to the underlying softfloat function. We only need to change the VFP VCVT instructions, because the standard- FPSCR value used by the Neon VCVT is always set to round-to-nearest, so we don't need to do the extra work of saving and restoring the rounding mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201013103532.13391-1-peter.maydell@linaro.org
| * target/arm: Fix SMLAD incorrect setting of Q bitPeter Maydell2020-10-201-11/+49
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SMLAD instruction is supposed to: * signed multiply Rn[15:0] * Rm[15:0] * signed multiply Rn[31:16] * Rm[31:16] * perform a signed addition of the products and Ra * set Rd to the low 32 bits of the theoretical infinite-precision result * set the Q flag if the sign-extension of Rd would differ from the infinite-precision result (ie on overflow) Our current implementation doesn't quite do this, though: it performs an addition of the products setting Q on overflow, and then it adds Ra, again possibly setting Q. This sometimes incorrectly sets Q when the architecturally mandated only-check-for-overflow-once algorithm does not. For instance: r1 = 0x80008000; r2 = 0x80008000; r3 = 0xffffffff smlad r0, r1, r2, r3 This is (-32768 * -32768) + (-32768 * -32768) - 1 The products are both 0x4000_0000, so when added together as 32-bit signed numbers they overflow (and QEMU sets Q), but because the addition of Ra == -1 brings the total back down to 0x7fff_ffff there is no overflow for the complete operation and setting Q is incorrect. Fix this edge case by resorting to 64-bit arithmetic for the case where we need to add three values together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201009144712.11187-1-peter.maydell@linaro.org
* Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into ↵Peter Maydell2020-10-208-16/+51
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Xen queue * cleanup patches. * improve xen backend setup performance when other xen guests are running/booting. * improve xen guest migration when running in a stubdomain. # gpg: Signature made Tue 20 Oct 2020 10:55:11 BST # gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF # gpg: issuer "anthony.perard@citrix.com" # gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [marginal] # gpg: aka "Anthony PERARD <anthony.perard@citrix.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8 # Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF * remotes/aperard/tags/pull-xen-20201020: hw/xen: Set suppress-vmdesc for Xen machines xen-bus: reduce scope of backend watch xen: Rename XENBACKEND_DEVICE to XENBACKEND xen: xenguest is not used so is not needed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/xen: Set suppress-vmdesc for Xen machinesJason Andryuk2020-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xen-save-devices-state doesn't currently generate a vmdesc, so restore always triggers "Expected vmdescription section, but got 0". This is not a problem when restore comes from a file. However, when QEMU runs in a linux stubdom and comes over a console, EOF is not received. This causes a delay restoring - though it does restore. Setting suppress-vmdesc skips looking for the vmdesc during restore and avoids the wait. The other approach would be generate a vmdesc in qemu_save_device_state. Since COLO shared that function, and the vmdesc is just discarded on restore, we choose to skip it. Reported-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> Signed-off-by: Jason Andryuk <jandryuk@gmail.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20201013190506.3325-1-jandryuk@gmail.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
| * xen-bus: reduce scope of backend watchPaul Durrant2020-10-194-9/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently a single watch on /local/domain/X/backend is registered by each QEMU process running in service domain X (where X is usually 0). The purpose of this watch is to ensure that QEMU is notified when the Xen toolstack creates a new device backend area. Such a backend area is specific to a single frontend area created for a specific guest domain and, since each QEMU process is also created to service a specfic guest domain, it is unnecessary and inefficient to notify all QEMU processes. Only the QEMU process associated with the same guest domain need receive the notification. This patch re-factors the watch registration code such that notifications are targetted appropriately. Reported-by: Jerome Leseinne <jerome.leseinne@gmail.com> Signed-off-by: Paul Durrant <pdurrant@amazon.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20201001081500.1026-1-paul@xen.org> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
| * xen: Rename XENBACKEND_DEVICE to XENBACKENDEduardo Habkost2020-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | Make the type checking macro name consistent with the TYPE_* constant. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20200902224311.1321159-58-ehabkost@redhat.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
| * xen: xenguest is not used so is not neededMichael Tokarev2020-10-192-4/+2Star
|/ | | | | | | | | | | | There's no references in only file which includes xenguest.h to any xen definitions. And there's no references to -lxenguest in qemu, either. Drop it. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20200727140048.19779-1-mjt@msgid.tls.msk.ru> [perard: rebased] Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
* Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201019' ↵Peter Maydell2020-10-195-23/+292
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging 9pfs: add tests using local fs driver The currently existing 9pfs test cases are all solely using the 9pfs 'synth' fileystem driver, which is a very simple and purely simulated (in RAM only) filesystem. There are issues though where the 'synth' fs driver is not sufficient. For example the following two bugs need test cases running the 9pfs 'local' fs driver: https://bugs.launchpad.net/qemu/+bug/1336794 https://bugs.launchpad.net/qemu/+bug/1877384 This patch set for that reason introduces 9pfs test cases using the 9pfs 'local' filesystem driver along to the already existing tests on 'synth'. # gpg: Signature made Mon 19 Oct 2020 13:39:08 BST # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * remotes/cschoenebeck/tags/pull-9p-20201019: tests/9pfs: add local Tmkdir test tests/9pfs: add virtio_9p_test_path() tests/9pfs: wipe local 9pfs test directory tests/9pfs: introduce local tests tests/9pfs: change qtest name prefix to synth 9pfs: suppress performance warnings on qtest runs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/9pfs: add local Tmkdir testChristian Schoenebeck2020-10-191-0/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This test case uses the 9pfs 'local' driver to create a directory and then checks if the expected directory was actually created (as real directory) on host side. This patch introduces a custom split() implementation, because the test code requires non empty array elements as result. For that reason g_strsplit() would not be a good alternative, as it would require additional filter code for reshuffling the array, and the resulting code would be even more complex than this split() function. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <be342f236842272275f65dbe05587f0a5409ad77.1602182956.git.qemu_oss@crudebyte.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
| * tests/9pfs: add virtio_9p_test_path()Christian Schoenebeck2020-10-192-0/+11
| | | | | | | | | | | | | | | | | | | | | | This new public function virtio_9p_test_path() allows 9pfs 'local' tests to translate a path from guest scope to host scope. For instance by passing an empty string it would return the root path on host of the exported 9pfs tree. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <b563d3c73c6391ec927a2622c9f65c09ca56bd83.1602182956.git.qemu_oss@crudebyte.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
| * tests/9pfs: wipe local 9pfs test directoryChristian Schoenebeck2020-10-191-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before running the first 9pfs test case, make sure the test directory for running the 9pfs 'local' tests on is entirely empty. For that reason simply delete the test directory (if any) before (re)creating it on test suite startup. Note: The preferable precise behaviour would be the test directory only being wiped once *before* a test suite run. Right now the test directory is also wiped at the *end* of a test suite run because libqos is calling the virtio_9p_register_nodes() callback for some reason also when a test suite completed. This is suboptimal as developers cannot immediately see what files and directories the 9pfs local tests created precisely after the test suite completed. But fortunately the test directory is not wiped if some test failed. So it is probably not worth it drilling another hole into libqos for this issue. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <b30776ea3289dc40dabc7d0063d825d21d9a65bf.1602182956.git.qemu_oss@crudebyte.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
| * tests/9pfs: introduce local testsChristian Schoenebeck2020-10-193-14/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces 9pfs test cases using the 9pfs 'local' filesystem driver which reads/writes/creates/deletes real files and directories. In this initial version, there is only one local test which actually only checks if the 9pfs 'local' device was created successfully. Before the 9pfs 'local' tests are run, a test directory 'qtest-9p-local' is created (with world rwx permissions) under the current working directory. At this point that test directory is not auto deleted yet. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <81fc4b3b6b6c9bf7999e79f5e7cbc364a5f09ddb.1602182956.git.qemu_oss@crudebyte.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
| * tests/9pfs: change qtest name prefix to synthChristian Schoenebeck2020-10-191-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All existing 9pfs test cases are using the 'synth' fs driver so far, which means they are not accessing real files, but a purely simulated (in RAM only) file system. Let's make this clear by changing the prefix of the individual qtest case names from 'fs/' to 'synth/'. That way they'll be easily distinguishable from upcoming new 9pfs test cases supposed to be using a different fs driver. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <e04e75acb849b085c6d6320b2433a15fa935bcff.1602182956.git.qemu_oss@crudebyte.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
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