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* target-ppc: Use ctpop helperRichard Henderson2017-01-103-18/+9Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Use ctpop helperRichard Henderson2017-01-103-8/+1Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add opcode for ctpopRichard Henderson2017-01-1016-0/+79
| | | | | | | | | The number of actual invocations of ctpop itself does not warrent an opcode, but it is very helpful for POWER7 to use in generating an expansion for ctz. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-xtensa: Use clrsb helperRichard Henderson2017-01-101-10/+1Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Use clrsb helperRichard Henderson2017-01-103-7/+1Star
| | | | | | Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: Use clrsb helperRichard Henderson2017-01-103-16/+4Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add helpers for clrsbRichard Henderson2017-01-104-0/+44
| | | | | | | | | The number of actual invocations does not warrent an opcode, and the backends generating it. But at least we can eliminate redundant helpers. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSRRichard Henderson2017-01-101-13/+22
| | | | | | | | | | | | | | | The ISA manual documents the output is undefined if the input was zero. However, we document in target-i386 that the behavior of real silicon is to preserve the contents of the output register. We also mention that there are real applications that depend on this. That this is baked into silicon is mentioned as a potential cause for some false sharing behaviour wrt lzcnt/tzcnt. Taking advantage of this allows us to save 2 insns in the normal case, and 4 insns for i686 emulating a 64-bit clz. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Handle ctz and clz opcodesRichard Henderson2017-01-102-13/+120
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Allow bmi2 shiftx to have non-matching operandsRichard Henderson2017-01-101-14/+19
| | | | | | | | | | Previously we could not have different constraints for different ISA levels, which prevented us from eliding the matching constraint for shifts. We do now have to make sure that the operands match for constant shifts. We can also handle some small left shifts via lea. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Hoist common arguments in tcg_out_opRichard Henderson2017-01-101-102/+95Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Fuly convert tcg_target_op_defRichard Henderson2017-01-101-142/+198
| | | | | | | Use a switch instead of searching a table. Share constraints between 32-bit and 64-bit, when at all possible. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Handle clz opcodeRichard Henderson2017-01-102-2/+36
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/mips: Handle clz opcodeRichard Henderson2017-01-102-2/+51
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/arm: Handle ctz and clz opcodesRichard Henderson2017-01-102-2/+29
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/aarch64: Handle ctz and clz opcodesRichard Henderson2017-01-102-4/+52
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/ppc: Handle ctz and clz opcodesRichard Henderson2017-01-102-4/+73
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Use clz and ctz opcodesRichard Henderson2017-01-103-30/+14Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: Use clz opcodeRichard Henderson2017-01-106-25/+7Star
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-xtensa: Use clz opcodeRichard Henderson2017-01-103-17/+11Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-unicore32: Use clz opcodeRichard Henderson2017-01-103-16/+3Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Use clz opcodeRichard Henderson2017-01-103-14/+3Star
| | | | | | Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tilegx: Use clz and ctz opcodesRichard Henderson2017-01-103-14/+2Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390x: Use clz opcodeRichard Henderson2017-01-103-8/+1Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-ppc: Use clz and ctz opcodesRichard Henderson2017-01-103-28/+16Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-openrisc: Use clz and ctz opcodesRichard Henderson2017-01-103-23/+4Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-mips: Use clz opcodeRichard Henderson2017-01-103-36/+16Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-microblaze: Use clz opcodeRichard Henderson2017-01-103-7/+1Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-cris: Use clz opcodeRichard Henderson2017-01-103-7/+1Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Use the ctz and clz opcodesRichard Henderson2017-01-103-14/+2Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas/ppc: Handle popcnt and cnttzRichard Henderson2017-01-101-0/+10
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas/i386.c: Handle tzcntRichard Henderson2017-01-101-2/+10
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add clz and ctz opcodesRichard Henderson2017-01-1017-0/+266
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Allow an operand to be matching or a constantRichard Henderson2017-01-102-35/+41
| | | | | | | | This allows an output operand to match an input operand only when the input operand needs a register. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Pass the opcode width to target_parse_constraintRichard Henderson2017-01-1010-85/+53Star
| | | | | | | | | | | | This will let us choose how to interpret a given constraint depending on whether the opcode is 32- or 64-bit. Which will let us share more constraint combinations between opcodes. At the same time, change the interface to return the advanced pointer instead of passing it in/out by reference. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Transition flat op_defs array to a target callbackRichard Henderson2017-01-1011-77/+136
| | | | | | | | This will allow the target to tailor the constraints to the auto-detected ISA extensions. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add markup for output requires new registerRichard Henderson2017-01-102-12/+23
| | | | | | | | This is the same concept as, and same markup as, the early clobber markup in gcc. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/optimize: Fold movcond 0/1 into setcondRichard Henderson2017-01-101-0/+15
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390x: Use the new deposit and extract opsRichard Henderson2017-01-101-12/+22
| | | | | | Use the new primitives for RISBG. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-ppc: Use the new deposit and extract opsRichard Henderson2017-01-101-16/+19
| | | | | | | Use the new primitives for RDWINM and RLDICL. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-mips: Use the new extract opRichard Henderson2017-01-101-7/+5Star
| | | | | | | Use extract for EXT and DEXT. Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Use new deposit and extract opsRichard Henderson2017-01-101-22/+23
| | | | | | | | | A couple of places where it was easy to identify a right-shift followed by an extract or and-with-immediate, and the obvious sign-extract from a high byte register. Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: Use new deposit and extract opsRichard Henderson2017-01-102-81/+37Star
| | | | | | Use the new primitives for UBFX and SBFX. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-alpha: Use deposit and extract opsRichard Henderson2017-01-101-25/+42
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Support deposit into zeroRichard Henderson2017-01-101-4/+26
| | | | | | | Since we can no longer use matching constraints, this does mean we must handle that data movement by hand. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Implement field extraction opcodesRichard Henderson2017-01-102-2/+13
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Expose host facilities to tcg-target.hRichard Henderson2017-01-102-104/+96Star
| | | | | | | This lets us expose facilities to TCG_TARGET_HAS_* defines directly, rather than hiding behind function calls. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/ppc: Implement field extraction opcodesRichard Henderson2017-01-102-2/+12
| | | | | Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/mips: Implement field extraction opcodesRichard Henderson2017-01-102-1/+12
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Implement field extraction opcodesRichard Henderson2017-01-102-3/+47
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
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