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* clock: Provide builtin multiplier/dividerPeter Maydell2021-09-015-5/+119
* hw/arm/mps2.c: Connect up armv7m clocksPeter Maydell2021-09-011-0/+15
* armsse: Wire up systick cpuclk clockPeter Maydell2021-09-011-0/+3
* hw/arm/armv7m: Create input clocksPeter Maydell2021-09-012-0/+29
* hw/timer/armv7m_systick: Add input clocksPeter Maydell2021-09-012-2/+15
* hw/timer/armv7m_systick: Add usual QEMU interface commentPeter Maydell2021-09-011-0/+7
* arm: Move system PPB container handling to armv7mPeter Maydell2021-09-014-145/+107Star
* arm: Move systick device creation from NVIC to ARMv7M objectPeter Maydell2021-09-014-77/+137
* arm: Move M-profile RAS register block into its own devicePeter Maydell2021-09-018-57/+148
* tests/arm-cpu-features: Add A64FX processor related testsShuuichirou Ishii2021-09-011-0/+13
* hw/arm/virt: target-arm: Add A64FX processor support to virt machineShuuichirou Ishii2021-09-012-0/+2
* target-arm: Add support for Fujitsu A64FXShuuichirou Ishii2021-09-011-0/+48
* target/arm: Enable MVE in Cortex-M55Peter Maydell2021-09-011-5/+2Star
* target/arm: Implement MVE VRINT insnsPeter Maydell2021-09-014-0/+93
* target/arm: Implement MVE VCVT between single and half precisionPeter Maydell2021-09-014-0/+108
* target/arm: Implement MVE VCVT with specified rounding modePeter Maydell2021-09-014-0/+105
* target/arm: Implement MVE VCVT between fp and integerPeter Maydell2021-09-012-0/+39
* target/arm: Implement MVE VCVT between floating and fixed pointPeter Maydell2021-09-014-0/+82
* target/arm: Implement MVE fp scalar comparisonsPeter Maydell2021-09-014-24/+131
* target/arm: Implement MVE fp vector comparisonsPeter Maydell2021-09-014-6/+137
* target/arm: Implement MVE FP max/min across vectorPeter Maydell2021-09-014-6/+102
* softfloat: Remove assertion preventing silencing of NaN in default-NaN modePeter Maydell2021-09-011-1/+0Star
* target/arm: Implement MVE fp-with-scalar VFMA, VFMASPeter Maydell2021-09-014-3/+56
* target/arm: Implement MVE scalar fp insnsPeter Maydell2021-09-014-6/+85
* target/arm: Implement MVE VMAXNMA and VMINNMAPeter Maydell2021-09-014-0/+42
* target/arm: Implement MVE VCMUL and VCMLAPeter Maydell2021-09-014-8/+139
* target/arm: Implement MVE VFMA and VFMSPeter Maydell2021-09-014-0/+48
* target/arm: Implement MVE VCADDPeter Maydell2021-09-014-1/+57
* target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNMPeter Maydell2021-09-014-0/+42
* target/arm: Implement MVE VADD (floating-point)Peter Maydell2021-09-016-6/+76
* hw: Add compat machines for 6.2Yanan Wang2021-09-019-6/+71
* hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleansPhilippe Mathieu-Daudé2021-09-011-95/+106
* hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffixPhilippe Mathieu-Daudé2021-09-011-6/+6
* hw/arm/raspi: Remove deprecated raspi2/raspi3 aliasesPhilippe Mathieu-Daudé2021-09-013-9/+7Star
* tests: Remove uses of deprecated raspi2/raspi3 machine namesPhilippe Mathieu-Daudé2021-09-017-32/+32
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell2021-09-0124-1381/+1240Star
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| * target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-012-61/+26Star
| * target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-012-210/+57Star
| * target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60Star
| * target/riscv: Use {get,dest}_gpr for RVFRichard Henderson2021-09-011-76/+70Star
| * target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson2021-09-011-13/+6Star
| * target/riscv: Use {get,dest}_gpr for RVARichard Henderson2021-09-011-28/+19Star
| * target/riscv: Reorg csr instructionsRichard Henderson2021-09-013-66/+132
| * target/riscv: Fix hgeie, hgeipRichard Henderson2021-09-011-18/+8Star
| * target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson2021-09-011-8/+15
| * target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson2021-09-011-18/+20
| * target/riscv: Use get_gpr in branchesRichard Henderson2021-09-011-15/+10Star
| * target/riscv: Use extracts for sraiw and srliwRichard Henderson2021-09-011-2/+12
| * target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-013-202/+125Star
| * target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-012-23/+15Star
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