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* hw/mips: Simplify loading 64-bit ELF kernelsPhilippe Mathieu-Daudé2020-10-172-10/+2Star
| | | | | | | | | | Since 82790064116 ("Cast ELF datatypes properly to host 64bit types") we don't need to sign-extend the entry_point address. Remove this unnecessary code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200927163943.614604-2-f4bug@amsat.org>
* hw/mips/malta: Use clearer qdev stylePhilippe Mathieu-Daudé2020-10-171-4/+4
| | | | | | | | | | In order to be consistent with the other code base uses, rewrite slightly how the MIPS_MALTA object is created. No logical change. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201012160503.3472140-3-f4bug@amsat.org>
* hw/mips/malta: Move gt64120 related code togetherPhilippe Mathieu-Daudé2020-10-171-7/+6Star
| | | | | | | | | The 'empty_slot' region created is related to the gt64120. Move its creation close to the gt64120 instance creation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201012160503.3472140-2-f4bug@amsat.org>
* hw/mips/malta: Fix FPGA I/O region sizePhilippe Mathieu-Daudé2020-10-171-1/+1
| | | | | | | | | | | | The FPGA present on the CoreCard has an I/O region 1MiB wide. Refs: - Atlas User’s Manual (Document Number: MD00005) - Malta User’s Manual (Document Number: MD00048) Fixes: ea85df72b60 ("mips_malta: convert to memory API") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200905213049.761949-1-f4bug@amsat.org>
* target/mips/cpu: Display warning when CPU is used without input clockPhilippe Mathieu-Daudé2020-10-171-0/+10
| | | | | | | | | | | | | All our QOM users provides an input clock. In order to avoid avoid future machines added without clock, display a warning. User-mode emulation use the CP0 timer with the RDHWR instruction (see commit cdfcad788394) so keep using the fixed 200 MHz clock without diplaying any warning. Only display it in system-mode emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-22-f4bug@amsat.org>
* hw/mips/cps: Do not allow use without input clockPhilippe Mathieu-Daudé2020-10-171-0/+5
| | | | | | | | Now than all QOM users provides the input clock, do not allow using a CPS without input clock connected. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-21-f4bug@amsat.org>
* hw/mips/malta: Set CPU frequency to 320 MHzPhilippe Mathieu-Daudé2020-10-171-3/+16
| | | | | | | | The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-20-f4bug@amsat.org>
* hw/mips/boston: Set CPU frequency to 1 GHzPhilippe Mathieu-Daudé2020-10-171-0/+13
| | | | | | | | The I6400 can run at 1 GHz or more. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-19-f4bug@amsat.org>
* hw/mips/cps: Expose input clock and connect it to CPU coresPhilippe Mathieu-Daudé2020-10-172-0/+6
| | | | | | | | Expose a qdev input clock named 'clk-in', and connect it to each core to forward-propagate the clock. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-18-f4bug@amsat.org>
* hw/mips/jazz: Correct CPU frequenciesPhilippe Mathieu-Daudé2020-10-171-1/+14
| | | | | | | | The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61 CPU at ~134 MHz. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-17-f4bug@amsat.org>
* hw/mips/mipssim: Correct CPU frequencyPhilippe Mathieu-Daudé2020-10-171-1/+10
| | | | | | | | | | | The MIPSsim machine CPU frequency is too fast running at 200 MHz, while it should be 12 MHz for the 24K and 6 MHz for the 5K core. Ref: Linux commit c78cbf49c4ed ("Support for MIPSsim, the cycle accurate MIPS simulator.") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-16-f4bug@amsat.org>
* hw/mips/fuloong2e: Set CPU frequency to 533 MHzPhilippe Mathieu-Daudé2020-10-171-1/+6
| | | | | | | | | | | The CPU frequency is normally provided by the firmware in the "cpuclock" environment variable. The 2E board can handles up to 660MHz, but be conservative and take the same value used by the Linux kernel: 533 MHz. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-15-f4bug@amsat.org>
* hw/mips/r4k: Explicit CPU frequency is 200 MHzPhilippe Mathieu-Daudé2020-10-171-1/+6
| | | | | | | | Since its introduction in commit 6af0bf9c7c3, the 'r4k' machine runs at 200 MHz. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-14-f4bug@amsat.org>
* target/mips/cpu: Introduce mips_cpu_create_with_clock() helperPhilippe Mathieu-Daudé2020-10-172-0/+24
| | | | | | | | | | Introduce an helper to create a MIPS CPU and connect it to a reference clock. This helper is not MIPS specific, but so far only MIPS CPUs need it. Suggested-by: Huacai Chen <zltjiangshi@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-13-f4bug@amsat.org>
* target/mips/cpu: Allow the CPU to use dynamic frequenciesPhilippe Mathieu-Daudé2020-10-172-2/+13
| | | | | | | | | | | Use the Clock API and let the CPU object have an input clock. If no clock is connected, keep using the default frequency of 200 MHz used since the introduction of the 'r4k' machine in commit 6af0bf9c7c3. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-12-f4bug@amsat.org>
* target/mips/cpu: Make cp0_count_rate a propertyPhilippe Mathieu-Daudé2020-10-172-8/+20
| | | | | | | | Since not all CPU implementations use a cores use a CP0 timer at half the frequency of the CPU, make this variable a property. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>
* target/mips/cpu: Calculate the CP0 timer period using the CPU frequencyPhilippe Mathieu-Daudé2020-10-171-2/+2
| | | | | | | | | | The CP0 timer period is a function of the CPU frequency. Start using the default values, which will be replaced by properties in the next commits. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
* target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé2020-10-173-17/+28
| | | | | | | | | | | | | | Currently the CP0 timer period is fixed at 10 ns, corresponding to a fixed CPU frequency of 200 MHz (using half the speed of the CPU). In few commits we will be able to use a different CPU frequency. In preparation, move the cp0_count_ns variable to CPUMIPSState so we can modify it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>
* target/mips/cp0_timer: Document TIMER_PERIOD originPhilippe Mathieu-Daudé2020-10-171-1/+11
| | | | | | | | | | TIMER_PERIOD value of '10 ns' can be explained looking at commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz and CP0 default count rate is half the frequency of the CPU. Document that. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-8-f4bug@amsat.org>
* target/mips/cp0_timer: Explicit unit in variable namePhilippe Mathieu-Daudé2020-10-171-9/+10
| | | | | | | | Name variables holding nanoseconds with the '_ns' suffix. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20201012095804.3335117-7-f4bug@amsat.org>
* target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé2020-10-173-26/+26
| | | | | | | | | | | | | The get_random() helper uses the CP0_Wired register, which is unrelated to the CP0_Count register used as timer. Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") incorrectly moved this get_random() helper with timer specific code. Move it back to generic CP0 helpers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-Id: <20201012095804.3335117-6-f4bug@amsat.org>
* target/mips/op_helper: Log unimplemented cache opcodePhilippe Mathieu-Daudé2020-10-171-0/+9
| | | | | | | | | | | In case the guest uses a cache opcode we are not expecting, log it to give us a chance to notice it, in case we should actually do something. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-4-f4bug@amsat.org>
* target/mips/op_helper: Document Invalidate/Writeback opcodes as no-opPhilippe Mathieu-Daudé2020-10-171-0/+5
| | | | | | | | | | | QEMU does not model caches, so there is not much to do with the Invalidate/Writeback opcodes. Make it explicit adding a comment. Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-3-f4bug@amsat.org>
* target/mips/op_helper: Convert multiple if() to switch casePhilippe Mathieu-Daudé2020-10-171-4/+9
| | | | | | | | | | | | | | | | | | The cache operation is encoded in bits [20:18] of the instruction. The 'op' argument of helper_cache() contains the bits [20:16]. Extract the 3 bits and parse them using a switch case. This allow us to handle multiple cache types (the cache type is encoded in bits [17:16]). Previously the if() block was only checking the D-Cache (Primary Data or Unified Primary). Now we also handle the I-Cache (Primary Instruction), S-Cache (Secondary) and T-Cache (Terciary). Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-2-f4bug@amsat.org>
* target/mips: Add loongson-ext lsdc2 group of instructionsJiaxun Yang2020-10-171-0/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LDC2/SDC2 opcodes have been rewritten as "load & store with offset" group of instructions by loongson-ext ASE. This patch add implementation of these instructions: gslbx: load 1 bytes to GPR gslhx: load 2 bytes to GPR gslwx: load 4 bytes to GPR gsldx: load 8 bytes to GPR gslwxc1: load 4 bytes to FPR gsldxc1: load 8 bytes to FPR gssbx: store 1 bytes from GPR gsshx: store 2 bytes from GPR gsswx: store 4 bytes from GPR gssdx: store 8 bytes from GPR gsswxc1: store 4 bytes from FPR gssdxc1: store 8 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602831120-3377-5-git-send-email-chenhc@lemote.com>
* target/mips: Add loongson-ext lswc2 group of instructions (Part 2)Jiaxun Yang2020-10-171-2/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslwlc1: similar to lwl but RT is FPR instead of GPR gslwrc1: similar to lwr but RT is FPR instead of GPR gsldlc1: similar to ldl but RT is FPR instead of GPR gsldrc1: similar to ldr but RT is FPR instead of GPR gsswlc1: similar to swl but RT is FPR instead of GPR gsswrc1: similar to swr but RT is FPR instead of GPR gssdlc1: similar to sdl but RT is FPR instead of GPR gssdrc1: similar to sdr but RT is FPR instead of GPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com> [PMD: Reuse t1 on MIPS32, reintroduce t2/fp0] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Add loongson-ext lswc2 group of instructions (Part 1)Jiaxun Yang2020-10-171-0/+86
| | | | | | | | | | | | | | | | | | | | | | LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslq: load 16 bytes to GPR gssq: store 16 bytes from GPR gslqc1: load 16 bytes to FPR gssqc1: store 16 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1602831120-3377-3-git-send-email-chenhc@lemote.com> [PMD: Restrict t1 variable to TARGET_MIPS64, remove unused t2/fp0] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>Aleksandar Markovic2020-10-171-23/+81
| | | | | | | | | Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602103041-32017-4-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>Aleksandar Markovic2020-10-171-17/+46
| | | | | | | | | Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602103041-32017-3-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>Aleksandar Markovic2020-10-171-21/+40
| | | | | | | | | Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602103041-32017-2-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Fix some comment spelling errorszhaolichang2020-10-173-7/+7
| | | | | | | | | | | There are many spelling errors in the comments in target/mips/. Use spellcheck to check the spelling errors. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* hw/core/clock: Add the clock_new helper functionLuc Michel2020-10-162-0/+28
| | | | | | | | | | | | | | | | This function creates a clock and parents it to another object with a given name. It calls clock_setup_canonical_path before returning the new clock. This function is useful to create clocks in devices when one doesn't want to expose it at the qdev level (as an input or an output). Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201010135759.437903-4-luc@lmichel.fr> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* hw/qdev-clock: Display error hint when clock is missing from devicePhilippe Mathieu-Daudé2020-10-161-0/+11
| | | | | | | | | | | | Instead of directly aborting, display a hint to help the developer figure out the problem (likely trying to connect a clock to a device pre-dating the Clock API, thus not expecting clocks). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20201012095804.3335117-4-f4bug@amsat.org>
* util/cutils: Introduce freq_to_str() to display Hertz unitsPhilippe Mathieu-Daudé2020-10-162-0/+26
| | | | | | | | | | | Introduce freq_to_str() to convert frequency values in human friendly units using the SI units for Hertz. Suggested-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-Id: <20201012095804.3335117-2-f4bug@amsat.org>
* Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell2020-10-1613-162/+339
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block layer patches: - qemu-storage-daemon: Remove QemuOpts from --object parser - monitor: Fix order in monitor_cleanup() - Deprecate the sheepdog block driver # gpg: Signature made Thu 15 Oct 2020 15:48:10 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: block: deprecate the sheepdog block driver block: drop moderated sheepdog mailing list from MAINTAINERS file monitor: Fix order in monitor_cleanup() qemu-storage-daemon: Remove QemuOpts from --object parser qom: Add user_creatable_print_help_from_qdict() qom: Factor out helpers from user_creatable_print_help() keyval: Parse help options keyval: Fix parsing of ',' in value of implied key test-keyval: Demonstrate misparse of ',' with implied key keyval: Fix and clarify grammar Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * block: deprecate the sheepdog block driverDaniel P. Berrangé2020-10-153-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This thread from a little over a year ago: http://lists.wpkg.org/pipermail/sheepdog/2019-March/thread.html states that sheepdog is no longer actively developed. The only mentioned users are some companies who are said to have it for legacy reasons with plans to replace it by Ceph. There is talk about cutting out existing features to turn it into a simple demo of how to write a distributed block service. There is no evidence of anyone working on that idea: https://github.com/sheepdog/sheepdog/commits/master No real commits to git since Jan 2018, and before then just some minor technical debt cleanup. There is essentially no activity on the mailing list aside from patches to QEMU that get CC'd due to our MAINTAINERS entry. Fedora packages for sheepdog failed to build from upstream source because of the more strict linker that no longer merges duplicate global symbols. Fedora patches it to add the missing "extern" annotations and presumably other distros do to, but upstream source remains broken. There is only basic compile testing, no functional testing of the driver. Since there are no build pre-requisites the sheepdog driver is currently enabled unconditionally. This would result in configure issuing a deprecation warning by default for all users. Thus the configure default is changed to disable it, requiring users to pass --enable-sheepdog to build the driver. Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20201002113243.2347710-3-berrange@redhat.com> Reviewed-by: Neal Gompa <ngompa13@gmail.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * block: drop moderated sheepdog mailing list from MAINTAINERS fileDaniel P. Berrangé2020-10-151-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sheepdog mailing list is setup to stop and queue messages from non-subscribers, pending moderator approval. Unfortunately it seems that the moderation queue is not actively dealt with. Even when messages are approved, the sender is never added to the whitelist, so every future mail from the same sender continues to get stopped for moderation. MAINTAINERS entries should be responsive and not unneccessarily block mails from QEMU contributors, so drop the sheepdog mailing list. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20201002113243.2347710-2-berrange@redhat.com> Reviewed-by: Neal Gompa <ngompa13@gmail.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * monitor: Fix order in monitor_cleanup()Kevin Wolf2020-10-151-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can only destroy Monitor objects after we're sure that they are not in use by the dispatcher coroutine any more. This fixes crashes like the following where we tried to destroy a monitor mutex while the dispatcher coroutine still holds it: (gdb) bt #0 0x00007fe541cf4bc5 in raise () at /lib64/libc.so.6 #1 0x00007fe541cdd8a4 in abort () at /lib64/libc.so.6 #2 0x000055c24e965327 in error_exit (err=16, msg=0x55c24eead3a0 <__func__.33> "qemu_mutex_destroy") at ../util/qemu-thread-posix.c:37 #3 0x000055c24e9654c3 in qemu_mutex_destroy (mutex=0x55c25133e0f0) at ../util/qemu-thread-posix.c:70 #4 0x000055c24e7cfaf1 in monitor_data_destroy_qmp (mon=0x55c25133dfd0) at ../monitor/qmp.c:439 #5 0x000055c24e7d23bc in monitor_data_destroy (mon=0x55c25133dfd0) at ../monitor/monitor.c:615 #6 0x000055c24e7d253a in monitor_cleanup () at ../monitor/monitor.c:644 #7 0x000055c24e6cb002 in qemu_cleanup () at ../softmmu/vl.c:4549 #8 0x000055c24e0d259b in main (argc=24, argv=0x7ffff66b0d58, envp=0x7ffff66b0e20) at ../softmmu/main.c:51 Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20201013125027.41003-1-kwolf@redhat.com> Tested-by: Ben Widawsky <ben.widawsky@intel.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * qemu-storage-daemon: Remove QemuOpts from --object parserKevin Wolf2020-10-151-11/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command line parser for --object parses the input twice: Once into QemuOpts just for detecting help options, and then again into a QDict using the keyval parser for actually creating the object. Now that the keyval parser can also detect help options, we can simplify this and remove the QemuOpts part. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201007164903.282198-5-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * qom: Add user_creatable_print_help_from_qdict()Kevin Wolf2020-10-152-3/+27
| | | | | | | | | | | | | | | | | | | | | | This adds a function that, given a QDict of non-help options, prints help for user creatable objects. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201007164903.282198-4-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * qom: Factor out helpers from user_creatable_print_help()Kevin Wolf2020-10-151-38/+52
| | | | | | | | | | | | | | | | | | | | | | | | This creates separate helper functions for printing a list of user creatable object types and for printing a list of properties of a given type. This will allow using these parts without having a QemuOpts. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201007164903.282198-3-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * keyval: Parse help optionsKevin Wolf2020-10-156-78/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a special meaning for 'help' and '?' as options to the keyval parser. Instead of being an error (because of a missing value) or a value for an implied key, they now request help, which is a new boolean output of the parser in addition to the QDict. A new parameter 'p_help' is added to keyval_parse() that contains on return whether help was requested. If NULL is passed, requesting help results in an error and all other cases work like before. Turning previous error cases into help is a compatible extension. The behaviour potentially changes for implied keys: They could previously get 'help' as their value, which is now interpreted as requesting help. This is not a problem in practice because 'help' and '?' are not a valid values for the implied key of any option parsed with keyval_parse(): * audiodev: union Audiodev, implied key "driver" is enum AudiodevDriver, "help" and "?" are not among its values * display: union DisplayOptions, implied key "type" is enum DisplayType, "help" and "?" are not among its values * blockdev: union BlockdevOptions, implied key "driver is enum BlockdevDriver, "help" and "?" are not among its values * export: union BlockExport, implied key "type" is enum BlockExportType, "help" and "?" are not among its values * monitor: struct MonitorOptions, implied key "mode" is enum MonitorMode, "help" and "?" are not among its values * nbd-server: struct NbdServerOptions, no implied key. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201011073505.1185335-5-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * keyval: Fix parsing of ',' in value of implied keyMarkus Armbruster2020-10-152-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous commit demonstrated documentation and code disagree on parsing of ',' in the value of an implied key. Fix the code to match the documentation. This breaks uses of keyval_parse() that pass an implied key and accept a value containing ','. None of the existing uses does: * audiodev: implied key "driver" is enum AudiodevDriver, none of the values contains ',' * display: implied key "type" is enum DisplayType, none of the values contains ',' * blockdev: implied key "driver is enum BlockdevDriver, none of the values contains ',' * export: implied key "type" is enum BlockExportType, none of the values contains ',' * monitor: implied key "mode" is enum MonitorMode, none of the values contains ',' * nbd-server: no implied key. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201011073505.1185335-4-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * test-keyval: Demonstrate misparse of ',' with implied keyMarkus Armbruster2020-10-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add a test for "val,,ue" with implied key. Documentation says this should parse as implied key with value "val", then fail. The code parses it as implied key with value "val,ue", then succeeds. The next commit will fix it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201011073505.1185335-3-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * keyval: Fix and clarify grammarMarkus Armbruster2020-10-151-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The grammar has a few issues: * key-fragment = / [^=,.]* / Prose restricts key fragments: they "must be valid QAPI names or consist only of decimal digits". Technically, '' consists only of decimal digits. The code rejects that. Fix the grammar. * val = { / [^,]* / | ',,' } Use + instead of *. Accepts the same language. * val-no-key = / [^=,]* / The code rejects an empty value. Fix the grammar. * Section "Additional syntax for use with an implied key" is confusing. Rewrite it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20201011073505.1185335-2-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2020-10-1514-70/+68Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/kraxel/tags/modules-20201015-pull-request' into staging modules: misc fixes & tweaks. modules: build spice chardevs as module. # gpg: Signature made Thu 15 Oct 2020 13:53:03 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/modules-20201015-pull-request: chardev/spice: build spice chardevs as module meson: add spice dependency to core spice source files. meson: add spice_headers dependency. chardev/spice: simplify chardev setup chardev/spice: make qemu_chr_open_spice_port static ui/spice-app: don't use qemu_chr_open_spice_port directly modules: update qom object module comment module: silence errors for module_load_qom_all(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | chardev/spice: build spice chardevs as moduleGerd Hoffmann2020-10-152-1/+8
| | | | | | | | | | | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20201014121120.13482-8-kraxel@redhat.com
| * | meson: add spice dependency to core spice source files.Gerd Hoffmann2020-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now it happens to work by pure luck because the spice chardevs add the spice dependency to the softmmu source set. That'll change though once we start building spice chardevs as module, so lets fix it properly. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20201014121120.13482-7-kraxel@redhat.com
| * | meson: add spice_headers dependency.Gerd Hoffmann2020-10-153-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Used for files which (with CONFIG_SPICE=y) depend on spice header files to pick up some enum, but which do not depend on on the actual spice shared library. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20201014121120.13482-6-kraxel@redhat.com
| * | chardev/spice: simplify chardev setupGerd Hoffmann2020-10-156-39/+20Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize spice before chardevs. That allows to register the spice chardevs directly in the init function and removes the need to maintain a linked list of chardevs just for registration. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20201014121120.13482-5-kraxel@redhat.com
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