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* libqtest: add qtest_socket_server()Stefan Hajnoczi2021-03-082-17/+31
| | | | | | | | | | | | | | Add an API that returns a new UNIX domain socket in the listen state. The code for this was already there but only used internally in init_socket(). This new API will be used by vhost-user-blk-test. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20210223144653.811468-3-stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* vhost-user-blk: fix blkcfg->num_queues endiannessStefan Hajnoczi2021-03-081-4/+3Star
| | | | | | | | | | | | | | | | | | Treat the num_queues field as virtio-endian. On big-endian hosts the vhost-user-blk num_queues field was in the wrong endianness. Move the blkcfg.num_queues store operation from realize to vhost_user_blk_update_config() so feature negotiation has finished and we know the endianness of the device. VIRTIO 1.0 devices are little-endian, but in case someone wants to use legacy VIRTIO we support all endianness cases. Cc: qemu-stable@nongnu.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20210223144653.811468-2-stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* docs: replace insecure /tmp examples in qsd docsStefan Hajnoczi2021-03-081-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | World-writeable directories have security issues. Avoid showing them in the documentation since someone might accidentally use them in situations where they are insecure. There tend to be 3 security problems: 1. Denial of service. An adversary may be able to create the file beforehand, consume all space/inodes, etc to sabotage us. 2. Impersonation. An adversary may be able to create a listen socket and accept incoming connections that were meant for us. 3. Unauthenticated client access. An adversary may be able to connect to us if we did not set the uid/gid and permissions correctly. These can be prevented or mitigated with private /tmp, carefully setting the umask, etc but that requires special action and does not apply to all situations. Just avoid using /tmp in examples. Reported-by: Richard W.M. Jones <rjones@redhat.com> Reported-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20210301172728.135331-3-stefanha@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* docs: show how to spawn qemu-storage-daemon with fd passingStefan Hajnoczi2021-03-081-2/+40
| | | | | | | | | | | | | | | | | | | | | | | The QMP monitor, NBD server, and vhost-user-blk export all support file descriptor passing. This is a useful technique because it allows the parent process to spawn and wait for qemu-storage-daemon without busy waiting, which may delay startup due to arbitrary sleep() calls. This Python example is inspired by the test case written for libnbd by Richard W.M. Jones <rjones@redhat.com>: https://gitlab.com/nbdkit/libnbd/-/commit/89113f484effb0e6c322314ba75c1cbe07a04543 Thanks to Daniel P. Berrangé <berrange@redhat.com> for suggestions on how to get this working. Now let's document it! Reported-by: Richard W.M. Jones <rjones@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20210301172728.135331-2-stefanha@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qemu-storage-daemon: add --pidfile optionStefan Hajnoczi2021-03-082-0/+50
| | | | | | | | | | | | | | | | | Daemons often have a --pidfile option where the pid is written to a file so that scripts can stop the daemon by sending a signal. The pid file also acts as a lock to prevent multiple instances of the daemon from launching for a given pid file. QEMU, qemu-nbd, qemu-ga, virtiofsd, and qemu-pr-helper all support the --pidfile option. Add it to qemu-storage-daemon too. Reported-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20210302142746.170535-1-stefanha@redhat.com> Reviewed-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* storage-daemon: include current command line option in the errorsPaolo Bonzini2021-03-081-2/+17
| | | | | | | | | | | | | | | | | | | | Use the location management facilities that the emulator uses, so that the current command line option appears in the error message. Before: $ storage-daemon/qemu-storage-daemon --nbd key..= qemu-storage-daemon: Invalid parameter 'key..' After: $ storage-daemon/qemu-storage-daemon --nbd key..= qemu-storage-daemon: --nbd key..=: Invalid parameter 'key..' Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210301152844.291799-3-pbonzini@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* storage-daemon: report unexpected arguments on the flyPaolo Bonzini2021-03-081-5/+4Star
| | | | | | | | | | | | If the first character of optstring is '-', then each nonoption argv element is handled as if it were the argument of an option with character code 1. This removes the reordering of the argv array, and enables usage of loc_set_cmdline to provide better error messages. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210301152844.291799-2-pbonzini@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* blockjob: report a better error messageStefano Garzarella2021-03-081-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When a block job fails, we report strerror(-job->job.ret) error message, also if the job set an error object. Let's report a better error message using error_get_pretty(job->job.err). If an error object was not set, strerror(-job->ret) is used as fallback, as explained in include/qemu/job.h: typedef struct Job { ... /** * Error object for a failed job. * If job->ret is nonzero and an error object was not set, it will be set * to strerror(-job->ret) during job_completed. */ Error *err; } In block_job_query() there can be a transient where 'job.err' is not set by a scheduled bottom half. In that case we use strerror(-job->ret) as it was before. Suggested-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20210225103633.76746-1-sgarzare@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* iotests: Fix up python style in 300Eric Blake2021-03-081-4/+6
| | | | | | | | | | | | | | | Break some long lines, and relax our type hints to be more generic to any JSON, in order to more easily permit the additional JSON depth now possible in migration parameters. Detected by iotest 297. Fixes: ca4bfec41d56 (qemu-iotests: 300: Add test case for modifying persistence of bitmap) Reported-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20210215220518.1745469-1-eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* iotests/283: Check that finalize drops backup-topMax Reitz2021-03-082-0/+68
| | | | | | | | | | | | | | | | | | | | | | Without any of HEAD^ or HEAD^^ applied, qemu will most likely crash on the qemu-io invocation, for a variety of immediate reasons. The underlying problem is generally a use-after-free access into backup-top's BlockCopyState. With only HEAD^ applied, qemu-io will run into an EIO (which is not capture by the output, but you can see that the qemu-io invocation will be accepted (i.e., qemu-io will run) in contrast to the reference output, where the node name cannot be found), and qemu will then crash in query-named-block-nodes: bdrv_get_allocated_file_size() detects backup-top to be a filter and passes the request through to its child. However, after bdrv_backup_top_drop(), that child is NULL, so the recursive call crashes. With HEAD^^ applied, this test should pass. Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210219153348.41861-4-mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* backup-top: Refuse I/O in inactive stateMax Reitz2021-03-081-0/+10
| | | | | | | | | | | | | | | | | | | When the backup-top node transitions from active to inactive in bdrv_backup_top_drop(), the BlockCopyState is freed and the filtered child is removed, so the node effectively becomes unusable. However, noone told its I/O functions this, so they will happily continue accessing bs->backing and s->bcs. Prevent that by aborting early when s->active is false. (After the preceding patch, the node should be gone after bdrv_backup_top_drop(), so this should largely be a theoretical problem. But still, better to be safe than sorry, and also I think it just makes sense to check s->active in the I/O functions.) Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210219153348.41861-3-mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* backup: Remove nodes from job in .clean()Max Reitz2021-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | The block job holds a reference to the backup-top node (because it is passed as the main job BDS to block_job_create()). Therefore, bdrv_backup_top_drop() cannot delete the backup-top node (replacing it by its child does not affect the job parent, because that has .stay_at_node set). That is a problem, because all of its I/O functions assume the BlockCopyState (s->bcs) to be valid and that it has a filtered child; but after bdrv_backup_top_drop(), neither of those things are true. It does not make sense to add new parents to backup-top after backup_clean(), so we should detach it from the job before bdrv_backup_top_drop(). Because there is no function to do that for a single node, just detach all of the job's nodes -- the job does not do anything past backup_clean() anyway. Signed-off-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210219153348.41861-2-mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* iotests: Drop deprecated 'props' from object-addAlberto Garcia2021-03-089-29/+19Star
| | | | | | Signed-off-by: Alberto Garcia <berto@igalia.com> Message-Id: <20210222115737.2993-1-berto@igalia.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2021-03-0848-619/+3109
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210308' into staging target-arm queue: * sbsa-ref: remove cortex-a53 from list of supported cpus * sbsa-ref: add 'max' to list of allowed cpus * target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe * npcm7xx: add EMC model * xlnx-zynqmp: Remove obsolete 'has_rpu' property * target/arm: Speed up aarch64 TBL/TBX * virtio-mmio: improve virtio-mmio get_dev_path alog * target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks * target/arm: Restrict v8M IDAU to TCG * target/arm/cpu: Update coding style to make checkpatch.pl happy * musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces * Add new board: mps3-an524 # gpg: Signature made Mon 08 Mar 2021 11:56:24 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210308: (49 commits) hw/arm/mps2: Update old infocenter.arm.com URLs docs/system/arm/mps2.rst: Document the new mps3-an524 board hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 hw/arm/mps2-tz: Stub out USB controller for mps3-an524 hw/arm/mps2-tz: Add new mps3-an524 board hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo hw/arm/mps2-tz: Support ROMs as well as RAMs hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data hw/arm/mps2-tz: Make RAM arrangement board-specific hw/arm/mps2-tz: Allow boards to have different PPCInfo data hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs hw/arm/mps2-tz: Move device IRQ info to data structures hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 hw/arm/mps2-tz: Make number of IRQs board-specific hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board hw/misc/mps2-fpgaio: Support SWITCH register hw/misc/mps2-fpgaio: Make number of LEDs configurable by board ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/mps2: Update old infocenter.arm.com URLsPeter Maydell2021-03-0814-20/+19Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Update old infocenter.arm.com URLs to the equivalent developer.arm.com ones (the old URLs should redirect, but we might as well avoid the redirection notice, and the new URLs are pleasantly shorter). This commit covers the links to the MPS2 board TRM, the various Application Notes, the IoTKit and SSE-200 documents. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-25-peter.maydell@linaro.org
| * docs/system/arm/mps2.rst: Document the new mps3-an524 boardPeter Maydell2021-03-081-6/+18
| | | | | | | | | | | | | | | | | | Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-24-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524Peter Maydell2021-03-081-2/+20
| | | | | | | | | | | | | | | | | | | | The AN524 has a PL031 RTC, which we have a model of; provide it rather than an unimplemented-device stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-23-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Stub out USB controller for mps3-an524Peter Maydell2021-03-081-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AN524 has a USB controller (an ISP1763); we don't have a model of it but we should provide a stub "unimplemented-device" for it. This is slightly complicated because the USB controller shares a PPC port with the ethernet controller. Implement a make_* function which provides creates a container MemoryRegion with both the ethernet controller and an unimplemented-device stub for the USB controller. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-22-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Add new mps3-an524 boardPeter Maydell2021-03-061-4/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the mps3-an524 board; this is an SSE-200 based FPGA image, like the existing mps2-an521. It has a usefully larger amount of RAM, and a PL031 RTC, as well as some more minor differences. In real hardware this image runs on a newer generation of the FPGA board, the MPS3 rather than the older MPS2. Architecturally the two boards are similar, so we implement the MPS3 boards in the mps2-tz.c file as variations of the existing MPS2 boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-21-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfoPeter Maydell2021-03-061-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The armv7m_load_kernel() function takes a mem_size argument which it expects to be the size of the memory region at guest address 0. (It uses this argument only as a limit on how large a raw image file it can load at address zero). Instead of hardcoding this value, find the RAMInfo corresponding to the 0 address and extract its size. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-20-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Support ROMs as well as RAMsPeter Maydell2021-03-061-0/+6
| | | | | | | | | | | | | | | | | | The AN505 and AN521 don't have any read-only memory, but the AN524 does; add a flag to ROMInfo to mark a region as ROM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-19-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo dataPeter Maydell2021-03-061-2/+22
| | | | | | | | | | | | | | | | | | | | | | Instead of hardcoding the MachineClass default_ram_size and default_ram_id fields, set them on class creation by finding the entry in the RAMInfo array which is marked as being the QEMU system RAM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-18-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Make RAM arrangement board-specificPeter Maydell2021-03-061-37/+138
| | | | | | | | | | | | | | | | | | | | The AN505 and AN521 have the same layout of RAM; the AN524 does not. Replace the current hard-coding of where the RAM is and which parts of it are behind which MPCs with a data-driven approach. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-17-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Allow boards to have different PPCInfo dataPeter Maydell2021-03-061-2/+14
| | | | | | | | | | | | | | | | | | | | The AN505 and AN521 have the same device layout, but the AN524 is somewhat different. Allow for more than one PPCInfo array, which can be selected based on the board type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-16-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTsPeter Maydell2021-03-061-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We create an OR gate to wire together the overflow IRQs for all the UARTs on the board; this has to have twice the number of inputs as there are UARTs, since each UART feeds it a TX overflow and an RX overflow interrupt line. Replace the hardcoded '10' with a calculation based on the size of the uart[] array in the MPS2TZMachineState. (We rely on OR gate inputs that are never wired up or asserted being treated as always-zero.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-15-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Move device IRQ info to data structuresPeter Maydell2021-03-061-27/+25Star
| | | | | | | | | | | | | | | | | | | | | | Move the specification of the IRQ information for the uart, ethernet, dma and spi devices to the data structures. (The other devices handled by the PPCPortInfo structures don't have any interrupt lines we need to wire up.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-14-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interruptsPeter Maydell2021-03-061-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mps2-tz code uses PPCPortInfo data structures to define what devices are present and how they are wired up. Currently we use these to specify device types and addresses, but hard-code the interrupt line wiring in each make_* helper function. This works for the two boards we have at the moment, but the AN524 has some devices with different interrupt assignments. This commit adds the framework to allow PPCPortInfo structures to specify interrupt numbers. We add an array of interrupt numbers to the PPCPortInfo struct, and pass it through to the make_* helpers. The following commit will change the make_* helpers over to using the framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-13-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPIPeter Maydell2021-03-061-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the MPS2 boards, the first 32 interrupt lines are entirely internal to the SSE; interrupt lines for devices outside the SSE start at 32. In the application notes that document each FPGA image, the interrupt wiring is documented from the point of view of the CPU, so '0' is the first of the SSE's interrupts and the devices in the FPGA image itself are '32' and up: so the UART 0 Receive interrupt is 32, the SPI #0 interrupt is 51, and so on. Within our implementation, because the external interrupts must be connected to the EXP_IRQ[0...n] lines of the SSE object, we made the get_sse_irq_in() function take an irqno whose values start at 0 for the first FPGA device interrupt. In this numbering scheme the UART 0 Receive interrupt is 0, the SPI #0 interrupt is 19, and so on. The result of these two different numbering schemes has been that half of the devices were wired up to the wrong IRQs: the UART IRQs are wired up correctly, but the DMA and SPI devices were passing start-at-32 values to get_sse_irq_in() and so being mis-connected. Fix the bug by making get_sse_irq_in() take values specified with the same scheme that the hardware manuals use, to avoid confusion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-12-peter.maydell@linaro.org
| * hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524Peter Maydell2021-03-062-2/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AN524 version of the SCC interface has different behaviour for some of the CFG registers; implement it. Each board in this family can have minor differences in the meaning of the CFG registers, so rather than trying to specify all the possible semantics via individual device properties, we make the behaviour conditional on the part-number field of the SCC_ID register which the board code already passes us. For the AN524, the differences are: * CFG3 is reserved rather than being board switches * CFG5 is a new register ("ACLK Frequency in Hz") * CFG6 is a new register ("Clock divider for BRAM") We implement both of the new registers as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-11-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Make number of IRQs board-specificPeter Maydell2021-03-061-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AN524 has more interrupt lines than the AN505 and AN521; make numirq board-specific rather than a compile-time constant. Since the difference is small (92 on the current boards and 95 on the new one) we don't dynamically allocate the cpu_irq_splitter[] array but leave it as a fixed length array whose size is the maximum needed for any of the boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-10-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board typePeter Maydell2021-03-061-10/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the mps2-tz board code, we handle devices whose interrupt lines must be wired to all CPUs by creating IRQ splitter devices for the AN521, because it has 2 CPUs, but wiring the device IRQ directly to the SSE/IoTKit input for the AN505, which has only 1 CPU. We can avoid making an explicit check on the board type constant by instead creating and using the IRQ splitters for any board with more than 1 CPU. This avoids having to add extra cases to the conditionals every time we add new boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-9-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Make FPGAIO switch and LED config per-boardPeter Maydell2021-03-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Set the FPGAIO num-leds and have-switches properties explicitly per-board, rather than relying on the defaults. The AN505 and AN521 both have the same settings as the default values, but the AN524 will be different. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-8-peter.maydell@linaro.org
| * hw/misc/mps2-fpgaio: Support SWITCH registerPeter Maydell2021-03-062-0/+11
| | | | | | | | | | | | | | | | | | | | | | MPS3 boards have an extra SWITCH register in the FPGAIO block which reports the value of some switches. Implement this, governed by a property the board code can use to specify whether whether it exists. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-7-peter.maydell@linaro.org
| * hw/misc/mps2-fpgaio: Make number of LEDs configurable by boardPeter Maydell2021-03-062-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The FPGAIO device is similar on both sets of boards, but the LED0 register has correspondingly more bits that have an effect. Add a device property for number of LEDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-6-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-boardPeter Maydell2021-03-061-5/+18
| | | | | | | | | | | | | | | | | | | | | | The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-5-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511Peter Maydell2021-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | We were previously using the default OSCCLK settings, which are correct for the older MPS2 boards (mps2-an385, mps2-an386, mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 implemented in mps2-tz.c. Now we're setting the values explicitly we can fix them to be correct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-4-peter.maydell@linaro.org
| * hw/misc/mps2-scc: Support configurable number of OSCCLK valuesPeter Maydell2021-03-064-15/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the MPS2 SCC device implements a fixed number of OSCCLK values (3). The variant of this device in the MPS3 AN524 board has 6 OSCCLK values. Switch to using a PROP_ARRAY, which allows board code to specify how large the OSCCLK array should be as well as its values. With a variable-length property array, the SCC no longer specifies default values for the OSCCLKs, so we must set them explicitly in the board code. This defaults are actually incorrect for the an521 and an505; we will correct this bug in a following patch. This is a migration compatibility break for all the mps boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-3-peter.maydell@linaro.org
| * hw/arm/mps2-tz: Make SYSCLK frequency board-specificPeter Maydell2021-03-061-4/+6
| | | | | | | | | | | | | | | | | | | | | | The AN524 has a different SYSCLK frequency from the AN505 and AN521; make the SYSCLK frequency a field in the MPS2TZMachineClass rather than a compile-time constant so we can support the AN524. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-2-peter.maydell@linaro.org
| * hw/display/tcx: Drop unnecessary code for handling BGR format outputsPeter Maydell2021-03-061-23/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel, RGB. The TCX code already assumes 32bpp, but it still has some checks of is_surface_bgr() in an attempt to support 32bpp BGR. is_surface_bgr() will always return false for the qemu_console_surface(), unless the display device itself has deliberately created an alternate-format surface via a function like qemu_create_displaysurface_from(). Drop the never-used BGR-handling code, and assert that we have a 32-bit surface rather than just doing nothing if it isn't. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215102149.20513-1-peter.maydell@linaro.org
| * hw/display/omap_lcdc: Delete unnecessary macroPeter Maydell2021-03-061-3/+1Star
| | | | | | | | | | | | | | | | | | The macro draw_line_func is used only once; just expand it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-10-peter.maydell@linaro.org
| * hw/display/omap_lcdc: Inline template header into C filePeter Maydell2021-03-062-156/+125Star
| | | | | | | | | | | | | | | | | | | | We only include the template header once, so just inline it into the source file for the device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-9-peter.maydell@linaro.org
| * hw/display/omap_lcdc: Fix coding style issues in template headerPeter Maydell2021-03-061-3/+3
| | | | | | | | | | | | | | | | | | | | Fix some minor coding style issues in the template header, so checkpatch doesn't complain when we move the code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-8-peter.maydell@linaro.org
| * hw/display/omap_lcdc: Drop broken bigendian ifdefPeter Maydell2021-03-061-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The draw_line16_32() function in the omap_lcdc template header includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches TARGET_WORDS_BIGENDIAN. This is trying to optimise for "source bitmap and destination bitmap format match", but it is broken, because in this function the formats don't match: the source is 16-bit colour and the destination is 32-bit colour, so a memcpy() will produce corrupted graphics output. Drop the bogus ifdef. This bug was introduced in commit ea644cf343129, when we dropped support for DEPTH values other than 32 from the template header. The old #if line was #if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) and this was mistakenly changed to #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) rather than deleting the #if as now having an always-false condition. Fixes: ea644cf343129 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-7-peter.maydell@linaro.org
| * hw/display/omap_lcdc: Expand out macros in template headerPeter Maydell2021-03-061-39/+28Star
| | | | | | | | | | | | | | | | | | | | | | The omap_lcdc template header is already only included once, for DEPTH==32, but it still has all the macro-driven parameterization for other depths. Expand out all the macros in the header. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-6-peter.maydell@linaro.org
| * hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsitePeter Maydell2021-03-062-49/+19Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The function tc6393xb_draw_graphic32() is called in exactly one place, so just inline the function body at its callsite. This allows us to drop the template header entirely. The code move includes a single added space after 'for' to fix the coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-5-peter.maydell@linaro.org
| * hw/display/tc6393xb: Expand out macros in template headerPeter Maydell2021-03-061-31/+4Star
| | | | | | | | | | | | | | | | | | Now the template header is included only for BITS==32, expand out all the macros that depended on the BITS setting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-4-peter.maydell@linaro.org
| * hw/display/tc6393xb: Remove dead code for handling non-32bpp surfacesPeter Maydell2021-03-051-32/+1Star
| | | | | | | | | | | | | | | | | | | | | | For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the tc6393xb display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-3-peter.maydell@linaro.org
| * hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfacesPeter Maydell2021-03-051-40/+24Star
| | | | | | | | | | | | | | | | | | | | | | For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the milkymist display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-2-peter.maydell@linaro.org
| * target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé2021-03-051-4/+8
| | | | | | | | | | | | | | | | | | | | We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210221222617.2579610-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Restrict v8M IDAU to TCGPhilippe Mathieu-Daudé2021-03-052-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | IDAU is specific to M-profile. KVM only supports A-profile. Restrict this interface to TCG, as it is pointless (and confusing) on a KVM-only build. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210221222617.2579610-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 15:55:33 +0100