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* spapr_hcall: Fix little-endian resource handling in H_SET_MODEAlexey Kardashevskiy2014-03-202-10/+40
| | | | | | | | | | | | | | This changes resource code definitions to ones used in the host kernel. This fixes H_SET_MODE_RESOURCE_LE (switch between big endian and little endian) to sync registers from KVM before changing LPCR value. This adds a set_spr() helper to update an SPR in a CPU's context to avoid possible races and makes use of it to change LPCR. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Introduce powerisa-207-server flagAlexey Kardashevskiy2014-03-202-1/+4
| | | | | | | | | | | | This flag will be used to decide whether to emulate some bits of H_SET_MODE hypercall because some are POWER8-only. While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already have it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Force CPU threads count to be a power of 2Bharata B Rao2014-03-201-0/+6
| | | | | | | | | | | | | | PowerPC kernel expects the number of SMT threads in a core to be a power of 2. Since QEMU doesn't enforce this, it leads to an early guest kernel crash if invalid threads count is specified. Prevent this crash and make it a graceful exit from QEMU itself by validating the user-supplied threads count. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Fix overallocation of opcode tablesStuart Brady2014-03-201-1/+1
| | | | | | | | | | create_new_table() should allocate 0x20 opc_handler_t pointers, but actually allocates 0x20 opc_handler_t structs. Fix this. Signed-off-by: Stuart Brady <sdb@zubnet.me.uk> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Reset SPRs on CPU resetAlexey Kardashevskiy2014-03-202-1/+12
| | | | | | | | | This resets SPR values to defaults on CPU reset. This should help with little-endian guests reboot issues. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* spapr_hcall: Fix h_enter to loop correctlyAneesh Kumar K.V2014-03-201-6/+5Star
| | | | | | | | | | | We wanted to loop till index is 8. On 8 we return with H_PTEG_FULL. If we are successful in loading hpte with any other index, we continue with that index value. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Add missing 'static' and 'const' attributesStefan Weil2014-03-193-6/+6
| | | | | | | This fixes warnings from the static code analysis (smatch). Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
* Merge remote-tracking branch 'remotes/riku/linux-user-for-upstream' into stagingPeter Maydell2014-03-195-35/+236
|\ | | | | | | | | | | | | | | | | | | | | | | | | * remotes/riku/linux-user-for-upstream: linux-user: Implement capget, capset linux-user: Don't allow guest to block SIGSEGV signal: added a wrapper for sigprocmask function linux-user: Don't reserve space for commpage for AArch64 linux-user: implement F_[GS]ETOWN_EX linux-user: Don't return uninitialized value for atomic_barrier syscall linux-user/signal.c: Correct error path for AArch64 do_rt_sigreturn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * linux-user: Implement capget, capsetPeter Maydell2014-03-172-2/+84
| | | | | | | | | | | | | | | | | | Implement the capget and capset syscalls. This is useful because simple programs like 'ls' try to use it in AArch64, and otherwise we emit a lot of noise about it being unimplemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
| * linux-user: Don't allow guest to block SIGSEGVPeter Maydell2014-03-172-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't allow the linux-user guest to block SIGSEGV -- QEMU needs this signal to detect accesses to pages which it has marked read-only because it has cached translated code from them. We implement this by making the do_sigprocmask() wrapper suppress SIGSEGV when doing the host process signal mask manipulation; instead we store the current state of SIGSEGV in the TaskState struct. If we get a SIGSEGV for the guest when the guest has blocked the signal, we treat it as if the default SEGV handler was in place, as the kernel does for forced SIGSEGV delivery. This patch is based on an idea by Alex Barcelo, but rather than simply lying to the guest about the SIGSEGV state we track it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Alex Barcelo <abarcelo@ac.upc.edu> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
| * signal: added a wrapper for sigprocmask functionAlex Barcelo2014-03-173-31/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a wrapper for signal mask changes initiated by the guest; (this includes syscalls and also the sigreturns from signal.c) this will give us a place to put code which prevents the guest from changing the handling of signals used by QEMU itself internally. The wrapper is called from all the guest-initiated sigprocmask, but is not called from internal qemu sigprocmask calls. Signed-off-by: Alex Barcelo <abarcelo@ac.upc.edu> [PMM: Added calls to wrapper for sigprocmask uses in signal.c when setting the signal mask on entry and exit from signal handlers, since these also are guest-provided signal masks.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
| * linux-user: Don't reserve space for commpage for AArch64Peter Maydell2014-03-171-1/+4
| | | | | | | | | | | | | | | | | | | | AArch64 Linux, unlike AArch32, doesn't use a commpage. This means we should not be reserving room in the guest address space for one. Fixes LP:1287195. Reported-by: Amanieu d'Antras <amanieu@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
| * linux-user: implement F_[GS]ETOWN_EXAndreas Schwab2014-03-172-0/+43
| | | | | | | | | | | | | | F_GETOWN is replaced by F_GETOWN_EX inside the glibc fcntl wrapper Signed-off-by: Andreas Schwab <schwab@suse.de> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
| * linux-user: Don't return uninitialized value for atomic_barrier syscallPeter Maydell2014-03-171-0/+1
| | | | | | | | | | | | | | | | QEMU's implementation of the m68k atomic_barrier syscall, like the kernel's, is just a no-op. However we still need to return a result code from it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
| * linux-user/signal.c: Correct error path for AArch64 do_rt_sigreturnPeter Maydell2014-03-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | The error path in AArch64 do_rt_sigreturn() which fails before attempting lock_user_struct() was doing an unlock_user_struct() on an uninitialized variable. Initialize frame to NULL so we can use the same error-exit path in all cases (unlock of NULL is permitted and does nothing). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell2014-03-1913-41/+107
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block patches for 2.0.0-rc1 # gpg: Signature made Wed 19 Mar 2014 13:03:27 GMT using RSA key ID C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" * remotes/kevin/tags/for-upstream: dataplane: fix implicit IOThread refcount block/nfs: report errors from libnfs block/nfs: bump libnfs requirement to 1.9.3 qcow2: Fix fail path in realloc_refcount_block() qcow2: Correct comment for realloc_refcount_block() qemu-io: Extended "--cmd" description in usage text qemu-io-cmds: Fixed typo in example for writev. block: Add error handling to bdrv_invalidate_cache() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | dataplane: fix implicit IOThread refcountStefan Hajnoczi2014-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating an IOThread implicitly (the user did not specify x-iothread=<id>) remember that iothread_find() does not return the object with an incremented refcount. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | block/nfs: report errors from libnfsPeter Lieven2014-03-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | if an NFS operation fails we should report what libnfs knows about the failure. It is likely more than just an error code. Signed-off-by: Peter Lieven <pl@kamp.de> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | block/nfs: bump libnfs requirement to 1.9.3Peter Lieven2014-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | libnfs prior to 1.9.3 contains a bug that will report wrong transfer sizes if the file offset grows beyond 4GB and RPC responses are received out of order. this error is not detectable and fixable in qemu. additionally 1.9.3 introduces support for handling short read/writes in general and takes care of the necessary retransmissions internally. Signed-off-by: Peter Lieven <pl@kamp.de> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | qcow2: Fix fail path in realloc_refcount_block()Max Reitz2014-03-191-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If qcow2_alloc_clusters() fails, new_offset and ret will both be negative after the fail label, thus passing the first if condition and subsequently resulting in a call of qcow2_free_clusters() with an invalid (negative) offset parameter. Fix this by introducing a new label "fail_free_cluster" which is only invoked if new_offset is indeed pointing to a newly allocated cluster that should be cleaned up by freeing it. While we're at it, clean up the whole fail path. qcow2_cache_put() should (and actually can) never fail, hence the return value can safely be ignored (aside from asserting that it indeed did not fail). Furthermore, there is no reason to give QCOW2_DISCARD_ALWAYS to qcow2_free_clusters(), a mere QCOW2_DISCARD_OTHER will suffice. Ultimately, rename the "fail" label to "done", as it is invoked both on failure and success. Suggested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | qcow2: Correct comment for realloc_refcount_block()Max Reitz2014-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Contrary to the comment describing this function's behavior, it does not return 0 on success, but rather the offset of the newly allocated cluster. This patch adjusts the comment accordingly to reflect the actual behavior. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | qemu-io: Extended "--cmd" description in usage textMaria Kustova2014-03-191-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not clear from the usage description that "--cmd" option accepts its argument as a string, so any special symbols have to be quoted from the shell. Updates in usage text: - Specified parameter format for "--cmd" option. - Added an instruction how to get help for "--cmd" option. Signed-off-by: Maria Kustova <maria.k@catit.be> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | qemu-io-cmds: Fixed typo in example for writev.Maria Kustova2014-03-191-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Maria Kustova <maria.k@catit.be> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * | block: Add error handling to bdrv_invalidate_cache()Kevin Wolf2014-03-197-18/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If it returns an error, the migrated VM will not be started, but qemu exits with an error message. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Benoit Canet <benoit@irqsave.net>
* | | Merge remote-tracking branch ↵Peter Maydell2014-03-195-35/+383
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20140319' into staging target-arm queue: * last few A64 Neon instructions * fix some PL011 UART bugs causing occasional serial lockups * fix the non-PCI AHCI device # gpg: Signature made Wed 19 Mar 2014 12:00:59 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140319: target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD) target-arm: A64: Add saturating int ops (SQNEG/SQABS) pl011: fix incorrect logic to set the RXFF flag pl011: fix UARTRSR accesses corrupting the UARTCR value pl011: reset the fifo when enabled or disabled ahci: fix sysbus support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée2014-03-193-10/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the saturating accumulate operations USQADD and SUQADD to the A64 instruction set. This completes coverage of A64 Neon. These operations (which are unsigned + signed -> signed and signed + unsigned -> unsigned) don't exist in the A32/T32 instruction set, so require a complete new set of helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * | target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée2014-03-193-12/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This mostly re-uses the existing NEON helpers with an additional two for the 64 bit case. I also took the opportunity to add TCG_CALL_NO_RWG options to the helpers as they don't modify globals (saturation flags are in the CPU Environment). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
| * | pl011: fix incorrect logic to set the RXFF flagRob Herring2014-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The receive fifo full bit should be set when 1 character is received and the fifo is disabled or when 16 characters are in the fifo. Signed-off-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1395166721-15716-4-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | pl011: fix UARTRSR accesses corrupting the UARTCR valueRob Herring2014-03-181-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be corrupted if the UARTRSR is ever written. Fix by implementing a correct model of the UARTRSR/UARTECR register. Reads of this register simply reflect the error bits in data register. Only breaks can be triggered in QEMU. With the pl011_can_receive function, we effectively have flow control between the host and the model. Framing and parity errors simply don't make sense in the model and will never occur. Signed-off-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1395166721-15716-3-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | pl011: reset the fifo when enabled or disabledRob Herring2014-03-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intermittent issues have been seen where no serial input occurs. It appears the pl011 gets in a state where the rx interrupt never fires because the rx interrupt only asserts when crossing the fifo trigger level. The fifo state appears to get out of sync when the pl011 is re-configured. This combined with the rx timeout interrupt not being modeled results in no more rx interrupts. Disabling the fifo is the recommended way to clear the tx fifo in the TRM (section 3.3.8). The behavior in this case for the rx fifo is undefined in the TRM, but having fifo contents to be maintained during configuration changes is not likely expected behavior. Reseting the fifo state when the fifo size is changed is the simplest solution. Signed-off-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1395166721-15716-2-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ahci: fix sysbus supportRob Herring2014-03-181-5/+8
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Non-PCI AHCI support is broken due to assertion failures when trying to convert AHCIState to a PCIDevice pointer as AHCIState can have different container structs. Fix this by using the non-asserting object cast and checking the returned pointer is not NULL. The AddressSpace pointer is also being initialized to NULL and causing dma_memory_map call to fail. Fix this by initializing to address_space_memory for sysbus instances. Also correct AHCI_VMSTATE to use the correct container SysbusAHCIState for sysbus instances. Signed-off-by: Rob Herring <rob.herring@linaro.org> Message-id: 1392073373-3295-1-git-send-email-robherring2@gmail.com [PMM: added linebreaks to fix overlong lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-2' into stagingPeter Maydell2014-03-182-4/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vnc: fix vmware VGA incompatiblities # gpg: Signature made Tue 18 Mar 2014 07:23:10 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vnc-2: ui/vnc: fix vmware VGA incompatiblities Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ui/vnc: fix vmware VGA incompatiblitiesPeter Lieven2014-03-182-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this fixes invalid rectangle updates observed after commit 12b316d with the vmware VGA driver. The issues occured because the server and client surface update seems to be out of sync at some points and the max width of the surface is not dividable by VNC_DIRTY_BITS_PER_PIXEL (16). Reported-by: Serge Hallyn <serge.hallyn@ubuntu.com> Signed-off-by: Peter Lieven <pl@kamp.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | | Merge remote-tracking branch ↵Peter Maydell2014-03-1815-263/+1855
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20140317' into staging target-arm queue: * more A64 Neon instructions * fixes to reset CBAR values for A9 and A15 boards * fix accesses to PMCR register in -icount mode # gpg: Signature made Mon 17 Mar 2014 22:04:52 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140317: (30 commits) scripts/qemu-binfmt-conf.sh: Add AArch64 registration target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) target-arm: A64: Implement FCVTXN target-arm: A64: Implement scalar saturating narrow ops target-arm: A64: Move handle_2misc_narrow function target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE softfloat: export squash_input_denormal functions target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder target-arm: A64: Implement FRINT* target-arm: A64: Implement SRI target-arm: A64: Add FRECPX (reciprocal exponent) target-arm: A64: List unsupported shift-imm opcodes target-arm: A64: Implement FCVTL target-arm: A64: Implement FCVTN target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions target-arm: A64: Implement SHLL, SHLL2 target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP target-arm: A64: Saturating and narrowing shift ops ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | scripts/qemu-binfmt-conf.sh: Add AArch64 registrationPeter Maydell2014-03-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the binfmt-misc magic needed to register QEMU for handling AArch64 ELF binaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-26-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée2014-03-174-37/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-arm: A64: Implement FCVTXNPeter Maydell2014-03-173-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the FCVTXN operation, which does a narrowing fp precision conversion using the "round to odd" (von Neumann) mode. This can conveniently be implemented as "do operation using round to zero; then set the LSB of the mantissa to 1 if the Inexact flag was set". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-24-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Implement scalar saturating narrow opsAlex Bennée2014-03-171-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Move handle_2misc_narrow functionAlex Bennée2014-03-171-90/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the handle_2misc_narrow() function up the file so that it can be called from disas_simd_scalar_two_reg_misc(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-22-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée2014-03-174-42/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
| * | softfloat: export squash_input_denormal functionsAlex Bennée2014-03-172-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I need these available outside of softfloat for some of the reciprocal processing in aarch64 helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-20-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell2014-03-171-2/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-19-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell2014-03-171-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the saturating left shift instructions SQSHL, SQSHLU and UQSHL for the scalar-shift-imm and shift-imm categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-18-git-send-email-peter.maydell@linaro.org
| * | exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell2014-03-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Implement FRINT*Peter Maydell2014-03-171-3/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the FRINT* round-to-integral operations from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-16-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Implement SRIPeter Maydell2014-03-171-8/+49
| | | | | | | | | | | | | | | | | | | | | | | | Implement SRI (shift right and insert). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-15-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée2014-03-173-1/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | These are fairly simple exponent only estimation functions using helpers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-14-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: List unsupported shift-imm opcodesPeter Maydell2014-03-171-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Implement FCVTLPeter Maydell2014-03-171-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement FCVTL, the only instruction in the 2-reg-misc group which widens from size to 2*size elements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-12-git-send-email-peter.maydell@linaro.org
| * | target-arm: A64: Implement FCVTNPeter Maydell2014-03-171-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-11-git-send-email-peter.maydell@linaro.org
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-09 09:46:47 +0100