summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* linux-user: Provide new force_sig_fault() functionPeter Maydell2021-09-232-0/+18
* linux-user: Zero out target_siginfo_t in force_sig()Peter Maydell2021-09-231-1/+1
* linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPEPeter Maydell2021-09-231-7/+4Star
* linux-user/arm: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell2021-09-231-0/+1
* linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell2021-09-231-0/+1
* Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson2021-09-2134-669/+1844
|\
| * hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis2021-09-211-1/+1
| * target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-212-16/+16
| * target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang2021-09-211-1/+2
| * docs/system/riscv: sifive_u: Update U-Boot instructionsBin Meng2021-09-201-23/+26
| * hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang2021-09-201-6/+6
| * hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan2021-09-201-6/+10
| * hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang2021-09-201-0/+9
| * hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang2021-09-201-0/+19
| * hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-203-1/+124
| * hw/riscv: virt: Re-factor FDT generationAnup Patel2021-09-201-200/+327
| * hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-208-156/+339
| * hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-2011-15/+15
| * sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-204-2/+69
| * hw/timer: Add SiFive PWM supportAlistair Francis2021-09-205-0/+540
| * hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2021-09-203-5/+17
| * hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-207-12/+33
| * hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-203-11/+16
| * hw/intc: sifive_clint: Use RISC-V CPU GPIO linesAlistair Francis2021-09-202-20/+50
| * target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis2021-09-201-0/+30
| * target/riscv: Fix satp writeLIU Zhiwei2021-09-201-1/+1
| * target/riscv: Update the ePMP CSR addressAlistair Francis2021-09-202-2/+3
* | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...Peter Maydell2021-09-2124-168/+1825
|\ \
| * | target/arm: Optimize MVE 1op-immediate insnsPeter Maydell2021-09-211-5/+21
| * | target/arm: Optimize MVE VSLI and VSRIPeter Maydell2021-09-211-2/+2
| * | target/arm: Optimize MVE VSHLL and VMOVLPeter Maydell2021-09-211-8/+59
| * | target/arm: Optimize MVE VSHL, VSHR immediate formsPeter Maydell2021-09-211-20/+63
| * | target/arm: Optimize MVE VMVNPeter Maydell2021-09-211-1/+1
| * | target/arm: Optimize MVE VDUPPeter Maydell2021-09-211-4/+8
| * | target/arm: Optimize MVE VNEG, VABSPeter Maydell2021-09-211-10/+22
| * | target/arm: Optimize MVE arithmetic opsPeter Maydell2021-09-211-9/+11
| * | target/arm: Optimize MVE logic opsPeter Maydell2021-09-211-15/+36
| * | target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell2021-09-217-9/+92
| * | target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migrationPeter Maydell2021-09-211-0/+13
| * | target/arm: Avoid goto_tb if we're trying to exit to the main loopPeter Maydell2021-09-211-1/+33
| * | hvf: arm: Add rudimentary PMC supportAlexander Graf2021-09-211-0/+179
| * | arm: Add Hypervisor.framework build targetAlexander Graf2021-09-213-0/+12
| * | hvf: arm: Implement PSCI handlingAlexander Graf2021-09-213-7/+139
| * | hvf: arm: Implement -cpu hostPeter Maydell2021-09-215-6/+124
| * | arm/hvf: Add a WFI handlerPeter Collingbourne2021-09-213-3/+82
| * | hvf: Add Apple Silicon supportAlexander Graf2021-09-207-1/+834
| * | hvf: Introduce hvf_arch_init() callbackAlexander Graf2021-09-203-1/+8
| * | hvf: Add execute to dirty log permission bitmapAlexander Graf2021-09-201-2/+2
| * | arm: Move PMC register definitions to internals.hAlexander Graf2021-09-202-44/+44
| * | hw/intc: Set GIC maintenance interrupt level to only 0 or 1Shashi Mallela2021-09-201-2/+3
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-06-16 03:39:07 +0200