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| * | hw/timer: Add value matching support to aspeed_timerAndrew Jeffery2016-06-172-39/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the palmetto-bmc machine. Two match registers are provided for each timer. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1465974248-20434-1-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target-arm/monitor.c: Advertise emulated GICv3 in capabilitiesPeter Maydell2016-06-171-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have an emulated GICv3 we should advertise it via the capabilities in the monitor protocol. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-21-git-send-email-peter.maydell@linaro.org
| * | target-arm/machine.c: Allow user to request GICv3 emulationPeter Maydell2016-06-171-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have an emulated GICv3, remove the restriction in gicv3_class_name() so that the user can request a GICv3 with -machine gic-version=3 even when not using KVM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-20-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Add IRQ handling CPU interface registersPeter Maydell2016-06-173-0/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the CPU interface registers which deal with acknowledging and dismissing interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-19-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Implement CPU i/f SGI generation registersPeter Maydell2016-06-174-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the registers in the GICv3 CPU interface which generate new SGI interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-18-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Implement gicv3_cpuif_update()Peter Maydell2016-06-173-5/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the gicv3_cpuif_update() function which deals with correctly asserting IRQ and FIQ based on the current running priority of the CPU, the priority of the highest priority pending interrupt and the CPU's current exception level and security state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-17-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Implement GICv3 CPU interface registersPeter Maydell2016-06-175-0/+666
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the CPU interface registers for the GICv3; these are CPU system registers, not MMIO registers. This commit implements all the registers which are simple accessors for GIC state, but not those which act as interfaces for acknowledging, dismissing or generating interrupts. (Those will be added in a later commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-16-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Implement gicv3_set_irq()Peter Maydell2016-06-175-1/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the code which updates the GIC state when an interrupt input into the GIC is asserted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-15-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regionsPeter Maydell2016-06-171-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire up the MMIO functions exposed by the distributor and the redistributor into MMIO regions exposed by the GICv3 device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-14-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Implement GICv3 redistributor registersShlomo Pongratz2016-06-174-0/+512
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the redistributor registers of a GICv3. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-13-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled/rewritten: * use the new data structures * restructure register read/write to handle different width accesses natively, since almost all registers are 32-bit only, rather than implementing everything as byte accesses * implemented security extension support ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/intc/arm_gicv3: Implement GICv3 distributor registersShlomo Pongratz2016-06-174-0/+869
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the distributor registers of a GICv3. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-12-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled/rewritten: * use the new bitmap data structures * restructure register read/write to handle different width accesses natively, since almost all registers are 32-bit only, rather than implementing everything as byte accesses * implemented security extension support ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/intc/arm_gicv3: Implement functions to identify next pending irqPeter Maydell2016-06-174-0/+441
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the GICv3 logic to recalculate the highest priority pending interrupt for each CPU after some part of the GIC state has changed. We avoid unnecessary full recalculation where possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-11-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: ARM GICv3 device frameworkShlomo Pongratz2016-06-174-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the device class itself, some ID register value functions which will be needed by both distributor and redistributor, and some skeleton functions for handling interrupts coming in and going out, which will be filled in in a subsequent patch. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-10-git-send-email-peter.maydell@linaro.org [PMM: pulled this patch earlier in the sequence, and left some code out of it for a later patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
| * | hw/intc/arm_gicv3: Add vmstate descriptorsPavel Fedin2016-06-172-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add state structure descriptors for the GICv3 state. We mark the KVM GICv3 device as having a migration blocker until the code to save and restore the state in the kernel is implemented. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-9-git-send-email-peter.maydell@linaro.org [PMM: Adjust to renamed struct fields; switched to using uint32_t array backed bitmaps; add migration blocker setting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structurePeter Maydell2016-06-172-8/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the GICv3 parent_irq and parent_fiq pointers into the GICv3CPUState structure rather than giving them their own array. This will make it easy to assert the IRQ and FIQ lines for a particular CPU interface without having to know or calculate the CPU index for the GICv3CPUState we are working on. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-8-git-send-email-peter.maydell@linaro.org
| * | hw/intc/arm_gicv3: Add state informationPavel Fedin2016-06-173-5/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add state information to GICv3 object structure and implement arm_gicv3_common_reset(). This commit includes accessor functions for the fields which are stored as bitmaps in uint32_t arrays. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-7-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled: * Add missing qom/cpu.h include * Remove legacy-only state fields (we can add them later if/when we add legacy emulation) * Use arrays of uint32_t to store the various distributor bitmaps, and provide accessor functions for the various set/test/etc operations * Add various missing register offset #defines * Accessor macros which combine distributor and redistributor behaviour removed * Fields in state structures renamed to match architectural register names * Corrected the reset value for GICR_IENABLER0 since we don't support legacy mode * Added ARM_LINUX_BOOT_IF interface for "we are directly booting a kernel in non-secure" so that we can fake up the firmware-mandated reconfiguration only when we need it ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
| * | target-arm: Add mp-affinity property for ARM CPU classPavel Fedin2016-06-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows to override default affinity IDs on a per-machine basis, and possibility to retrieve IDs will be used by vGICv3 live migration code. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-6-git-send-email-peter.maydell@linaro.org
| * | target-arm: Provide hook to tell GICv3 about changes of security statePeter Maydell2016-06-175-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv3 CPU interface needs to know when the CPU it is attached to makes an exception level or mode transition that changes the security state, because whether it is asserting IRQ or FIQ can change depending on these things. Provide a mechanism for letting the GICv3 device register a hook to be called on such changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-5-git-send-email-peter.maydell@linaro.org
| * | target-arm: Define new arm_is_el3_or_mon() functionPeter Maydell2016-06-171-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv3 system registers need to know if the CPU is AArch64 in EL3 or AArch32 in Monitor mode. This happens to be the first part of the check for arm_is_secure(), so factor it out into a new arm_is_el3_or_mon() function that the GIC can also use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-4-git-send-email-peter.maydell@linaro.org
| * | bitops.h: Implement half-shuffle and half-unshuffle opsPeter Maydell2016-06-172-0/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A half-shuffle operation takes a word with zeros in the high half: 0000 0000 0000 0000 ABCD EFGH IJKL MNOP and spreads the bits out so they are in every other bit of the word: 0A0B 0C0D 0E0F 0G0H 0I0J 0K0L 0M0N 0O0P A half-unshuffle performs the reverse operation. Provide functions in bitops.h which implement these operations for 32-bit and 64-bit inputs, and add tests for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-3-git-send-email-peter.maydell@linaro.org
| * | migration: Define VMSTATE_UINT64_2DARRAYPeter Maydell2016-06-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a VMSTATE_UINT64_2DARRAY macro, to go with the ones we already have for other type sizes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-2-git-send-email-peter.maydell@linaro.org
* | | Merge remote-tracking branch 'remotes/ehabkost/tags/machine-pull-request' ↵Peter Maydell2016-06-173-8/+10
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Machine queue, 2016-06-17 # gpg: Signature made Fri 17 Jun 2016 14:45:48 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-pull-request: vnc: Wrap vnc initialization code with CONFIG_VNC qdev: Use GList for global properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | vnc: Wrap vnc initialization code with CONFIG_VNCChao Peng2016-06-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit f8c75b2486 (vnc: Initialization stubs) removed CONFIG_VNC in vl.c code. However qemu_find_opts("vnc") is NULL when vnc is configured out. Crash will happen in qemu_opts_foreach() before stub vnc_init_func() is called. This patch add it back. Cc: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * | | qdev: Use GList for global propertiesEduardo Habkost2016-06-172-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the same GlobalProperty struct is registered twice, the list entry gets corrupted, making tqe_next points to itself, and qdev_prop_set_globals() gets stuck in a loop. The bug can be easily reproduced by running: $ qemu-system-x86_64 -rtc-td-hack -rtc-td-hack Change global_props to use GList instead of queue.h, making the code simpler and able to deal with properties being registered twice. Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | | | nbd/client.c: Correct trace format stringPeter Maydell2016-06-171-1/+1
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | The trace format string in nbd_send_request uses PRIu16 for request->type, but request->type is a uint32_t. This provokes compiler warnings on the OSX clang. Use PRIu32 instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1466167331-17063-1-git-send-email-peter.maydell@linaro.org
* | | Merge remote-tracking branch ↵Peter Maydell2016-06-177-129/+191
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/amit-migration/tags/migration-for-2.7-5' into staging Migration: - many compression/decompression fixes - trace improvements - static checker fix for detecting size mismatch in unused fields - fix VM save after snapshot # gpg: Signature made Fri 17 Jun 2016 13:59:44 BST # gpg: using RSA key 0xEB0B4DFC657EF670 # gpg: Good signature from "Amit Shah <amit@amitshah.net>" # gpg: aka "Amit Shah <amit@kernel.org>" # gpg: aka "Amit Shah <amitshah@gmx.net>" # Primary key fingerprint: 48CA 3722 5FE7 F4A8 B337 2735 1E9A 3B5F 8540 83B6 # Subkey fingerprint: CC63 D332 AB8F 4617 4529 6534 EB0B 4DFC 657E F670 * remotes/amit-migration/tags/migration-for-2.7-5: vmstate-static-checker: fix size mismatch detection in unused fields migration: code clean up migration: refine the decompression code migration: refine the compression code migration: protect the quit flag by lock migration: refine ram_save_compressed_page qemu-file: Fix qemu_put_compression_data flaw migration: remove useless code migration: Fix a potential issue migration: Fix multi-thread compression bug migration: fix inability to save VM after snapshot migration: Trace improvements migration: Don't use *_to_cpup() and cpu_to_*w() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | vmstate-static-checker: fix size mismatch detection in unused fieldsAmit Shah2016-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a field changed from something to unused, the checker wasn't flagging if the field size mismatched. This was noticed in: http://thread.gmane.org/gmane.comp.emulators.qemu/419802 where the 4->1 size change along with field name change to 'unused' wasn't being flagged. Fix this. Signed-off-by: Amit Shah <amit.shah@redhat.com> Message-Id: <d7ec03a9b2edfa0616764887a51ba8f64fdd3f68.1466165736.git.amit.shah@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: code clean upLiang Li2016-06-171-21/+15Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use 'QemuMutex comp_done_lock' and 'QemuCond comp_done_cond' instead of 'QemuMutex *comp_done_lock' and 'QemuCond comp_done_cond'. To keep consistent with 'QemuMutex decomp_done_lock' and 'QemuCond comp_done_cond'. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-10-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: refine the decompression codeLiang Li2016-06-171-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code for multi-thread decompression is not clear, especially in the aspect of using lock. Refine the code to make it clear. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-9-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: refine the compression codeLiang Li2016-06-171-44/+40Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code for multi-thread compression is not clear, especially in the aspect of using lock. Refine the code to make it clear. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-8-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: protect the quit flag by lockLiang Li2016-06-171-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | quit_comp_thread and quit_decomp_thread are accessed by several thread, it's better to protect them with locks. We use a per thread flag to replace the global one, and the new flag is protected by a lock. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-7-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: refine ram_save_compressed_pageLiang Li2016-06-171-14/+13Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use qemu_put_compression_data to do the compression directly instead of using do_compress_ram_page, avoid some data copy. very small improvement, at the same time, add code to check if the compression is successful. Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-6-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | qemu-file: Fix qemu_put_compression_data flawLiang Li2016-06-172-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current qemu_put_compression_data can only work with no writable QEMUFile, and can't work with the writable QEMUFile. But it does not provide any measure to prevent users from using it with a writable QEMUFile. We should fix this flaw to make it works with writable QEMUFile. Signed-off-by: Liang Li <liang.z.li@intel.com> Suggested-by: Juan Quintela <quintela@redhat.com> Message-Id: <1462433579-13691-5-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: remove useless codeLiang Li2016-06-171-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | page_buffer is set twice repeatedly, remove the previous set. Signed-off-by: Liang Li <liang.z.li@intel.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <1462433579-13691-4-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: Fix a potential issueLiang Li2016-06-171-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the end of live migration and before vm_start() on the destination side, we should make sure all the decompression tasks are finished, if this can not be guaranteed, the VM may get the incorrect memory data, or the updated memory may be overwritten by the decompression thread. Add the code to fix this potential issue. Suggested-by: David Alan Gilbert <dgilbert@redhat.com> Suggested-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-3-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: Fix multi-thread compression bugLiang Li2016-06-171-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently, a bug related to multiple thread compression feature for live migration is reported. The destination side will be blocked during live migration if there are heavy workload in host and memory intensive workload in guest, this is most likely to happen when there is one decompression thread. Some parts of the decompression code are incorrect: 1. The main thread receives data from source side will enter a busy loop to wait for a free decompression thread. 2. A lock is needed to protect the decomp_param[idx]->start, because it is checked in the main thread and is updated in the decompression thread. Fix these two issues by following the code pattern for compression. Signed-off-by: Liang Li <liang.z.li@intel.com> Reported-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Tested-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Liang Li <liang.z.li@intel.com> Message-Id: <1462433579-13691-2-git-send-email-liang.z.li@intel.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: fix inability to save VM after snapshotDenis V. Lunev2016-06-171-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following sequence of operations fails: virsh start vm virsh snapshot-create vm virshh save vm --file file with the following error error: Failed to save domain vm to file error: internal error: unable to execute QEMU command 'migrate': There's a migration process in progress The problem is that qemu_savevm_state() calls migrate_init() which sets migration state to MIGRATION_STATUS_SETUP and never cleaned it up. This patch do the job. Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Amit Shah <amit.shah@redhat.com> Message-Id: <1466003203-26263-1-git-send-email-den@openvz.org> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: Trace improvementsDr. David Alan Gilbert2016-06-172-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A couple of improvements to tracing that have come out of helping people with migration problems: * vmstate_n_elems trace the count/name - for when you have problems getting array counts right * vmstate_subsection_load_bad - add the idstr, for when you receive a subsection you weren't expecting. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <1465896986-16132-1-git-send-email-dgilbert@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
| * | migration: Don't use *_to_cpup() and cpu_to_*w()Peter Maydell2016-06-172-8/+8
|/ / | | | | | | | | | | | | | | | | | | | | | | | | The *_to_cpup() and cpu_to_*w() functions just compose a pointer dereference with a byteswap. Instead use ld*_p() and st*_p(), which handle potential pointer misalignment and avoid the need to cast the pointer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1465574962-2710-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Amit Shah <amit.shah@redhat.com>
* | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160617' ↵Peter Maydell2016-06-1733-90/+1169
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ppc patch queue for 2016-06-17 Here's the current accumulated set of spapr, ppc and related patches. * The big thing in here is CPU hotplug for spapr - This includes a number of acked generic changes adding new infrastructure for hotplugging cpu cores * A number of TCG bug fixes are also included * This adds a new testcase to make it harder to accidentally break Macintosh (and other openbios) platforms # gpg: Signature made Fri 17 Jun 2016 07:35:29 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160617: spapr: implement query-hotpluggable-cpus callback hmp: Add 'info hotpluggable-cpus' HMP command QMP: Add query-hotpluggable-cpus spapr: CPU hot unplug support spapr: CPU hotplug support spapr: convert boot CPUs into CPU core devices spapr: Move spapr_cpu_init() to spapr_cpu_core.c spapr: Abstract CPU core device and type specific core devices qom: API to get instance_size of a type spapr_drc: Prevent detach racing against attach for CPU DR xics,xics_kvm: Handle CPU unplug correctly cpu: Abstract CPU core type qdev: hotplug: Introduce HotplugHandler.pre_plug() callback target-ppc: Fix rlwimi, rlwinm, rlwnm vfio: Fix broken EEH target-ppc: Bug in BookE wait instruction ppc / sparc: Add a tester for checking whether OpenBIOS runs successfully hw/ppc/spapr: Silence deprecation message in qtest mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | spapr: implement query-hotpluggable-cpus callbackIgor Mammedov2016-06-171-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It returns a list of present/possible to hotplug CPU objects with a list of properties to use with device_add. in spapr case returned list would looks like: -> { "execute": "query-hotpluggable-cpus" } <- {"return": [ { "props": { "core": 8 }, "type": "POWER8-spapr-cpu-core", "vcpus-count": 2 }, { "props": { "core": 0 }, "type": "POWER8-spapr-cpu-core", "vcpus-count": 2, "qom-path": "/machine/unattached/device[0]"} ]}' TODO: add 'node' property for core <-> numa node mapping Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | hmp: Add 'info hotpluggable-cpus' HMP commandBharata B Rao2016-06-173-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is the HMP equivalent for QMP query-hotpluggable-cpus. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [dwg: Fixed problem with printf formats on 32-bit host] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | QMP: Add query-hotpluggable-cpusIgor Mammedov2016-06-174-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will allow mgmt to query present and hotpluggable CPU objects, it is required from a target platform that wishes to support command to implement and set MachineClass.query_hotpluggable_cpus callback, which will return a list of possible CPU objects with options that would be needed for hotplugging possible CPU objects. There are: 'type': 'str' - QOM CPU object type for usage with device_add 'vcpus-count': 'int' - number of logical VCPU threads per CPU object (mgmt needs to know) and a set of optional fields that are to used for hotplugging a CPU objects and would allows mgmt tools to know what/where it could be hotplugged; [node],[socket],[core],[thread] For present CPUs there is a 'qom-path' field which would allow mgmt to inspect whatever object/abstraction the target platform considers as CPU object. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr: CPU hot unplug supportBharata B Rao2016-06-173-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the CPU core device by removing the underlying CPU thread devices. Hot removal of CPU for sPAPR guests is achieved by sending the hot unplug notification to the guest. Release the vCPU object after CPU hot unplug so that vCPU fd can be parked and reused. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr: CPU hotplug supportBharata B Rao2016-06-176-13/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up device tree entries for the hotplugged CPU core and use the exising RTAS event logging infrastructure to send CPU hotplug notification to the guest. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr: convert boot CPUs into CPU core devicesBharata B Rao2016-06-174-10/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce sPAPRMachineClass.dr_cpu_enabled to indicate support for CPU core hotplug. Initialize boot time CPUs as core deivces and prevent topologies that result in partially filled cores. Both of these are done only if CPU core hotplug is supported. Note: An unrelated change in the call to xics_system_init() is done in this patch as it makes sense to use the local variable smt introduced in this patch instead of kvmppc_smt_threads() call here. TODO: We derive sPAPR core type by looking at -cpu <model>. However we don't take care of "compat=" feature yet for boot time as well as hotplug CPUs. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr: Move spapr_cpu_init() to spapr_cpu_core.cBharata B Rao2016-06-173-48/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Start consolidating CPU init related routines in spapr_cpu_core.c. As part of this, move spapr_cpu_init() and its dependencies from spapr.c to spapr_cpu_core.c No functionality change in this patch. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [dwg: Rename TIMEBASE_FREQ to SPAPR_TIMEBASE_FREQ, since it's now in a public(ish) header] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr: Abstract CPU core device and type specific core devicesBharata B Rao2016-06-176-2/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sPAPR specific abastract CPU core device that is based on generic CPU core device. Use this as base type to create sPAPR CPU specific core devices. TODO: - Add core types for other remaining CPU types - Handle CPU model alias correctly Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | qom: API to get instance_size of a typeBharata B Rao2016-06-172-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Add an API object_type_get_size(const char *typename) that returns the instance_size of the give typename. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr_drc: Prevent detach racing against attach for CPU DRBharata B Rao2016-06-172-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a CPU is hot removed while hotplug of the same is still in progress, the guest crashes. Prevent this by ensuring that detach is done only after attach has completed. The existing code already prevents such race for PCI hotplug. However given that CPU is a logical DR unlike PCI and starts with ISOLATED state, we need a logic that works for CPU too. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> [Don't set awaiting_attach for PCI devices] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-24 17:19:27 +0100