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* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-102-0/+17
| | | | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). For detailed instructions on how to create images for the Icicle Kit board, please check QEMU RISC-V WiKi page at: https://wiki.qemu.org/Documentation/Platforms/RISCV Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-102-0/+46
| | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we must specify 2 '-nic' options from the command line in order to get a working ethernet. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23Bin Meng2020-09-104-3/+7
| | | | | | | | | | | | | | When cadence_gem model was created for Xilinx boards, the PHY address was hard-coded to 23 in the GEM model. Now that we have introduced a property we can use that to tell GEM model what our PHY address is. Change all boards' GEM 'phy-addr' property value to 23, and set the PHY address default value to 0 in the GEM model. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/net: cadence_gem: Add a new 'phy-addr' propertyBin Meng2020-09-102-2/+5
| | | | | | | | | | | | | | At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-103-0/+27
| | | | | | | | | | | On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Let's connect a DMA controller to Microchip PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/dma: Add SiFive platform DMA controller emulationBin Meng2020-09-104-0/+374
| | | | | | | | | | | | | | Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-103-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=icicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/sd: Add Cadence SDHCI emulationBin Meng2020-09-104-0/+245
| | | | | | | | | | | | | | | | Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-103-0/+51
| | | | | | | | | | Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/char: Add Microchip PolarFire SoC MMUART emulationBin Meng2020-09-105-0/+153
| | | | | | | | | | | Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-106-0/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-104-5/+6
| | | | | | | | | | | | | Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: hart: Add a new 'resetvec' propertyBin Meng2020-09-102-0/+4
| | | | | | | | | | | | | RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2020-09-102-0/+2
| | | | | | | | | | | | | | | | | Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor2020-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When shutting down the machine running a mainline Linux kernel, the following error happens: $ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \ -display none -initrd rootfs.cpio -kernel Image -m 512m \ -nodefaults -serial mon:stdio ... Requesting system poweroff [ 4.999630] reboot: Power down sbi_trap_error: hart0: trap handler failed (error -2) sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000 sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822 sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78 sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0 sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040 sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024 sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024 sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555 sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158 sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000 sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000 sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000 sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000 sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008 sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000 sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000 sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000 sbi_trap_error: hart0: t6=0x0000000000000000 The kernel does a 16-bit write when powering off the machine, which was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid""). Make min_access_size match reality so that the machine can shut down properly now. Cc: qemu-stable@nongnu.org Fixes: 88a07990fa ("SiFive RISC-V Test Finisher") Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-103-2/+14
| | | | | | | | | | | | | | | When the cause number is equal to or greater than 23, print "(unknown)" in trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last excpetion "guest_store_page_fault" can not be printed. In addition, the current check of cause is invalid for riscv_intr_names. So introduce riscv_cpu_get_trap_name to get the trap cause name. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Merge remote-tracking branch ↵Peter Maydell2020-09-0810-2/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging ipxe: update to aug 2020 snapshot. # gpg: Signature made Tue 08 Sep 2020 07:09:26 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/sirius/ipxe-20200908-pull-request: ipxe: update binaries ipxe: drop ia32 efi roms ipxe: update submodule Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * ipxe: update binariesGerd Hoffmann2020-09-088-0/+0
| | | | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * ipxe: drop ia32 efi romsGerd Hoffmann2020-09-081-2/+0Star
| | | | | | | | | | | | | | | | UEFI on ia32 never really took off. Basically the BIOS -> UEFI shift came too late, x64 was widespread already, so vendors went from BIOS straight to UEFI on x64. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * ipxe: update submoduleGerd Hoffmann2020-09-081-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | master snapshot, most recent commit from Aug 23th shortlog ======== Andrew Grasso (1): [intel] Add INTEL_NO_PHY_RST for I218LM Ben Bleything (1): [intel] Set INTEL_NO_PHY_RST on i218v Bobby Lockwood (1): [libgcc] Change __divmoddi4 from int64 [unknown] to int64_t Bruce Rogers (1): [build] Be explicit about -fcommon compiler directive Christian Nilsson (1): [intel] Add PCI ID for I219-V and -LM 6 to 9 Daniel Johnson (1): [deflate] Fix typo in comment describing length codes David Decotigny (2): [pcbios] Fix "out of memory" detection when expanding bottom area [pcbios] Take alignment into account when checking for available space Dentcho Ludmilov Bankov (1): [comboot] Fix stack pointer retrieval after COM32 binary returns Ignat Korchagin (3): [snp] Try promiscuous multicast receive filter if the regular one fails [snp] Set EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST bit as per UEFI spec [efi] Check the status code from AllocatePool() Joe Groocock (1): [cmdline] Add "--timeout" parameter to "ifconf" command Joseph Wong (1): [bnxt] Add driver support for Broadcom NetXtreme-E Adapters LaDerrick H (1): [sfc] Add PCI ID for Solarflare SFC9120 and Solarflare SFC9140 Michael Brown (105): [init] Show startup and shutdown function names in debug messages [efi] Blacklist the Dell Ip4ConfigDxe driver [tls] Support stateful session resumption [tls] Fix incorrectly duplicated error number [tls] Support stateless session resumption [crypto] Use x509_name() in validator debug messages [tls] Display cross-certificate and OCSP status messages [tls] Display validator messages only while validation is in progress [tcp] Display "connecting" status until connection is established [ocsp] Accept response certID with missing hashAlgorithm parameters [pci] Add support for PCI MSI-X interrupts [vlan] Provide vlan_netdev_rx() and vlan_netdev_rx_err() [intelxl] Use VLAN tag in receive descriptor if present [intelxl] Allow for virtual function admin queue register maps [intelxl] Use one admin queue buffer per admin queue descriptor [intelxl] Allow admin queues to be reinitialised [intelxl] Allow admin cookie to hold extended opcode and return code [intelxl] Provide a mechanism for handling "send to VF" events [intelxl] Use 32-byte receive descriptors [intelxl] Allow for arbitrary placement of ring tail registers [intelxl] Split out ring creation from context programming [intelxl] Allow for arbitrary placement of interrupt control register [intelxl] Expose functions required by virtual function driver [intelxl] Choose to operate in non-PXE mode [intelxl] Add driver for Intel 40 Gigabit Ethernet NIC virtual functions [build] Fix use of inline assembly on GCC 8 ARM64 builds [arm] Provide dummy implementations for {in,out}[s]{b,w,l} [efi] Return only registered EFI devices from efidev_parent() [fdt] Add ability to parse a MAC address from a flattened device tree [efi] Register a device tree if provided by the platform firmware [smsc95xx] Fetch MAC from device tree for Raspberry Pi [build] Add named configuration for Raspberry Pi [smscusb] Fetch MAC from device tree for Raspberry Pi Model B+ [build] Do not apply WORKAROUND_CFLAGS for host compiler [build] Move predefined all-drivers build shortcut to Makefile [build] Add predefined shortcut for Raspberry Pi builds [process] Add PROC_INIT() for initialising static processes [peerdist] Start block download timers from within opener methods [peerdist] Limit number of concurrent raw block downloads [tls] Add missing call to tls_tx_resume() when restarting negotiation [crypto] Drag in configured digestInfo prefixes for any use of RSA [crypto] Profile the various stages of modular multiplication [coverity] Override assumptions about wcrtomb() and hmac_init() [ethernet] Avoid false positive Coverity warning [golan] Fix address-of-pointer bug for multicast attach/detach [efi] Report failed control transfers as expected by the USB core [efi] Do not attempt EFI_USB_IO_PROTOCOL transfers during shutdown [lan78xx] Always enable automatic speed and duplex detection [peerdist] Allow PeerDist to be globally enabled or disabled [peerdist] Allow for the use of a hosted cache server [build] Construct full version number automatically from git revision [travis] Ensure that most recent tag is always available [tftp] Eliminate unnecessary variable-length stack allocation [infiniband] Eliminate variable-length stack allocation [slam] Eliminate variable-length stack allocation [slam] Allow for the possibility of IPv6 multicast addresses [settings] Eliminate variable-length stack allocation [iscsi] Eliminate variable-length stack allocations in CHAP handlers [iscsi] Eliminate variable-length stack allocation in URI parsing [bios] Define macros for constructing partition table entries [int13con] Create log partition only when CONSOLE_INT13 is enabled [efi] Disambiguate errors returned by ConnectController [png] Fix potential integer overflow [efi] Work around UEFI specification bug in LoadImage [efi] Work around UEFI specification bug in LoadImage for SAN boot [uri] Avoid appearing to access final byte of a potentially empty string [efi] Attempt to connect our driver directly if ConnectController fails [tls] Allow a minimum TLS protocol version to be specified [tls] Default to supporting only TLSv1.1 or above [crypto] Allow algorithms to be included without being OID-identifiable [crypto] Ensure that test code drags in required ASN.1 object identifiers [crypto] Disable MD5 as an OID-identifiable algorithm by default [snp] Retry initialisation if link is reported as down [util] Treat empty integer strings as invalid [parseopt] Treat empty integer strings in user input as invalid [efi] Enable stack protection where possible [ocsp] Accept SHA1 certID responses even if SHA1 is not enabled [intel] Avoid spurious compiler warning on GCC 10 [golan] Add explicit type casts for nodnic_queue_pair_type [build] Disable position-independent code for ARM64 EFI builds [efi] Detect and disable seriously broken EFI_RNG_PROTOCOL implementations [efi] Raise TPL during driver entry point [axge] Handle non-gigabit link speeds [usb] Clear device endpoint halt before resetting host endpoint [usb] Add missing usb_recycle() for completed hub interrupt transfers [usb] Do not attempt to disable USB3 hub ports [xhci] Set link state to RxDetect after disabling USB3 root hub port [usb] Avoid unnecessary calls to usb_hub_set_drvdata() [xhci] Increase link state settling delay to 100ms [axge] Reapply USB device configuration when opening network device [usb] Leave port enabled after a failed device registration [crypto] Avoid temporarily setting direction flag in bigint_is_geq() [libc] Provide an unoptimised generic_memcpy_reverse() [efi] Avoid setting direction flag on EFI platforms [libc] Add bit-rotation functions for unsigned long values [efi] Distribute available entropy within stack cookie [efi] Ensure NUL byte is at lowest address within stack cookie [efi] Claim SNP devices early in efi_download_start() [xfer] Remove address family from definition of a socket opener [dns] Use all configured DNS servers [wpa] Fix erroneous debug message in wpa_derive_ptk [efi] Match EDK2 numbering for USB ports [efi] Use device path to locate filesystem from which we were loaded [efi] Attempt NII initialisation both with and without cable detection [build] Fix building on older versions of gcc Michael J. Bazzinotti (1): [libc] Fix memcmp() to return proper values Mohammed (1): [golan] Add various new PCI device IDs Rob Taglang (1): [intelx] Added PCI_ROM entry for Intel x553/x557-AT and x553 (SFP+) NICs Tobias Kortkamp (1): [build] Fix a GNUism that FreeBSD's sed(1) cannot deal with Valentine Barshak (2): [build] Fix "'%s' directive argument is null" error [build] Workaround compilation error with gcc 9.1 bit (1): [build] Fix default target in sdsk image Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2020-09-08' into ↵Peter Maydell2020-09-0813-89/+78Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging QAPI patches patches for 2020-09-08 # gpg: Signature made Tue 08 Sep 2020 07:06:52 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2020-09-08: qapi/block-core.json: Fix nbd-server-start docs qapi: Fix indentation, again qapi/migration.json: Fix indentation qapi: Make section headings start a new doc comment block qapi: Reject section markup in definition documentation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | qapi/block-core.json: Fix nbd-server-start docsPeter Maydell2020-09-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit eed8b6917832 added some new text to the nbd-server-start documentation in the wrong place. Since this is after the 'Returns:' line it's parsed as if it were part of the documentation of the "Returns:' information. Move it up to join the rest of the "documentation of the type as a whole" doc text. This doesn't look odd in the current HTML rendering, but the new QAPI-to-rST handling will complain about the indent level of the lines not matching up with the 'Returns:' line. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200810195019.25427-4-peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
| * | qapi: Fix indentation, againPeter Maydell2020-09-077-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 26ec4e53f2 and similar commits we fixed the indentation for doc comments in our qapi json files to follow a new stricter standard for indentation, which permits only: @arg: description line 1 description line 2 or: @arg: line 1 line 2 Unfortunately since we didn't manage to get the script changes that enforced the new style in, a variety of commits (eg df4097aeaf71, 2e4457032105) introduced new doc text which doesn't follow the new stricter rules for indentation on multi-line doc comments. Bring those into line with the new rules. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200810195019.25427-3-peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
| * | qapi/migration.json: Fix indentationPeter Maydell2020-09-071-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits 6a9ad1542065ca0bd54c6 and 9004db48c080632aef23 added some new text to qapi/migration.json which doesn't fit the stricter indentation requirements imposed by the rST documentation generator. Reindent those lines to the new standard. Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200810195019.25427-2-peter.maydell@linaro.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
| * | qapi: Make section headings start a new doc comment blockMarkus Armbruster2020-09-072-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our current QAPI doc-comment markup allows section headers (introduced with a leading '=' or '==') anywhere in a free-form documentation comment. This works for Texinfo because the generator simply prints a Texinfo section command at that point in the output stream. For rST generation, since we're assembling a tree of docutils nodes, this is awkward because a new section implies starting a new section node at the top level of the tree and generating text into there. Make section headers start a new free-form documentation block, so the future rST document generator doesn't have to look at every line in free-form blocks and handle headings in odd places. This change makes no difference to the generated Texinfo. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200320091805.5585-3-armbru@redhat.com>
| * | qapi: Reject section markup in definition documentationMarkus Armbruster2020-09-075-26/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Section markup in definition documentation makes no sense and can produce invalid Texinfo. Reject. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200320091805.5585-2-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
* | | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200908' ↵Peter Maydell2020-09-0833-313/+548
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ppc patch queue 2020-09-08 This supersedes ppc-for-5.2-20200904, it fixes a couple of bugs in that PR and adds a few extra patches. Next pull request for qemu-5.2. The biggest thing here is the generalization of ARM's start-powered-off machine property to all targets. This can fix a number of odd little edge cases where KVM could run vcpus before they were properly initialized. This does include changes to a number of files that aren't normally in my purview. There are suitable Acked-by lines and Peter requested this come in via my tree, since the most pressing requirement for it is in pseries machines with the POWER secure virtual machine facility. In addition we have: * Daniel Barboza's rework and clean up of pseries machine NUMA handling * Correction to behaviour of the nvdimm= generic machine property on pseries * An optimization to the allocation of XIVE interrupts on KVM * Some fixes for confused behaviour with kernel_irqchip when both XICS and XIVE are in play * Add HIOMAP comamnd to pnv flash * Properly advertise the fact that spapr_vscsi doesn't handle hotplugged disks * Some assorted minor enhancements # gpg: Signature made Tue 08 Sep 2020 06:19:34 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.2-20200908: (33 commits) spapr_numa: use spapr_numa_get_vcpu_assoc() in home_node hcall spapr_numa: create a vcpu associativity helper spapr: move h_home_node_associativity to spapr_numa.c spapr_numa: move NVLink2 associativity handling to spapr_numa.c spapr, spapr_numa: move lookup-arrays handling to spapr_numa.c spapr, spapr_numa: handle vcpu ibm,associativity spapr: introduce SpaprMachineState::numa_assoc_array ppc/spapr_nvdimm: turn spapr_dt_nvdimm() static ppc: introducing spapr_numa.c NUMA code helper hw/ppc/ppc4xx_pci: Replace pointless warning by assert() hw/ppc/ppc4xx_pci: Use ARRAY_SIZE() instead of magic value target/s390x: Use start-powered-off CPUState property sparc/sun4m: Use start-powered-off CPUState property sparc/sun4m: Don't set cs->halted = 0 in main_cpu_reset() mips/cps: Use start-powered-off CPUState property ppc/e500: Use start-powered-off CPUState property ppc/spapr: Use start-powered-off CPUState property target/arm: Move setting of CPU halted state to generic code target/arm: Move start-powered-off property to generic CPUState ppc/spapr_nvdimm: do not enable support with 'nvdimm=off' ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | spapr_numa: use spapr_numa_get_vcpu_assoc() in home_node hcallDaniel Henrique Barboza2020-09-081-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of h_home_node_associativity hard codes the values of associativity domains of the vcpus. Let's make it consider the values already initialized in spapr->numa_assoc_array, via the spapr_numa_get_vcpu_assoc() helper. We want to set it and forget it, and for that we also need to assert that we don't overflow the registers of the hypercall. >From R4 to R9 we can squeeze in 12 associativity domains for vcpus, so let's assert that VCPU_ASSOC_SIZE -1 isn't greater than that. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200904172422.617460-4-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr_numa: create a vcpu associativity helperDaniel Henrique Barboza2020-09-082-14/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The work to be done in h_home_node_associativity() intersects with what is already done in spapr_numa_fixup_cpu_dt(). This patch creates a new helper, spapr_numa_get_vcpu_assoc(), to be used for both spapr_numa_fixup_cpu_dt() and h_home_node_associativity(). While we're at it, use memcpy() instead of loop assignment to created the returned array. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200904172422.617460-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr: move h_home_node_associativity to spapr_numa.cDaniel Henrique Barboza2020-09-082-40/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation of this hypercall will be modified to use spapr->numa_assoc_arrays input. Moving it to spapr_numa.c makes make more sense. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200904172422.617460-2-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr_numa: move NVLink2 associativity handling to spapr_numa.cDaniel Henrique Barboza2020-09-082-18/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVLink2 GPUs works like a regular NUMA node with its own associativity values, regardless of user input. This can be handled inside spapr_numa_associativity_init(), initializing NVGPU_MAX_NUM associativity arrays that can be used by the GPUs. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200903220639.563090-5-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr, spapr_numa: move lookup-arrays handling to spapr_numa.cDaniel Henrique Barboza2020-09-083-23/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a similar fashion as the previous patch, let's move the handling of ibm,associativity-lookup-arrays from spapr.c to spapr_numa.c. A spapr_numa_write_assoc_lookup_arrays() helper was created, and spapr_dt_dynamic_reconfiguration_memory() can now use it to advertise the lookup-arrays. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200903220639.563090-4-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr, spapr_numa: handle vcpu ibm,associativityDaniel Henrique Barboza2020-09-083-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vcpus have an additional paramenter to be appended, vcpu_id. This also changes the size of the of property itself, which is being represented in index 0 of numa_assoc_array[cpu->node_id], and defaults to MAX_DISTANCE_REF_POINTS for all cases but vcpus. All this logic makes more sense in spapr_numa.c, where we handle everything NUMA and associativity. A new helper spapr_numa_fixup_cpu_dt() was added, and spapr.c uses it the same way as it was using the former spapr_fixup_cpu_numa_dt(). Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200903220639.563090-3-danielhb413@gmail.com> [dwg: Correct uint to int type, which can break windows builds] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr: introduce SpaprMachineState::numa_assoc_arrayDaniel Henrique Barboza2020-09-087-33/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next step to centralize all NUMA/associativity handling in the spapr machine is to create a 'one stop place' for all things ibm,associativity. This patch introduces numa_assoc_array, a 2 dimensional array that will store all ibm,associativity arrays of all NUMA nodes. This array is initialized in a new spapr_numa_associativity_init() function, called in spapr_machine_init(). It is being initialized with the same values used in other ibm,associativity properties around spapr files (i.e. all zeros, last value is node_id). The idea is to remove all hardcoded definitions and FDT writes of ibm,associativity arrays, doing instead a call to the new helper spapr_numa_write_associativity_dt() helper, that will be able to write the DT with the correct values. We'll start small, handling the trivial cases first. The remaining instances of ibm,associativity will be handled next. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200903220639.563090-2-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | ppc/spapr_nvdimm: turn spapr_dt_nvdimm() staticDaniel Henrique Barboza2020-09-082-12/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is only used inside spapr_nvdimm.c. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200901125645.118026-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | ppc: introducing spapr_numa.c NUMA code helperDaniel Henrique Barboza2020-09-084-25/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're going to make changes in how spapr handles all ibm,associativity* related properties to enhance our current NUMA support. At this moment we have associativity code scattered all around spapr_* files, with hardcoded values and array sizes. This makes it harder to change any NUMA specific parameters in the future. Having everything in the same place allows not only for easier tuning, but also easier understanding since all NUMA related code is on the same file. This patch introduces a new file to gather all NUMA/associativity handling code in spapr, spapr_numa.c. To get things started, let's remove associativity-reference-points and max-associativity-domains code from spapr_dt_rtas() to a new helper called spapr_numa_write_rtas_dt(). This will decouple spapr_dt_rtas() from the NUMA changes that are going to happen in those two properties. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200901125645.118026-2-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | hw/ppc/ppc4xx_pci: Replace pointless warning by assert()Philippe Mathieu-Daudé2020-09-081-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We call pci_register_root_bus() to register 4 IRQs with the ppc4xx_pci_set_irq() handler. As it can only be called with values in the [0-4[ range, replace the pointless warning by an assert(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200901104043.91383-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | hw/ppc/ppc4xx_pci: Use ARRAY_SIZE() instead of magic valuePhilippe Mathieu-Daudé2020-09-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the magic '4' by ARRAY_SIZE(s->irq) which is more explicit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200901104043.91383-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | target/s390x: Use start-powered-off CPUState propertyThiago Jung Bauermann2020-09-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of setting CPUState::halted to 1 in s390_cpu_initfn(), use the start-powered-off property which makes cpu_common_reset() initialize it to 1 in common code. Note that this changes behavior by setting cs->halted to 1 on reset, which didn't happen before. Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-9-bauerman@linux.ibm.com> [dwg: Fix from Laurent Vivier for user only case] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | sparc/sun4m: Use start-powered-off CPUState propertyThiago Jung Bauermann2020-09-081-19/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of setting CPUState::halted to 1 in secondary_cpu_reset(), use the start-powered-off property which makes cpu_common_reset() initialize it to 1 in common code. Now secondary_cpu_reset() becomes equivalent to main_cpu_reset() so rename the function to sun4m_cpu_reset(). Also remove setting of cs->halted from cpu_devinit(), which seems out of place when compared to similar code in other architectures (e.g., ppce500_init() in hw/ppc/e500.c). Finally, change creation of CPU object from cpu_create() to object_new() and qdev_realize_and_unref() because cpu_create() realizes the CPU and it's not possible to set a property after the object is realized. Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-8-bauerman@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | sparc/sun4m: Don't set cs->halted = 0 in main_cpu_reset()Thiago Jung Bauermann2020-09-081-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We rely on cpu_common_reset() to set cs->halted to 0, it's redundant to do it in main_cpu_reset(). Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-7-bauerman@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | mips/cps: Use start-powered-off CPUState propertyThiago Jung Bauermann2020-09-081-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of setting CPUState::halted to 1 in main_cpu_reset(), use the start-powered-off property which makes cpu_common_reset() initialize it to 1 in common code. Also change creation of CPU object from cpu_create() to object_new() and qdev_realize_and_unref() because cpu_create() realizes the CPU and it's not possible to set a property after the object is realized. Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-6-bauerman@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | ppc/e500: Use start-powered-off CPUState propertyThiago Jung Bauermann2020-09-081-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of setting CPUState::halted to 1 in ppce500_cpu_reset_sec(), use the start-powered-off property which makes cpu_common_reset() initialize it to 1 in common code. Also change creation of CPU object from cpu_create() to object_new() and qdev_realize_and_unref() because cpu_create() realizes the CPU and it's not possible to set a property after the object is realized. Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-5-bauerman@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | ppc/spapr: Use start-powered-off CPUState propertyThiago Jung Bauermann2020-09-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PowerPC sPAPR CPUs start in the halted state, and spapr_reset_vcpu() attempts to implement this by setting CPUState::halted to 1. But that's too late for the case of hotplugged CPUs in a machine configure with 2 or more threads per core. By then, other parts of QEMU have already caused the vCPU to run in an unitialized state a couple of times. For example, ppc_cpu_reset() calls ppc_tlb_invalidate_all(), which ends up calling async_run_on_cpu(). This kicks the new vCPU while it has CPUState::halted = 0, causing QEMU to issue a KVM_RUN ioctl on the new vCPU before the guest is able to make the start-cpu RTAS call to initialize its register state. This problem doesn't seem to cause visible issues for regular guests, but on a secure guest running under the Ultravisor it does. The Ultravisor relies on being able to snoop on the start-cpu RTAS call to map vCPUs to guests, and this issue causes it to see a stray vCPU that doesn't belong to any guest. Fix by setting the start-powered-off CPUState property in spapr_create_vcpu(), which makes cpu_common_reset() initialize CPUState::halted to 1 at an earlier moment. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-4-bauerman@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | target/arm: Move setting of CPU halted state to generic codeThiago Jung Bauermann2020-09-082-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is in a separate patch because it's not so obvious that it won't cause a regression. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-3-bauerman@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | target/arm: Move start-powered-off property to generic CPUStateThiago Jung Bauermann2020-09-086-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are other platforms which also have CPUs that start powered off, so generalize the start-powered-off property so that it can be used by them. Note that ARMv7MState also has a property of the same name but this patch doesn't change it because that class isn't a subclass of CPUState so it wouldn't be a trivial change. This change should not cause any change in behavior. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com> Message-Id: <20200826055535.951207-2-bauerman@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | ppc/spapr_nvdimm: do not enable support with 'nvdimm=off'Daniel Henrique Barboza2020-09-081-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVDIMM support for pSeries was introduced in 5.1, but it didn't contemplate the 'nvdimm' machine option that other archs uses. For every other arch, if no '-machine nvdimm(=on)' is present, it is assumed that the NVDIMM support is disabled. The user must explictly inform that the machine supports NVDIMM. For pseries-5.1 the 'nvdimm' option is completely ignored, and support is always assumed to exist. This leads to situations where the user is able to set 'nvdimm=off' but the guest boots up with the NVDIMMs anyway. Fixing this now, after 5.1 launch, can put the overall NVDIMM support for pseries in a strange place regarding this 'nvdimm' machine option. If we force everything to be like other archs, existing pseries-5.1 guests that didn't use 'nvdimm' to use NVDIMM devices will break. If we attempt to make the newer pseries machines (5.2+) behave like everyone else, but keep pseries-5.1 untouched, we'll have consistency problems on machine upgrade (5.1 will have different default values for NVDIMM support than 5.2). The common ground here is, if the user sets 'nvdimm=off', we must comply regardless of being 5.1 or 5.2+. This patch changes spapr_nvdimm_validate() to verify if the user set NVDIMM support off in the machine options and, in that case, error out if we have a NVDIMM device. The default value for 5.2+ pseries machines will still be 'nvdimm=on' when there is no 'nvdimm' option declared, just like it is today with pseries-5.1. In the end we'll have different default semantics from everyone else in the absence of the 'nvdimm' machine option, but this boat has sailed. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1848887 Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200825215749.213536-4-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr, spapr_nvdimm: fold NVDIMM validation in the same placeDaniel Henrique Barboza2020-09-083-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NVDIMM has different contraints and conditions than the regular DIMM and we'll need to add at least one more. Instead of relying on 'if (nvdimm)' conditionals in the body of spapr_memory_pre_plug(), use the existing spapr_nvdimm_validate_opts() and put all NVDIMM handling code there. Rename it to spapr_nvdimm_validate() to reflect that the function is now checking more than the nvdimm device options. This makes spapr_memory_pre_plug() a bit easier to follow, and we can tune in NVDIMM parameters and validation in the same place. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200825215749.213536-3-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | ppc/spapr_nvdimm: use g_autofree in spapr_nvdimm_validate_opts()Daniel Henrique Barboza2020-09-081-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we're using the string just once, just use g_autofree and avoid leaking it without calling g_free(). Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20200825215749.213536-2-danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | | spapr/xive: Allocate vCPU IPIs from the vCPU contextsCédric Le Goater2020-09-081-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When QEMU switches to the XIVE interrupt mode, it creates all the guest interrupts at the level of the KVM device. These interrupts are backed by real HW interrupts from the IPI interrupt pool of the XIVE controller. Currently, this is done from the QEMU main thread, which results in allocating all interrupts from the chip on which QEMU is running. IPIs are not distributed across the system and the load is not well balanced across the interrupt controllers. Change the vCPU IPI allocation to run from the vCPU context. The associated XIVE IPI interrupt will be allocated on the chip on which the vCPU is running and improve distribution of the IPIs in the system. When the vCPUs are pinned, this will make the IPI local to the chip of the vCPU. It will reduce rerouting between interrupt controllers and gives better performance. Device interrupts are still treated the same. To improve placement, we would need some information on the chip owning the virtual source or the HW source in case of a passthrough device but this reuires changes in PAPR. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200820134547.2355743-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 13:03:48 +0100