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* target-microblaze: Consolidate MMU enabled checksEdgar E. Iglesias2018-05-292-4/+6
| | | | | | | | | | Consolidate MMU enabled checks to cpu_mmu_index(). No functional changes. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: cpu_mmu_index: Fixup indentationEdgar E. Iglesias2018-05-291-7/+9
| | | | | | | | | | Fixup the indentation of cpu_mmu_index in preparation for future edits. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Use tcg_gen_movcond in eval_cond_jmpEdgar E. Iglesias2018-05-291-6/+10
| | | | | | | | | | Cleanup eval_cond_jmp to use tcg_gen_movcond_i64(). No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Convert env_btarget to i64Edgar E. Iglesias2018-05-293-15/+25
| | | | | | | | | Convert env_btarget to i64. No functional change. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Remove argument b in eval_cc()Edgar E. Iglesias2018-05-291-3/+3
| | | | | | | | Remove argument b in eval_cc() as it is always set to zero. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Use table based condition-codes conversionEdgar E. Iglesias2018-05-291-21/+20Star
| | | | | | | | | Use a table based conversion to map condition-codes between MicroBlaze ISA encoding and TCG. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: mmu: Cleanup debug log messagesEdgar E. Iglesias2018-05-291-20/+19Star
| | | | | | | | | | | | Cleanup debug log messages: * Avoid long 80+ character lines. * Remove D() macro and use qemu_log_mask. * Remove logs that are not very useful Suggested-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Simplify address computation using tcg_gen_addi_i32()Edgar E. Iglesias2018-05-291-6/+1Star
| | | | | | | | | | | | | Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Allow address sizes between 32 and 64 bitsEdgar E. Iglesias2018-05-291-3/+2Star
| | | | | | | | Allow address sizes between 32 and 64 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Add support for extended access to TLBLOEdgar E. Iglesias2018-05-295-18/+35
| | | | | | | Add support for extended access to TLBLO's upper 32 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: dec_msr: Plug a temp leakEdgar E. Iglesias2018-05-291-4/+9
| | | | | | | | Plug a temp leak. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: mmu: Add a configurable output address maskEdgar E. Iglesias2018-05-293-0/+3
| | | | | | | | | Add a configurable output address mask, used to mimic the configurable physical address bit width. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: mmu: Prepare for 64-bit addressesEdgar E. Iglesias2018-05-292-10/+10
| | | | | | | | | Prepare for 64-bit addresses. This makes no functional difference as the upper parts of the 64-bit addresses are not yet reachable. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: mmu: Remove unused register stateEdgar E. Iglesias2018-05-292-3/+6
| | | | | | | | | | Add explicit handling for MMU_R_TLBX and log accesses to invalid MMU registers. We can now remove the state for all regs but PID, ZPR and TLBX (0 - 2). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: mmu: Add R_TBLX_MISS macrosEdgar E. Iglesias2018-05-292-2/+7
| | | | | | | | Add a R_TBLX_MISS MASK and SHIFT macros. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Implement MFSE EAREdgar E. Iglesias2018-05-291-1/+8
| | | | | | | Implement MFSE EAR to enable access to the upper part of EAR. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Add Extended AddressingEdgar E. Iglesias2018-05-293-13/+62
| | | | | | | | | | | | | Add support for Extended Addressing. Load/stores with EA enabled concatenate two 32bit registers to form an extended address. We don't allow users to enable address sizes larger than 32 bits quite yet though. Once the MMU support is in, we'll turn it on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Setup for 64bit addressingEdgar E. Iglesias2018-05-292-3/+4
| | | | | | | | | Setup MicroBlaze builds for 64bit addressing. No functional change since the translator does not yet emit 64bit addresses. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Make special registers 64-bitEdgar E. Iglesias2018-05-296-60/+72
| | | | | | | | Extend special registers to 64-bits. This is in preparation for MFSE/MTSE, moves to and from extended special registers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: dec_msr: Fix MTS to FSREdgar E. Iglesias2018-05-291-3/+1Star
| | | | | | | | Fix moves to FSR. Not only bit 31 is accessible. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: dec_msr: Reuse more code when reg-decodingEdgar E. Iglesias2018-05-291-29/+9Star
| | | | | | | | | | Reuse more code when decoding register numbers. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: dec_msr: Use bool and extract32Edgar E. Iglesias2018-05-291-6/+9
| | | | | | | | | | | Use bool and extract32 to represent the to, clr and clrset flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Break out trap_illegal()Edgar E. Iglesias2018-05-291-48/+27Star
| | | | | | | | | | Break out trap_illegal() to handle illegal operation traps. We now generally stop translation of the current insn if it's not valid. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Break out trap_userspace()Edgar E. Iglesias2018-05-291-49/+27Star
| | | | | | | | | | Break out trap_userspace() to avoid open coding it everywhere. For privileged insns, we now always stop translation of the current insn for cores without exceptions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Name special registers we supportEdgar E. Iglesias2018-05-291-2/+2
| | | | | | | Name special registers we support. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Use TCGv for load/store addressesEdgar E. Iglesias2018-05-294-42/+53
| | | | | | | | | | | Use TCGv for load/store addresses, allowing for future computation of 64-bit load/store address. No functional change. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Remove pointer indirection for ld/st addressesEdgar E. Iglesias2018-05-291-12/+12
| | | | | | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Make compute_ldst_addr always use a tempEdgar E. Iglesias2018-05-291-74/+37Star
| | | | | | | | | | | | Make compute_ldst_addr always use a temp. This simplifies the code a bit in preparation for adding support for 64bit addresses. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Bypass MMU with MMU_NOMMU_IDXEdgar E. Iglesias2018-05-291-1/+2
| | | | | | | | Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Conditionalize setting of PVR11_USE_MMUEdgar E. Iglesias2018-05-291-1/+2
| | | | | | | | | | Conditionalize setting of PVR11_USE_MMU on the use_mmu CPU property, otherwise we may incorrectly advertise an MMU via PVR when the core in fact has none. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Remove USE_MMU PVR checksEdgar E. Iglesias2018-05-291-11/+1Star
| | | | | | | | | | We already have a CPU property to control if a core has an MMU or not. Remove USE_MMU PVR checks in favor of looking at the property. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Tighten up TCGv_i32 vs TCGv type usageEdgar E. Iglesias2018-05-292-288/+295
| | | | | | | | | | | | Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when TCGv_i32 should be used. This is in preparation for adding 64bit addressing support. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Correct the PVR array sizeEdgar E. Iglesias2018-05-291-1/+1
| | | | | | | Correct the PVR array size, there are 13 PVR registers. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Correct special register array sizesEdgar E. Iglesias2018-05-292-5/+4Star
| | | | | | | Correct special register array sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Fallback to our latest CPU versionEdgar E. Iglesias2018-05-291-2/+7
| | | | | | | | | | | | Today, when running QEMU in linux-user or with boards that don't select a specific CPU version, we treat it as an invalid version and log a message. Instead, if no specific version was selected, fallback to our latest CPU version. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: compute_ldst_addr: Use bool instead of intEdgar E. Iglesias2018-05-291-5/+5
| | | | | | | | | Use bool instead of int to represent flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: dec_store: Use bool instead of unsigned intEdgar E. Iglesias2018-05-291-3/+4
| | | | | | | | | | | Use bool instead of unsigned int to represent flags. Also, use extract32 instead of open coding the bit extract. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: dec_load: Use bool instead of unsigned intEdgar E. Iglesias2018-05-291-3/+4
| | | | | | | | | Use bool instead of unsigned int to represent flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* Merge remote-tracking branch ↵Peter Maydell2018-05-2529-380/+532
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/linux-user-for-2.13-pull-request' into staging This pull request includes: - fixes for some comments - netlink update and fix - rework/cleanup fo socket.h, including fixes for SPARC part. # gpg: Signature made Fri 25 May 2018 09:16:21 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-2.13-pull-request: gdbstub: Clarify what gdb_handlesig() is doing linux-user: define TARGET_SO_REUSEPORT linux-user: copy sparc/sockbits.h definitions from linux linux-user: update ARCH_HAS_SOCKET_TYPES use linux-user: move ppc socket.h definitions to ppc/sockbits.h linux-user: move socket.h generic definitions to generic/sockbits.h linux-user: move sparc/sparc64 socket.h definitions to sparc/sockbits.h linux-user: move alpha socket.h definitions to alpha/sockbits.h linux-user: move mips socket.h definitions to mips/sockbits.h linux-user: Fix payload size logic in host_to_target_cmsg() linux-user: update comments to point to tcg_exec_init() linux-user: update netlink emulation linux-user: Assert on bad type in thunk_type_align() and thunk_type_size() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * gdbstub: Clarify what gdb_handlesig() is doingPeter Maydell2018-05-252-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | gdb_handlesig()'s behaviour is not entirely obvious at first glance. Add a doc comment for it, and also add a comment explaining why it's ok for gdb_do_syscallv() to ignore gdb_handlesig()'s return value. (Coverity complains about this: CID 1390850.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180515181958.25837-1-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: define TARGET_SO_REUSEPORTLaurent Vivier2018-05-253-5/+2Star
| | | | | | | | | | | | Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180519092956.15134-9-laurent@vivier.eu>
| * linux-user: copy sparc/sockbits.h definitions from linuxLaurent Vivier2018-05-251-39/+92
| | | | | | | | | | | | | | | | | | | | Values defined for sparc are not correct. Copy the content of "arch/sparc/include/uapi/asm/socket.h" to fix them. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180519092956.15134-8-laurent@vivier.eu>
| * linux-user: update ARCH_HAS_SOCKET_TYPES useLaurent Vivier2018-05-255-132/+44Star
| | | | | | | | | | | | | | | | to be like in the kernel and rename it TARGET_ARCH_HAS_SOCKET_TYPES Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180519092956.15134-7-laurent@vivier.eu>
| * linux-user: move ppc socket.h definitions to ppc/sockbits.hLaurent Vivier2018-05-252-9/+25
| | | | | | | | | | | | | | | | | | Change conditional #ifdef part by #undef of the symbols redefined for PPC relative to generic/socket.h Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180519092956.15134-6-laurent@vivier.eu>
| * linux-user: move socket.h generic definitions to generic/sockbits.hLaurent Vivier2018-05-2517-61/+82
| | | | | | | | | | | | | | | | and include the file from architectures without specific definitions Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180519092956.15134-5-laurent@vivier.eu>
| * linux-user: move sparc/sparc64 socket.h definitions to sparc/sockbits.hLaurent Vivier2018-05-253-42/+97
| | | | | | | | | | | | | | | | | | No code change. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180519092956.15134-4-laurent@vivier.eu>
| * linux-user: move alpha socket.h definitions to alpha/sockbits.hLaurent Vivier2018-05-252-105/+114
| | | | | | | | | | | | | | | | | | No code change. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180519092956.15134-3-laurent@vivier.eu>
| * linux-user: move mips socket.h definitions to mips/sockbits.hLaurent Vivier2018-05-253-104/+113
| | | | | | | | | | | | | | | | | | No code change. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180519092956.15134-2-laurent@vivier.eu>
| * linux-user: Fix payload size logic in host_to_target_cmsg()Peter Maydell2018-05-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coverity points out that there's a missing break in the switch in host_to_target_cmsg() where we update tgt_len for cmsg_level/cmsg_type combinations which require a different length for host and target (CID 1385425). To avoid duplicating the default case (target length same as host) in both switches, set that before the switch so that only the cases which want to override it need any code. This fixes a bug where we would have used the wrong length for SOL_SOCKET/SO_TIMESTAMP messages where the target and host have differently sized 'struct timeval' (ie one is 32 bit and the other is 64 bit). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180518184715.29833-1-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: update comments to point to tcg_exec_init()Igor Mammedov2018-05-252-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | cpu_init() was replaced by cpu_create() since 2.12 but comments weren't updated. So update stale comments to point that page sizes arei actually initialized by tcg_exec_init(). Also move another qemu_host_page_size related comment before tcg_exec_init() where it belongs. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1526557877-293151-1-git-send-email-imammedo@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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