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| * | virtiofsd: Move core file creation code in separate functionVivek Goyal2022-02-171-11/+25
| * | virtiofsd, fuse_lowlevel.c: Add capability to parse security contextVivek Goyal2022-02-173-1/+113
| * | virtiofsd: Extend size of fuse_conn_info->capable and ->want fieldsVivek Goyal2022-02-172-3/+3
| * | virtiofsd: Parse extended "struct fuse_init_in"Vivek Goyal2022-02-171-22/+39
| * | linux-headers: Update headers to v5.17-rc1Vivek Goyal2022-02-1726-76/+469
| * | virtiofsd: Fix breakage due to fuse_init_in size changeVivek Goyal2022-02-171-1/+3
| * | virtiofsd: Do not support blocking flockSebastian Hasler2022-02-161-0/+9
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* | Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20220217' int...Peter Maydell2022-02-197-92/+96
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| * 9pfs: Fix segfault in do_readdir_many caused by struct dirent overreadVitaly Chikunov2022-02-175-5/+55
| * tests/9pfs: Use g_autofree and g_autoptr where possibleGreg Kurz2022-02-171-9/+4Star
| * tests/9pfs: Fix leak of local_test_pathGreg Kurz2022-02-171-0/+7
| * tests/9pfs: fix mkdir() being called twiceChristian Schoenebeck2022-02-171-15/+3Star
| * tests/9pfs: use g_autofree where possibleChristian Schoenebeck2022-02-171-63/+27Star
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* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220...Peter Maydell2022-02-1627-370/+3252
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| * docs/system: riscv: Update description of CPUYu Li2022-02-161-3/+3
| * target/riscv: add support for svpbmt extensionWeiwei Li2022-02-163-1/+6
| * target/riscv: add support for svinval extensionWeiwei Li2022-02-165-0/+85
| * target/riscv: add support for svnapot extensionWeiwei Li2022-02-163-3/+18
| * target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li2022-02-161-0/+3
| * target/riscv: Ignore reserved bits in PTE for RV64Guo Ren2022-02-163-1/+30
| * hw/intc: Add RISC-V AIA APLIC device emulationAnup Patel2022-02-164-0/+1061
| * target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel2022-02-162-0/+6
| * hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel2022-02-161-2/+11
| * target/riscv: Implement AIA IMSIC interface CSRsAnup Patel2022-02-161-0/+203
| * target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel2022-02-163-0/+187
| * target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel2022-02-161-0/+156
| * target/riscv: Implement AIA interrupt filtering CSRsAnup Patel2022-02-161-0/+23
| * target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel2022-02-163-1/+131
| * target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel2022-02-164-120/+474
| * target/riscv: Implement AIA local interrupt prioritiesAnup Patel2022-02-164-21/+294
| * target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel2022-02-162-0/+37
| * target/riscv: Add defines for AIA CSRsAnup Patel2022-02-161-0/+119
| * target/riscv: Add AIA cpu featureAnup Patel2022-02-161-1/+2
| * target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel2022-02-162-8/+8
| * target/riscv: Improve delivery of guest external interruptsAnup Patel2022-02-161-0/+13
| * target/riscv: Implement hgeie and hgeip CSRsAnup Patel2022-02-166-38/+121
| * target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel2022-02-163-8/+16
| * target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel2022-02-161-1/+1
| * target/riscv: Fix vill field write in vtypeLIU Zhiwei2022-02-161-0/+1
| * target/riscv: add a MAINTAINERS entry for XVentanaCondOpsPhilipp Tomsich2022-02-161-0/+7
| * target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich2022-02-166-0/+83
| * target/riscv: iterate over a table of decodersPhilipp Tomsich2022-02-161-5/+27
| * target/riscv: access cfg structure through DisasContextPhilipp Tomsich2022-02-161-4/+4
| * target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich2022-02-164-69/+97
| * target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich2022-02-161-0/+2
| * target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich2022-02-161-37/+41
| * target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot2022-02-162-2/+4
| * Allow setting up to 8 bytes with the generic loaderPetr Tesarik2022-02-161-1/+1
| * include: hw: remove ibex_plic.hWilfred Mallawa2022-02-161-67/+0Star
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* Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request...Peter Maydell2022-02-155-4/+51
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