| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | | target/arm: Split gen_nop_hint | Richard Henderson | 2019-09-05 | 1 | -43/+24 |
| * | | target/arm: Convert T16, nop hints | Richard Henderson | 2019-09-05 | 2 | -2/+18 |
| * | | target/arm: Convert T16, Reverse bytes | Richard Henderson | 2019-09-05 | 2 | -15/+12 |
| * | | target/arm: Convert T16, Change processor state | Richard Henderson | 2019-09-05 | 2 | -46/+50 |
| * | | target/arm: Convert T16, extract | Richard Henderson | 2019-09-05 | 2 | -13/+11 |
| * | | target/arm: Convert T16 adjust sp (immediate) | Richard Henderson | 2019-09-05 | 2 | -13/+11 |
| * | | target/arm: Convert T16 add, compare, move (two high registers) | Richard Henderson | 2019-09-05 | 2 | -47/+12 |
| * | | target/arm: Convert T16 branch and exchange | Richard Henderson | 2019-09-05 | 2 | -41/+39 |
| * | | target/arm: Convert T16 one low register and immediate | Richard Henderson | 2019-09-05 | 2 | -42/+13 |
| * | | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson | 2019-09-05 | 2 | -24/+18 |
| * | | target/arm: Convert T16 load/store multiple | Richard Henderson | 2019-09-05 | 2 | -39/+17 |
| * | | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson | 2019-09-05 | 2 | -11/+8 |
| * | | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson | 2019-09-05 | 2 | -89/+38 |
| * | | target/arm: Convert T16 load/store (register offset) | Richard Henderson | 2019-09-05 | 2 | -49/+17 |
| * | | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson | 2019-09-05 | 2 | -145/+43 |
| * | | target/arm: Add skeleton for T16 decodetree | Richard Henderson | 2019-09-05 | 3 | -0/+32 |
| * | | target/arm: Simplify disas_arm_insn | Richard Henderson | 2019-09-05 | 1 | -53/+16 |
| * | | target/arm: Simplify disas_thumb2_insn | Richard Henderson | 2019-09-05 | 1 | -76/+3 |
| * | | target/arm: Convert TT | Richard Henderson | 2019-09-05 | 2 | -61/+34 |
| * | | target/arm: Convert SG | Richard Henderson | 2019-09-05 | 2 | -23/+33 |
| * | | target/arm: Convert Table Branch | Richard Henderson | 2019-09-05 | 2 | -24/+41 |
| * | | target/arm: Convert Unallocated memory hint | Richard Henderson | 2019-09-05 | 2 | -8/+8 |
| * | | target/arm: Convert PLI, PLD, PLDW | Richard Henderson | 2019-09-05 | 2 | -17/+30 |
| * | | target/arm: Convert SETEND | Richard Henderson | 2019-09-05 | 2 | -9/+17 |
| * | | target/arm: Convert CPS (privileged) | Richard Henderson | 2019-09-05 | 3 | -51/+48 |
| * | | target/arm: Convert Clear-Exclusive, Barriers | Richard Henderson | 2019-09-05 | 3 | -69/+78 |
| * | | target/arm: Convert RFE and SRS | Richard Henderson | 2019-09-05 | 3 | -89/+75 |
| * | | target/arm: Convert SVC | Richard Henderson | 2019-09-05 | 2 | -6/+17 |
| * | | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson | 2019-09-05 | 4 | -109/+125 |
| * | | target/arm: Diagnose base == pc for LDM/STM | Richard Henderson | 2019-09-05 | 1 | -2/+3 |
| * | | target/arm: Diagnose too few registers in list for LDM/STM | Richard Henderson | 2019-09-05 | 1 | -8/+18 |
| * | | target/arm: Diagnose writeback register in list for LDM for v7 | Richard Henderson | 2019-09-05 | 1 | -0/+9 |
| * | | target/arm: Convert LDM, STM | Richard Henderson | 2019-09-05 | 3 | -198/+246 |
| * | | target/arm: Convert MOVW, MOVT | Richard Henderson | 2019-09-05 | 3 | -56/+48 |
| * | | target/arm: Convert Signed multiply, signed and unsigned divide | Richard Henderson | 2019-09-05 | 3 | -272/+258 |
| * | | target/arm: Convert packing, unpacking, saturation, and reversal | Richard Henderson | 2019-09-05 | 3 | -310/+300 |
| * | | target/arm: Convert Parallel addition and subtraction | Richard Henderson | 2019-09-05 | 3 | -117/+200 |
| * | | target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF | Richard Henderson | 2019-09-05 | 3 | -96/+144 |
| * | | target/arm: Diagnose UNPREDICTABLE ldrex/strex cases | Richard Henderson | 2019-09-05 | 1 | -2/+38 |
| * | | target/arm: Convert Synchronization primitives | Richard Henderson | 2019-09-05 | 3 | -258/+412 |
| * | | target/arm: Convert load/store (register, immediate, literal) | Richard Henderson | 2019-09-05 | 3 | -443/+623 |
| * | | target/arm: Convert T32 ADDW/SUBW | Richard Henderson | 2019-09-05 | 3 | -11/+33 |
| * | | target/arm: Convert the rest of A32 Miscelaneous instructions | Richard Henderson | 2019-09-05 | 3 | -82/+58 |
| * | | target/arm: Convert ERET | Richard Henderson | 2019-09-05 | 3 | -39/+33 |
| * | | target/arm: Convert CLZ | Richard Henderson | 2019-09-05 | 3 | -16/+24 |
| * | | target/arm: Convert BX, BXJ, BLX (register) | Richard Henderson | 2019-09-05 | 3 | -40/+47 |
| * | | target/arm: Convert Cyclic Redundancy Check | Richard Henderson | 2019-09-05 | 3 | -65/+72 |
| * | | target/arm: Convert MRS/MSR (banked, register) | Richard Henderson | 2019-09-05 | 3 | -141/+145 |
| * | | target/arm: Convert MSR (immediate) and hints | Richard Henderson | 2019-09-05 | 3 | -18/+84 |
| * | | target/arm: Simplify op_smlawx for SMLAW* | Richard Henderson | 2019-09-05 | 1 | -8/+8 |
