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* audio: Remove AudioState from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-222-3/+2Star
| | | | | | | | | | Files requiring AudioState already include "audio_int.h". To clean "qemu/typedefs.h", move the declaration to "audio_int.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/i386: Remove PCMachineClass from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-222-3/+2Star
| | | | | | | | | | Files requiring PCMachineClass already include "hw/i386/pc.h". To clean "qemu/typedefs.h", move the declaration to "hw/i386/pc.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/char/serial: Remove SerialState from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-222-3/+2Star
| | | | | | | | | | Files requiring SerialState already include "hw/char/serial.h". To clean "qemu/typedefs.h", move the declaration to "hw/char/serial.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/bt: Remove HCIInfo from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-222-3/+2Star
| | | | | | | | | | Files requiring HCIInfo already include "sysemu/bt.h". To clean "qemu/typedefs.h", move the declaration to "sysemu/bt.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/i2c/smbus: Remove SMBusDevice from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-222-1/+2
| | | | | | | | | | Files requiring SMBusDevice already include "hw/i2c/smbus.h". To clean "qemu/typedefs.h", move the forward declaration to "hw/i2c/smbus.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/ide/ahci: Remove AllwinnerAHCIState from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-222-3/+2Star
| | | | | | | | | | | Files requiring AllwinnerAHCIState already include "hw/ide/ahci.h". To clean "qemu/typedefs.h", move the declaration to "hw/ide/ahci.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/pcmcia: Remove PCMCIACardState from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-223-3/+3
| | | | | | | | | | | | There is only one header file requiring this typedef (hw/arm/pxa.h), let it include "hw/pcmcia.h" directly to simplify "qemu/typedefs.h". To clean "qemu/typedefs.h", move the declaration to "hw/pcmcia.h" (removing the forward declaration). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [thuth: slightly tweaked commit message] Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/input/ps2: Remove PS2State from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-222-1/+2
| | | | | | | | | | | | PS2State is only used in "hw/input/ps2.h", there is no need to expose it via "qemu/typedefs.h". To clean "qemu/typedefs.h", move the forward declaration to "hw/input/ps2.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/pnv-xscom: Make test independent of global_qtestThomas Huth2019-01-221-14/+15
| | | | | | | Pass around the QTestState, so that we can finally get rid of the out-of-favor global_qtest variable in this file, too. Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/boot-order: Make test independent of global_qtestThomas Huth2019-01-221-30/+29Star
| | | | | | | Pass around the QTestState from function to function, so that we can finally get rid of the out-of-favor global_qtest variable in this file, too. Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/endianesss: Make test independent of global_qtestThomas Huth2019-01-221-163/+166
| | | | | | | Pass around the test state explicitly, to be able to use the qtest_in*() and qtest_out*() function in this test. Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/Makefile: Use some more CONFIG switches for ppc testsThomas Huth2019-01-221-6/+6
| | | | | | | | | | To be able to build and test QEMU binaries where certain devices or machines are disabled, we have to use the right CONFIG_* switches to run certain tests only if the corresponding device or machine really has been compiled into the binary. Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/Makefile: Use some more CONFIG switches for x86 testsThomas Huth2019-01-221-5/+5
| | | | | | | | | To be able to build and test QEMU binaries where certain devices are disabled, we have to use the right CONFIG_* switches to run certain tests only if the corresponding device really has been compiled into the binary. Signed-off-by: Thomas Huth <thuth@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2019-01-219-648/+1042
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/amarkovic/tags/mips-queue-january-17-2019-v2' into staging MIPS queue for January 17, 2019 - v2 # gpg: Signature made Fri 18 Jan 2019 15:55:35 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-january-17-2019-v2: target/mips: Introduce 32 R5900 multimedia registers target/mips: Rename 'rn' to 'register_name' target/mips: Add CP0 register MemoryMapID target/mips: Amend preprocessor constants for CP0 registers target/mips: Update ITU to handle bus errors target/mips: Update ITU to utilize SAARI and SAAR CP0 registers target/mips: Add field and R/W access to ITU control register ICR0 target/mips: Provide R/W access to SAARI and SAAR CP0 registers target/mips: Add fields for SAARI and SAAR CP0 registers target/mips: Use preprocessor constants for 32 major CP0 registers target/mips: Add preprocessor constants for 32 major CP0 registers target/mips: Move comment containing summary of CP0 registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/mips: Introduce 32 R5900 multimedia registersFredrik Noring2019-01-182-0/+19
| | | | | | | | | | | | | | | | | | | | The 32 R5900 128-bit registers are split into two 64-bit halves: the lower halves are the GPRs and the upper halves are accessible by the R5900-specific multimedia instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Rename 'rn' to 'register_name'Aleksandar Markovic2019-01-181-426/+432
| | | | | | | | | | | | | | Rename 'rn' to 'register_name' in CP0-related handlers. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Add CP0 register MemoryMapIDAleksandar Markovic2019-01-182-2/+4
| | | | | | | | | | | | | | | | | | Add CP0 register MemoryMapID. Only data field is added. The corresponding functionality will be added in future patches. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Amend preprocessor constants for CP0 registersAleksandar Markovic2019-01-182-170/+284
| | | | | | | | | | | | | | | | | | | | | | | | Correct existing CP0-related preprocessor constants (replace "CPO" with "CP0" (form letter "O" to digit "0", when needed). Besides, add preprocessor constants for CP0 subregisters. The names of the subregisters were chosen to be in sync with the table of corresponding assembler mnemonics found in the documentation for I6500 and I6400 (release 1.0). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Update ITU to handle bus errorsYongbok Kim2019-01-181-0/+22
| | | | | | | | | | | | | | | | Update ITU to handle bus errors. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Update ITU to utilize SAARI and SAAR CP0 registersYongbok Kim2019-01-185-6/+54
| | | | | | | | | | | | | | | | Update ITU to utilize SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Add field and R/W access to ITU control register ICR0Yongbok Kim2019-01-182-1/+25
| | | | | | | | | | | | | | | | Add field and R/W access to ITU control register ICR0. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-185-4/+120
| | | | | | | | | | | | | | | | Provide R/W access to SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Add fields for SAARI and SAAR CP0 registersYongbok Kim2019-01-182-4/+12
| | | | | | | | | | | | | | | | Add fields for SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Use preprocessor constants for 32 major CP0 registersAleksandar Markovic2019-01-181-136/+136
| | | | | | | | | | | | | | Use preprocessor constants for 32 major CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Add preprocessor constants for 32 major CP0 registersAleksandar Markovic2019-01-181-0/+32
| | | | | | | | | | | | | | Add preprocessor constants for 32 major CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| * target/mips: Move comment containing summary of CP0 registersAleksandar Markovic2019-01-181-81/+84
| | | | | | | | | | | | | | | | | | Move comment containing summary of CP0 registers. Checkpatch script reported some tabs in the resutling diff, so convert these tabs to spaces too. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* | hw/virtio/virtio-balloon: zero-initialize the virtio_balloon_config structPeter Maydell2019-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In virtio_balloon_get_config() we initialize a struct virtio_balloon_config which we then copy to guest memory. However, the local variable is not zero initialized. This works OK at the moment because we initialize all the fields in it; however an upcoming kernel header change will add some new fields. If we don't zero out the whole struct then we will start leaking a small amount of the contents of QEMU's stack to the guest as soon as we update linux-headers/ to a set of headers that includes the new fields. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190118183603.24757-1-peter.maydell@linaro.org
* | hw/block/xen: use proper format string for printing sectorsAlex Bennée2019-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The %lu format string is different depending on the host architecture which causes builds like the debian-armhf-cross build to fail. Use the correct PRi64 format string. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190116121350.23863-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch ↵Peter Maydell2019-01-2121-631/+2514
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20190121' into staging target-arm queue: * hw/char/stm32f2xx_usart: Do not update data register when device is disabled * hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node * target/arm: Allow Aarch32 exception return to switch from Mon->Hyp * ftgmac100: implement the new MDIO interface on Aspeed SoC * implement the ARMv8.3-PAuth extension * improve emulation of the ARM PMU # gpg: Signature made Mon 21 Jan 2019 10:42:11 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190121: (48 commits) target/arm: Implement PMSWINC target/arm: PMU: Set PMCR.N to 4 target/arm: PMU: Add instruction and cycle events target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] target/arm: Define FIELDs for ID_DFR0 target/arm: Implement PMOVSSET target/arm: Allow AArch32 access for PMCCFILTR target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Swap PMU values before/after migrations target/arm: Reorganize PMCCNTR accesses migration: Add post_save function to VMStateDescription target/arm: Tidy TBI handling in gen_a64_set_pc target/arm: Enable PAuth for user-only target/arm: Enable PAuth for -cpu max target/arm: Add PAuth system registers target/arm: Implement pauth_computepac target/arm: Implement pauth_addpac target/arm: Implement pauth_auth ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Implement PMSWINCAaron Lindsay2019-01-211-2/+37
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-14-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: PMU: Set PMCR.N to 4Aaron Lindsay2019-01-211-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-13-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: PMU: Add instruction and cycle eventsAaron Lindsay2019-01-211-46/+44Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-12-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPERAaron Lindsay2019-01-212-17/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add arrays to hold the registers, the definitions themselves, access functions, and logic to reset counters when PMCR.P is set. Update filtering code to support counters other than PMCCNTR. Support migration with raw read/write functions. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-11-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0Aaron Lindsay2019-01-214-11/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-10-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]Aaron Lindsay2019-01-212-4/+19
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-9-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Define FIELDs for ID_DFR0Aaron Lindsay2019-01-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is immediately necessary for the PMUv3 implementation to check ID_DFR0.PerfMon to enable/disable specific features, but defines the full complement of fields for possible future use elsewhere. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-8-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Implement PMOVSSETAaron Lindsay2019-01-211-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-7-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Allow AArch32 access for PMCCFILTRAaron Lindsay2019-01-211-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-6-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Filter cycle counter based on PMCCFILTR_EL0Aaron Lindsay2019-01-213-8/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-5-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Swap PMU values before/after migrationsAaron Lindsay2019-01-212-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Reorganize PMCCNTR accessesAaron Lindsay2019-01-212-53/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Consolidate the duplicated code into two functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to c15_ccnt in CPUARMState so that we can simultaneously save both the architectural register value and the last underlying cycle count - this ensures time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-3-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | migration: Add post_save function to VMStateDescriptionAaron Lindsay2019-01-213-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases it may be helpful to modify state before saving it for migration, and then modify the state back after it has been saved. The existing pre_save function provides half of this functionality. This patch adds a post_save function to provide the second half. Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 20181211151945.29137-2-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Tidy TBI handling in gen_a64_set_pcRichard Henderson2019-01-211-43/+23Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | We can perform this with fewer operations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Enable PAuth for user-onlyRichard Henderson2019-01-212-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 4 attributes that controls the EL1 enable bits, as we may not always want to turn on pointer authentication with -cpu max. However, by default they are enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Enable PAuth for -cpu maxRichard Henderson2019-01-211-0/+4
| | | | | | | | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Add PAuth system registersRichard Henderson2019-01-211-0/+70
| | | | | | | | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Implement pauth_computepacRichard Henderson2019-01-211-1/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the main crypto routine, an implementation of QARMA. This matches, as much as possible, ARM pseudocode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-28-richard.henderson@linaro.org [PMM: fixed minor checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Implement pauth_addpacRichard Henderson2019-01-211-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not really functional yet, because the crypto is not yet implemented. This, however follows the AddPAC pseudo function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Implement pauth_authRichard Henderson2019-01-211-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not really functional yet, because the crypto is not yet implemented. This, however follows the Auth pseudo function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Implement pauth_stripRichard Henderson2019-01-211-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stripping out the authentication data does not require any crypto, it merely requires the virtual address parameters. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-06 03:20:08 +0100