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* fdc: Open-code fdctrl_init_isa()Markus Armbruster2020-06-233-17/+6Star
* fdc: Reject clash between -drive if=floppy and -global isa-fdcMarkus Armbruster2020-06-236-159/+71Star
* iotests/172: Cover -global floppy.drive=...Markus Armbruster2020-06-232-0/+141
* iotests/172: Cover empty filename and multiple use of drivesMarkus Armbruster2020-06-232-0/+62
* iotests/172: Include "info block" in test outputMarkus Armbruster2020-06-232-2/+489
* Merge remote-tracking branch 'remotes/philmd-gitlab/tags/acceptance-testing-2...Peter Maydell2020-06-222-0/+309
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| * tests/acceptance: record/replay tests with advcal imagesPavel Dovgalyuk2020-06-211-0/+108
| * tests/acceptance: add record/replay test for m68kPavel Dovgalyuk2020-06-211-0/+18
| * tests/acceptance: add record/replay test for ppc64Pavel Dovgalyuk2020-06-211-0/+16
| * tests/acceptance: add record/replay test for armPavel Dovgalyuk2020-06-211-0/+48
| * tests/acceptance: add record/replay test for aarch64Pavel Dovgalyuk2020-06-211-0/+19
| * tests/acceptance: add kernel record/replay test for x86_64Pavel Dovgalyuk2020-06-211-0/+18
| * tests/acceptance: add base class record/replay kernel testsPavel Dovgalyuk2020-06-212-0/+74
| * MAINTAINERS: Add an entry to review Avocado based acceptance testsPhilippe Mathieu-Daudé2020-06-211-0/+8
* | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-06-2226-182/+1350
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| * | hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2020-06-192-0/+5
| * | hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng2020-06-191-2/+2
| * | hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2020-06-192-8/+37
| * | hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-193-15/+17
| * | target/riscv: Rename IBEX CPU init routineBin Meng2020-06-191-2/+2
| * | hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2020-06-192-0/+8
| * | hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng2020-06-191-6/+8
| * | hw/riscv: sifive_u: Add reset functionalityBin Meng2020-06-191-1/+23
| * | hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng2020-06-191-1/+3
| * | hw/riscv: sifive_u: Hook a GPIO controllerBin Meng2020-06-192-2/+60
| * | hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng2020-06-192-11/+22
| * | hw/riscv: sifive_gpio: Clean up the codesBin Meng2020-06-192-11/+9Star
| * | hw/riscv: sifive_u: Generate device tree node for OTPBin Meng2020-06-191-0/+11
| * | hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng2020-06-191-6/+1Star
| * | hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng2020-06-191-15/+14Star
| * | hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng2020-06-191-12/+12
| * | target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis2020-06-191-5/+9
| * | riscv/opentitan: Connect the UART deviceAlistair Francis2020-06-192-2/+36
| * | riscv/opentitan: Connect the PLIC deviceAlistair Francis2020-06-192-2/+15
| * | hw/intc: Initial commit of lowRISC Ibex PLICAlistair Francis2020-06-194-0/+327
| * | hw/char: Initial commit of Ibex UARTAlistair Francis2020-06-195-0/+609
| * | riscv/opentitan: Fix the ROM sizeAlistair Francis2020-06-191-1/+2
| * | target/riscv: Implement checks for hfenceAlistair Francis2020-06-193-26/+24Star
| * | target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis2020-06-194-41/+63
| * | target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis2020-06-191-2/+7
| * | target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis2020-06-191-1/+1
| * | riscv: Keep the CPU init routine names consistentBin Meng2020-06-191-4/+4
| * | riscv: Generalize CPU init routine for the imacu CPUBin Meng2020-06-191-21/+10Star
| * | riscv: Generalize CPU init routine for the gcsu CPUBin Meng2020-06-191-14/+6Star
| * | riscv: Generalize CPU init routine for the base CPUBin Meng2020-06-191-13/+5Star
| * | sifive_e: Support the revB machineAlistair Francis2020-06-192-4/+31
| * | riscv: Add helper to make NaN-boxing for FP registerIan Jiang2020-06-191-2/+15
* | | Merge remote-tracking branch 'remotes/kraxel/tags/audio-20200619-pull-request...Peter Maydell2020-06-193-37/+40
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| * | hw/audio/gus: Fix registers 32-bit accessAllan Peramaki2020-06-192-2/+2
| * | audio/jack: simplify the re-init code pathGeoffrey McRae2020-06-171-6/+6
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