summaryrefslogtreecommitdiffstats
path: root/accel/tcg/cputlb.c
Commit message (Expand)AuthorAgeFilesLines
...
* accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()Peter Maydell2018-07-021-2/+1Star
* tcg: Define and use new tlb_hit() and tlb_hit_page() functionsPeter Maydell2018-07-021-10/+5Star
* tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZEPeter Maydell2018-06-261-20/+109
* cputlb: remove tb_lock from tlb_flush functionsEmilio G. Cota2018-06-151-8/+0Star
* exec.c: Handle IOMMUs in address_space_translate_for_iotlb()Peter Maydell2018-06-151-1/+2
* cputlb: Pass cpu_transaction_failed() the correct physaddrPeter Maydell2018-06-151-13/+31
* cpu-defs.h: Document CPUIOTLBEntry 'addr' fieldPeter Maydell2018-06-151-0/+12
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-5/+8
* accel/tcg: Handle atomic accesses to notdirty memory correctlyPeter Maydell2017-11-211-13/+25
* tcg: Record code_gen_buffer address for user-only memory helpersRichard Henderson2017-11-151-0/+1
* accel/tcg: allow to invalidate a write TLB entry immediatelyDavid Hildenbrand2017-10-201-1/+4
* cputlb: bring back tlb_flush_count under !TLB_DEBUGEmilio G. Cota2017-10-101-3/+14
* accel/tcg/cputlb: avoid recursive BQL (fixes #1706296)Alex Bennée2017-09-251-2/+2
* cputlb: Support generating CPU exceptions on memory transaction failuresPeter Maydell2017-09-041-2/+30
* tcg: consistently access cpu->tb_jmp_cache atomicallyEmilio G. Cota2017-06-301-2/+2
* exec: allow to get a pointer for some mmio memory regionKONRAD Frederic2017-06-271-0/+10
* cputlb: fix the way get_page_addr_code fills the tlbKONRAD Frederic2017-06-271-2/+4
* cputlb: move get_page_addr_codeKONRAD Frederic2017-06-271-35/+35
* cputlb: cleanup get_page_addr_code to use VICTIM_TLB_HITKONRAD Frederic2017-06-271-9/+9
* tcg: move tcg related files into accel/tcg/ subdirectoryYang Zhong2017-06-151-0/+1051
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-26 07:42:00 +0100