summaryrefslogtreecommitdiffstats
path: root/accel/tcg/cputlb.c
Commit message (Expand)AuthorAgeFilesLines
...
* cputlb: Fix size operand for tlb_fill on unaligned storeRichard Henderson2019-09-031-1/+4
* cputlb: Fold TLB_RECHECK into TLB_INVALID_MASKRichard Henderson2019-09-031-63/+23Star
* cputlb: Byte swap memory transaction attributeTony Nguyen2019-09-031-0/+12
* memory: Single byte swap along the I/O pathTony Nguyen2019-09-031-39/+3Star
* cputlb: Replace size and endian operands for MemOpTony Nguyen2019-09-031-89/+81Star
* memory: Access MemoryRegion with endiannessTony Nguyen2019-09-031-2/+6
* cputlb: Access MemoryRegion with MemOpTony Nguyen2019-09-031-4/+4
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-1/+1
* cputlb: cast size_t to target_ulong before using for address masksAlex Bennée2019-06-121-1/+1
* cputlb: use uint64_t for interim values for unaligned loadAlex Bennée2019-06-121-1/+1
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-19/+19
* tcg: Create struct CPUTLBRichard Henderson2019-06-101-76/+88
* tcg: Fold CPUTLBWindow into CPUTLBDescRichard Henderson2019-06-101-12/+12
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into stagingPeter Maydell2019-05-161-8/+80
|\
| * tcg: Use tlb_fill probe from tlb_vaddr_to_hostRichard Henderson2019-05-101-8/+61
| * tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson2019-05-101-0/+19
* | cputlb: Do unaligned store recursion to outermost functionRichard Henderson2019-05-101-4/+4
* | cputlb: Do unaligned load recursion to outermost functionRichard Henderson2019-05-101-20/+97
* | cputlb: Drop attribute flattenRichard Henderson2019-05-101-63/+42Star
* | cputlb: Move TLB_RECHECK handling into load/store_helperRichard Henderson2019-05-101-71/+55Star
* | accel/tcg: demacro cputlbAlex Bennée2019-05-101-26/+452
|/
* cputlb: Fix io_readx() to respect the access_typeShahab Vahedi2019-04-251-2/+3
* cputlb: update TLB entry/index after tlb_fillEmilio G. Cota2019-02-111-0/+4
* tcg: Fix LGPL version numberThomas Huth2019-01-301-1/+1
* cputlb: Remove static tlb sizingRichard Henderson2019-01-281-21/+0Star
* tcg: introduce dynamic TLB sizingEmilio G. Cota2019-01-281-5/+197
* cputlb: do not evict empty entries to the vtlbEmilio G. Cota2019-01-281-1/+10
* cputlb: Remove tlb_c.pending_flushesRichard Henderson2018-10-311-14/+2Star
* cputlb: Filter flushes on already clean tlbsRichard Henderson2018-10-311-10/+25
* cputlb: Count "partial" and "elided" tlb flushesRichard Henderson2018-10-311-5/+13
* cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidxRichard Henderson2018-10-311-46/+12Star
* cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_workRichard Henderson2018-10-311-72/+21Star
* cputlb: Move env->vtlb_index to env->tlb_d.vindexRichard Henderson2018-10-311-3/+2Star
* cputlb: Split large page tracking per mmu_idxRichard Henderson2018-10-311-77/+61Star
* cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flushRichard Henderson2018-10-311-12/+23
* cputlb: Remove tcg_enabled hack from tlb_flush_nocheckRichard Henderson2018-10-311-7/+0Star
* cputlb: Move tlb_lock to CPUTLBCommonRichard Henderson2018-10-311-24/+24
* cputlb: read CPUTLBEntry.addr_write atomicallyEmilio G. Cota2018-10-191-6/+13
* tcg: Split CONFIG_ATOMIC128Richard Henderson2018-10-191-1/+2
* tcg: Add tlb_index and tlb_entry helpersRichard Henderson2018-10-191-33/+27Star
* cputlb: serialize tlb updates with env->tlb_lockEmilio G. Cota2018-10-191-71/+84
* cputlb: fix assert_cpu_is_self macroEmilio G. Cota2018-10-191-2/+2
* exec: introduce tlb_initEmilio G. Cota2018-10-191-0/+4
* accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell2018-08-141-21/+8Star
* accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code()Peter Maydell2018-08-141-85/+10Star
* accel/tcg: Pass read access type through to io_readx()Peter Maydell2018-08-141-2/+3
* accel/tcg: Assert that tlb fill gave us a valid TLB entryPeter Maydell2018-07-161-2/+2
* accel/tcg: Use correct test when looking in victim TLB for codePeter Maydell2018-07-161-1/+1
* accel/tcg: Avoid caching overwritten tlb entriesRichard Henderson2018-07-021-26/+35
* accel/tcg: Don't treat invalid TLB entries as needing recheckPeter Maydell2018-07-021-1/+2
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-25 00:17:34 +0100