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* disas: nanoMIPS: Name some functions in a more descriptive wayAleksandar Markovic2019-01-032-72/+72
| | | | | | | | Rename some functions that have names that are hard to understand. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* disas: nanoMIPS: Fix order of some invocationsAleksandar Markovic2019-01-031-388/+388
| | | | | | | | | | | Fix order of extraction function invocations so that extraction goes from MSB side to LSB side of the given instruction coding content. This is desireable because of consistency and easier visual spotting of errors. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* disas: nanoMIPS: Fix a function misnomerAleksandar Markovic2019-01-032-133/+133
| | | | | | | | | Fix wrong function name. The convention in these files is that names of extraction functions should reflect bit patterns they are extracting. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* disas: nanoMIPS: Remove functions that are not usedAleksandar Markovic2019-01-032-233/+0Star
| | | | | | | | | | Some functions were not used at all. Compiler doesn't complain since they are class memebers. Remove them - no future usage is planned. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* disas: nanoMIPS: Fix preamble text in nanomips.* filesAleksandar Markovic2019-01-032-6/+8
| | | | | | | | | Fix several mistakes in preambles of nanomips disassembler source files. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* disas: nanoMIPS: Fix types and format stringsStefan Weil2019-01-032-13/+17
| | | | | | | | Use POSIX types and format strings. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Weil <sw@weilnetz.de>
* disas/microblaze: Remove unused REG_SP macroRichard Henderson2018-12-251-1/+0Star
| | | | | | | | | | | | | | | | This causes a build error with debian sid, riscv64 host: disas/microblaze.c:179: error: "REG_SP" redefined [-Werror] #define REG_SP 1 /* stack pointer */ In file included from /usr/include/signal.h:306, from include/qemu/osdep.h:101, from disas/microblaze.c:36: /usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of the previous definition # define REG_SP 2 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/ppc: tcg: Implement addex instructionSuraj Jitindar Singh2018-12-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the addex instruction introduced in ISA V3.00 in qemu tcg. The add extended using alternate carry bit (addex) instruction performs the same operation as the add extended (adde) instruction, but using the overflow (ov) field in the fixed point exception register (xer) as the carry in and out instead of the carry (ca) field. The instruction has a Z23-form, not an XO form, as follows: ------------------------------------------------------------------ | 31 | RT | RA | RB | CY | 170 | 0 | ------------------------------------------------------------------ 0 6 11 16 21 23 31 32 However since the only valid form of the instruction defined so far is CY = 0, we can treat this like an XO form instruction. There is no dot form (addex.) of the instruction and the summary overflow (so) bit in the xer is not modified by this instruction. For simplicity we reuse the gen_op_arith_add function and add a function argument to specify where the carry in input should come from and the carry out output be stored (note must be the same location). Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/mips: Add disassembler support for nanoMIPSAleksandar Markovic2018-10-253-0/+23342
| | | | | | | | Add disassembler support for nanoMIPS. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Matthew Fortune <matthew.fortune@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* fix "Missing break in switch" coverity reportsPaolo Bonzini2018-08-231-0/+1
| | | | | | | | | | Many of these are marked as "intentional/fix required" because they just need adding a fall through comment. This is exactly what this patch does, except for target/mips/translate.c where it is easier to duplicate the code, and hw/audio/sb16.c where I consulted the DOSBox sources and decide to just remove the LOG_UNIMP before the fallthrough. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/m68k: correctly disassemble move16Laurent Vivier2018-07-021-0/+14
| | | | | | | | | | | | | | | | | "move16 %a0@+,%a1@" and "fmovel (cpid=3) %a0@-,%fpcr" share the same opcode. To fix that, backport the fix from binutils: 2005-11-10 Andreas Schwab <schwab@suse.de> * m68k-dis.c (print_insn_m68k): Only match FPU insns with coprocessor ID 1. Reported-by: Thomas Huth <huth@tuxfamily.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20180625203559.21370-2-laurent@vivier.eu>
* RISC-V: Fix missing break statement in disassemblerMichael Clark2018-05-061-1/+2
| | | | | | | | | | | | | | This fixes an issue when disassembling rv128 c.sqsp, where the code erroneously fell through to c.swsp. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* RISC-V: Include instruction hex in disassemblyMichael Clark2018-05-061-19/+20
| | | | | | | | | | | | | This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Fix incorrect disassembly for addiwMichael Clark2018-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | This fixes a bug in the disassembler constraints used to lift instructions into pseudo-instructions, whereby addiw instructions are always lifted to sext.w instead of just lifting addiw with a zero immediate. An associated fix has been made to the metadata used to machine generate the disseasembler: https://github.com/michaeljclark/riscv-meta/ commit/4a6b2f3898430768acfe201405224d2ea31e1477 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* RISC-V DisassemblerMichael Clark2018-03-062-0/+3049
| | | | | | | | | | | | | | | | | The RISC-V disassembler has no dependencies outside of the 'disas' directory so it can be applied independently. The majority of the disassembler is machine-generated from instruction set metadata: - https://github.com/michaeljclark/riscv-meta Expected checkpatch errors for consistency and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com>
* Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into stagingPeter Maydell2018-01-241-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | target/xtensa updates: - make mini-bootloader independent of the initial CPU state; - add noMMU XTFPGA variants; - add two noMMU cores: de212 and sample_controller; - fix issues reported by coverity against xtensa translator and disassembler. # gpg: Signature made Mon 22 Jan 2018 20:00:01 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180122-xtensa: target/xtensa: disas/xtensa: fix coverity warnings target/xtensa: add sample_controller core target/xtensa: allow different default CPU for MMU/noMMU target/xtensa: add de212 core hw/xtensa/xtfpga: support noMMU cores hw/xtensa/xtfpga: extract flash configuration hw/xtensa: extract xtensa_create_memory_regions target/xtensa: fix default sysrom/sysram addresses hw/xtensa/xtfpga: clean up function/structure names hw/xtensa/xtfpga: rewrite mini bootloader Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/xtensa: disas/xtensa: fix coverity warningsMax Filippov2018-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | Coverity warnings CID 1385146, 1385148 1385149 and 1385150 point that xtensa_opcode_num_operands and xtensa_format_num_slots may return -1 even when xtensa_opcode_decode and xtensa_format_decode succeed. In that case unsigned counters used to iterate through operands/slots will not do the right thing. Make counters and loop bounds signed to fix the warnings. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* | disas/s390: fix global-buffer-overflowMarc-André Lureau2018-01-161-10/+6Star
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spotted thanks to ASAN: ==25226==ERROR: AddressSanitizer: global-buffer-overflow on address 0x556715a1f120 at pc 0x556714b6f6b1 bp 0x7ffcdfac1360 sp 0x7ffcdfac1350 READ of size 1 at 0x556715a1f120 thread T0 #0 0x556714b6f6b0 in init_disasm /home/elmarco/src/qemu/disas/s390.c:219 #1 0x556714b6fa6a in print_insn_s390 /home/elmarco/src/qemu/disas/s390.c:294 #2 0x55671484d031 in monitor_disas /home/elmarco/src/qemu/disas.c:635 #3 0x556714862ec0 in memory_dump /home/elmarco/src/qemu/monitor.c:1324 #4 0x55671486342a in hmp_memory_dump /home/elmarco/src/qemu/monitor.c:1418 #5 0x5567148670be in handle_hmp_command /home/elmarco/src/qemu/monitor.c:3109 #6 0x5567148674ed in qmp_human_monitor_command /home/elmarco/src/qemu/monitor.c:613 #7 0x556714b00918 in qmp_marshal_human_monitor_command /home/elmarco/src/qemu/build/qmp-marshal.c:1704 #8 0x556715138a3e in do_qmp_dispatch /home/elmarco/src/qemu/qapi/qmp-dispatch.c:104 #9 0x556715138f83 in qmp_dispatch /home/elmarco/src/qemu/qapi/qmp-dispatch.c:131 #10 0x55671485cf88 in handle_qmp_command /home/elmarco/src/qemu/monitor.c:3839 #11 0x55671514e80b in json_message_process_token /home/elmarco/src/qemu/qobject/json-streamer.c:105 #12 0x5567151bf2dc in json_lexer_feed_char /home/elmarco/src/qemu/qobject/json-lexer.c:323 #13 0x5567151bf827 in json_lexer_feed /home/elmarco/src/qemu/qobject/json-lexer.c:373 #14 0x55671514ee62 in json_message_parser_feed /home/elmarco/src/qemu/qobject/json-streamer.c:124 #15 0x556714854b1f in monitor_qmp_read /home/elmarco/src/qemu/monitor.c:3881 #16 0x556715045440 in qemu_chr_be_write_impl /home/elmarco/src/qemu/chardev/char.c:172 #17 0x556715047184 in qemu_chr_be_write /home/elmarco/src/qemu/chardev/char.c:184 #18 0x55671505a8e6 in tcp_chr_read /home/elmarco/src/qemu/chardev/char-socket.c:440 #19 0x5567150943c3 in qio_channel_fd_source_dispatch /home/elmarco/src/qemu/io/channel-watch.c:84 #20 0x7fb90292b90b in g_main_dispatch ../glib/gmain.c:3182 #21 0x7fb90292c7ac in g_main_context_dispatch ../glib/gmain.c:3847 #22 0x556715162eca in glib_pollfds_poll /home/elmarco/src/qemu/util/main-loop.c:214 #23 0x556715163001 in os_host_main_loop_wait /home/elmarco/src/qemu/util/main-loop.c:261 #24 0x5567151631fa in main_loop_wait /home/elmarco/src/qemu/util/main-loop.c:515 #25 0x556714ad6d3b in main_loop /home/elmarco/src/qemu/vl.c:1950 #26 0x556714ade329 in main /home/elmarco/src/qemu/vl.c:4865 #27 0x7fb8fe5c9009 in __libc_start_main (/lib64/libc.so.6+0x21009) #28 0x5567147af4d9 in _start (/home/elmarco/src/qemu/build/s390x-softmmu/qemu-system-s390x+0xf674d9) 0x556715a1f120 is located 32 bytes to the left of global variable 'char_hci_type_info' defined in '/home/elmarco/src/qemu/hw/bt/hci-csr.c:493:23' (0x556715a1f140) of size 104 0x556715a1f120 is located 8 bytes to the right of global variable 's390_opcodes' defined in '/home/elmarco/src/qemu/disas/s390.c:860:33' (0x556715a15280) of size 40600 This fix is based on Andreas Arnez <arnez@linux.vnet.ibm.com> upstream commit: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;h=9ace48f3d7d80ce09c5df60cccb433470410b11b 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com> * s390-dis.c (init_disasm): Simplify initialization of opc_index[]. This also fixes an access after the last element of s390_opcodes[]. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180104160523.22995-19-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch 'remotes/xtensa/tags/20180109-xtensa' into stagingPeter Maydell2018-01-092-0/+134
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | target/xtensa updates: - add libisa to the xtensa target; - change xtensa instruction translator to use it; - switch existing xtensa cores to use it; - add support for a number of instructions: salt/saltu, const16, GPIO32 group, debug mode and MMU-related; - add disassembler for Xtensa. # gpg: Signature made Tue 09 Jan 2018 18:11:02 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180109-xtensa: target/xtensa: implement disassembler target/xtensa: implement const16 target/xtensa: implement GPIO32 target/xtensa: implement salt/saltu target/xtensa: add internal/noop SRs and opcodes target/xtensa: drop DisasContext::litbase target/xtensa: tests: fix memctl SR test target/xtensa: use libisa for instruction decoding target/xtensa: switch fsf to libisa target/xtensa: switch dc233c to libisa target/xtensa: switch dc232b to libisa target/xtensa: update import_core.sh script for libisa target/xtensa: extract FPU2000 opcode translators target/xtensa: extract core opcode translators target/xtensa: import libisa source target/xtensa: pass actual frame size to the entry helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/xtensa: implement disassemblerMax Filippov2018-01-092-0/+134
| | | | | | | | | | | | | | Add disas/xtensa.c and use libisa for instruction decoding/opcode name lookup. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* | nios2: remove duplicated includes (in code commented out)Philippe Mathieu-Daudé2017-12-181-3/+0Star
| | | | | | | | | | | | | | | | applied using ./scripts/clean-includes Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | disas/arm: fix 'instuction' typo in commentEmilio G. Cota2017-12-181-1/+1
|/ | | | | Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target/arm: Move BE32 disassembler fixupRichard Henderson2017-10-251-5/+16
| | | | | | | | | | | The Capstone disassembler has its own big-endian fixup. Doing this twice does not work, of course. Move our current fixup from target/arm/cpu.c to disas/arm.c. This makes read_memory_inner_func unused and can be removed. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* disas/i386: Add disassembly of rorxRichard Henderson2017-09-061-2/+11
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas/i386: Add disassembly of vex.0f38.f5Richard Henderson2017-09-061-3/+12
| | | | | | Which includes pext, pdep and bzhi. Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas/i386: Fix disassembly of two-byte vex prefixesRichard Henderson2017-09-061-0/+1
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove support for ia64 as hostRichard Henderson2017-09-052-10601/+0Star
| | | | | | | | | | We threatened to remove ia64 as host in v2.9.0. Its time has now come. There are still some usages of defined(__ia64__) throughout the source code that would be triggered if one were to enable TCI on an ia64 host. Leave those alone for now. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* disas/microblaze: Add missing 'const' attributesStefan Weil2017-07-041-11/+7Star
| | | | | | | | | | | | Making the opcode list 'const' saves memory. Some function arguments and local variables needed 'const', too. Add also 'static' to two local functions. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> [EI: Removed old prototypes to fix the build] Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* configure: split c and cxx extra flagsBruno Dominguez2017-06-071-2/+2
| | | | | | | | | | | | | | | | | | | There was no possibility to add specific cxx flags using the configure file. So A new entrance has been created to support it. Duplication of information in configure and rules.mak. Taking QEMU_CFLAGS and add them to QEMU_CXXFLAGS, now the value of QEMU_CXXFLAGS is stored in config-host.mak, so there is no need for it. The makefile for libvixl was adding flags for QEMU_CXXFLAGS in QEMU_CFLAGS because of the addition in rules.mak. That was removed, so adding them where it should be. Signed-off-by: Bruno Dominguez <bru.dominguez@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1496754467-20893-1-git-send-email-bru.dominguez@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* libvixl: Correct build failures on NetBSDKamil Rytarowski2017-06-021-0/+3
| | | | | | | | | | | | | | | | | | | | Ensure that C99 macros are defined regardless of the inclusion order of headers in vixl. This is required at least on NetBSD. The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be included before other system headers. This file defines unconditionally the following macros, without altering the original sources: - __STDC_CONSTANT_MACROS - __STDC_LIMIT_MACROS - __STDC_FORMAT_MACROS Signed-off-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170514051820.15985-1-n54@gmx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* disas/cris.c: Avoid unintentional sign extensionPeter Maydell2017-04-031-2/+2
| | | | | | | | | | | Commit 001ebaca7b11 fixed some unintended sign extension issues spotted by Coverity (CID 1005402, 1005403), but didn't catch all of them. Fix the rest, so we behave consistently whether 'long' is 32 bit or 64 bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1490970671-20560-1-git-send-email-peter.maydell@linaro.org
* disas/microblaze: Remove unused REG_PC definePeter Maydell2017-03-241-1/+1
| | | | | | | | | | | | | | | | | | | | | The REG_PC define in disas/microblaze.c clashes with a define in the Linux SPARC system headers: /home/pm215/qemu/disas/microblaze.c:162:0: error: "REG_PC" redefined [-Werror] #define REG_PC 32 /* PC */ In file included from /usr/include/signal.h:326:0, from /home/pm215/qemu/include/qemu/osdep.h:86, from /home/pm215/qemu/disas/microblaze.c:36: /usr/include/sparc64-linux-gnu/sys/ucontext.h:96:0: note: this is the location of the previous definition #define REG_PC (1) Since the code doesn't actually use the REG_PC define anywhere, the simplest fix is just to remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1490272961-1128-1-git-send-email-peter.maydell@linaro.org
* disas/arm: Avoid unintended sign extensionPeter Maydell2017-03-071-2/+2
| | | | | | | | | | | | | | When assembling 'given' from the instruction bytes, C's integer promotion rules mean we may promote an unsigned char to a signed integer before shifting it, and then sign extend to a 64-bit long, which can set the high bits of the long. The code doesn't in fact care about the high bits if the long is 64 bits, but this is surprising, so don't do it. (Spotted by Coverity, CID 1005404.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1488556233-31246-7-git-send-email-peter.maydell@linaro.org
* disas/cris: Avoid unintended sign extensionPeter Maydell2017-03-071-2/+2
| | | | | | | | | | | | | | | In the cris disassembler we were using 'unsigned long' to calculate addresses which are supposed to be 32 bits. This meant that we might accidentally sign extend or calculate a value that was outside the 32 bit range of the guest CPU. Use 'uint32_t' instead so we give the right answers on 64-bit hosts. (Spotted by Coverity, CID 1005402, 1005403.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1488556233-31246-6-git-send-email-peter.maydell@linaro.org
* disas/microblaze: Avoid unintended sign extensionPeter Maydell2017-03-071-2/+4
| | | | | | | | | | | | | In read_insn_microblaze() we assemble 4 bytes into an 'unsigned long'. If 'unsigned long' is 64 bits and the high byte has its top bit set, then C's implicit conversion from 'unsigned char' to 'int' for the shift will result in an unintended sign extension which sets the top 32 bits in 'inst'. Add casts to prevent this. (Spotted by Coverity, CID 1005401.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1488556233-31246-5-git-send-email-peter.maydell@linaro.org
* disas/m68k: Avoid unintended sign extension in get_field()Peter Maydell2017-03-071-2/+3
| | | | | | | | | | | | | | | In get_field(), we take an 'unsigned char' value and shift it left, which implicitly promotes it to 'signed int', before ORing it into an 'unsigned long' type. If 'unsigned long' is 64 bits then this will result in a sign extension and the top 32 bits of the result will be 1s. Add explicit casts to unsigned long before shifting to prevent this. (Spotted by Coverity, CID 715697.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-id: 1488556233-31246-4-git-send-email-peter.maydell@linaro.org
* disas/i386: Avoid NULL pointer dereference in error casePeter Maydell2017-03-071-1/+1
| | | | | | | | | In a code path where we hit an internal disassembler error, execution would subsequently attempt to dereference a NULL pointer. This should never happen, but avoid the crash. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1488556233-31246-3-git-send-email-peter.maydell@linaro.org
* disas/hppa: Remove dead codePeter Maydell2017-03-071-2/+1Star
| | | | | | | | | | Coverity complains (CID 1302705) that the "fr0" part of the ?: in fput_fp_reg_r() is dead. This looks like cut-n-paste error from fput_fp_reg(); delete the dead code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1488556233-31246-2-git-send-email-peter.maydell@linaro.org
* disas/ppc: Fix indefinite articles in commentsStefan Weil2017-01-311-6/+6
| | | | | Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* Merge remote-tracking branch 'remotes/rth/tags/pull-nios-20170124' into stagingPeter Maydell2017-01-252-0/+3535
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nios2 target support # gpg: Signature made Tue 24 Jan 2017 21:11:47 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-nios-20170124: nios2: Add support for Nios-II R1 nios2: Add Altera 10M50 GHRD emulation nios2: Add periodic timer emulation nios2: Add IIC interrupt controller emulation nios2: Add usermode binaries emulation nios2: Add disas entries nios2: Add architecture emulation support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * nios2: Add disas entriesMarek Vasut2017-01-242-0/+3535
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nios2 disassembler support. This patch is composed from binutils files from commit "Opcodes and assembler support for Nios II R2". The files from binutils used in this patch are: include/opcode/nios2.h include/opcode/nios2r1.h include/opcode/nios2r2.h opcodes/nios2-opc.c opcodes/nios2-dis.c Checkpatch says total: 114 errors, 0 warnings, 3609 lines checked , which is caused by a different coding style in those files. These warnings and errors are not addressed To let these files be easily synchronized between binutils and qemu. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-2-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | disas/cris.c: Fix Coverity warning about unchecked NULLPeter Maydell2017-01-241-1/+1
|/ | | | | | | | | | | | Coverity (CID 1005689) warns that we don't check that spec_reg_info() returned non-NULL before dereferencing. Add the check, though as the comment notes this is a can't-really-happen case because the earlier constraint matching should have ruled out the "unknown reg" case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Revert "Remove remainders of HPPA backend"Richard Henderson2017-01-232-0/+2833
| | | | | | This reverts commit d41f3c3cc7a5fb9de144cc4022da14a9ff010671. Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas/ppc: Handle popcnt and cnttzRichard Henderson2017-01-101-0/+10
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas/i386.c: Handle tzcntRichard Henderson2017-01-101-2/+10
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into ↵Peter Maydell2016-12-221-6/+2Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging slirp updates # gpg: Signature made Tue 20 Dec 2016 23:05:13 GMT # gpg: using RSA key 0xA003196827414880 # gpg: Good signature from "Samuel Thibault <samuel.thibault@gnu.org>" # gpg: aka "Samuel Thibault <sthibault@debian.org>" # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@ens-lyon.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: 6B0F AC21 8566 46E9 4AA2 D200 A003 1968 2741 4880 * remotes/thibault/tags/samuel-thibault: slirp: support dynamic block size for TFTP transfers slirp, disas: Replace min/max with MIN/MAX macros Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * slirp, disas: Replace min/max with MIN/MAX macrosYuval Shaia2016-12-201-6/+2Star
| | | | | | | | | | | | | | Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
* | Move target-* CPU file into a target/ folderThomas Huth2016-12-201-3/+1Star
|/ | | | | | | | | | | | | | | | | | | | | | | | | We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
* target-ppc: add vrldnm and vrlwnm instructionsBharata B Rao2016-11-151-0/+2
| | | | | | | | | | vrldnm: Vector Rotate Left Doubleword then AND with Mask vrlwnm: Vector Rotate Left Word then AND with Mask Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target-ppc: add vrldnmi and vrlwmi instructionsGautham R. Shenoy2016-11-151-0/+2
| | | | | | | | | | | | vrldmi: Vector Rotate Left Dword then Mask Insert vrlwmi: Vector Rotate Left Word then Mask Insert Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> ( use extract[32,64] and rol[32,64], introduce mask helpers in internal.h ) Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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