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* arm: Consistently use "Cortex-Axx", not "Cortex Axx"Peter Maydell2021-06-033-6/+6
| | | | | | | | | | | | | | | | The official punctuation for Arm CPU names uses a hyphen, like "Cortex-A9". We mostly follow this, but in a few places usage without the hyphen has crept in. Fix those so we consistently use the same way of writing the CPU name. This commit was created with: git grep -z -l 'Cortex ' | xargs -0 sed -i 's/Cortex /Cortex-/' Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210527095152.10968-1-peter.maydell@linaro.org
* hw/arm/mps2-tz: Implement AN524 memory remapping via machine propertyPeter Maydell2021-05-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | The AN524 FPGA image supports two memory maps, which differ in where the QSPI and BRAM are. In the default map, the BRAM is at 0x0000_0000, and the QSPI at 0x2800_0000. In the second map, they are the other way around. In hardware, the initial mapping can be selected by the user by writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the board configuration file. The board config file is acted on by the "Motherboard Configuration Controller", which is an entirely separate microcontroller on the dev board but outside the FPGA. The guest can also dynamically change the mapping via the SCC CFG_REG0 register. Implement this functionality for QEMU, using a machine property "remap" with valid values "BRAM" and "QSPI" to allow the user to set the initial mapping, in the same way they can on the FPGA, and wiring up the bit from the SCC register to also switch the mapping. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210504120912.23094-4-peter.maydell@linaro.org
* docs: fix link in sbsa descriptionAlex Bennée2021-05-101-1/+1
| | | | | | | | | A trailing _ makes all the difference to the rendered link. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210428131316.31390-1-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed: Integrate HACEJoel Stanley2021-05-011-1/+0Star
| | | | | | | | | | | | Add the hash and crypto engine model to the Aspeed socs. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210409000253.1475587-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw: Model ASPEED's Hash and Crypto EngineJoel Stanley2021-05-011-0/+1
| | | | | | | | | | | | | | | | | | | The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1, SHA2, RSA and other cryptographic algorithms. This initial model implements a subset of the device's functionality; currently only MD5/SHA hashing, and on the ast2600's scatter gather engine. Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> [ clg: - fixes for 32-bit and OSX builds ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210409000253.1475587-2-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm: Add MFT device to NPCM7xx SocHao Wu2021-03-121-1/+1
| | | | | | | | | | | | This patch adds the recently implemented MFT device to the NPCM7XX SoC file. Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210311180855.149764-4-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: versal: Add support for the XRAMsEdgar E. Iglesias2021-03-121-0/+1
| | | | | | | | | | Connect the support for the Versal Accelerator RAMs (XRAMs). Reviewed-by: Luc Michel <luc@lmichel.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210308224637.2949533-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210309' ↵Peter Maydell2021-03-111-6/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Aspeed patches : * New model for the Aspeed LPC controller * Misc cleanups # gpg: Signature made Tue 09 Mar 2021 11:54:25 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20210309: hw/misc: Model KCS devices in the Aspeed LPC controller hw/misc: Add a basic Aspeed LPC controller model hw/arm: ast2600: Correct the iBT interrupt ID hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC hw/arm/aspeed: Fix location of firmware images in documentation arm/ast2600: Fix SMP booting with -kernel Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc: Add a basic Aspeed LPC controller modelCédric Le Goater2021-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/arm/aspeed: Fix location of firmware images in documentationCédric Le Goater2021-03-091-5/+9
| | | | | | | | | | | | | | | | | | | | Firmware images can be found on the OpenBMC jenkins site and on the OpenBMC GitHub release page. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210303072743.1551329-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | docs/system/arm/mps2.rst: Document the new mps3-an547 boardPeter Maydell2021-03-081-2/+4
|/ | | | | | | | | Add brief documentation of the new mps3-an547 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210219144617.4782-44-peter.maydell@linaro.org
* docs/system/arm/mps2.rst: Document the new mps3-an524 boardPeter Maydell2021-03-081-6/+18
| | | | | | | | | Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-24-peter.maydell@linaro.org
* hw/arm: Add npcm7xx emc modelDoug Evans2021-03-051-1/+2
| | | | | | | | | | | | | This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-3-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/i2c: Implement NPCM7XX SMBus Module Single ModeHao Wu2021-02-161-1/+1
| | | | | | | | | | | | | | | | | | | | This commit implements the single-byte mode of the SMBus. Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus and I2C protocol. This patch implements the single-byte mode of the SMBus. In this mode, the user sends or receives a byte each time. The SMBus device transmits it to the underlying i2c device and sends an interrupt back to the QEMU guest. Reviewed-by: Doug Evans<dje@google.com> Reviewed-by: Tyrong Ting<kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Corey Minyard <cminyard@mvista.com> Message-id: 20210210220426.3577804-2-wuhaotsh@google.com Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system: document an example booting the versatilepb machineAlex Bennée2021-02-081-0/+34
| | | | | | | | | | | | | | | | There is a bit more out there including Aurelien's excellent write up and older Debian images here: https://www.aurel32.net/info/debian_arm_qemu.php https://people.debian.org/~aurel32/qemu/armel/ However the web is transitory and git is forever so lets add something to the fine manual. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Anders Roxell <anders.roxell@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20210202134001.25738-16-alex.bennee@linaro.org>
* docs/system: document an example vexpress-a15 invocationAlex Bennée2021-02-081-0/+28
| | | | | | | | | | | The wiki and the web are curiously absent of the right runes to boot a vexpress model so I had to work from first principles to work it out. Use the more modern -drive notation so alternative backends can be used (unlike the hardwired -sd mode). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Anders Roxell <anders.roxell@linaro.org> Message-Id: <20210202134001.25738-15-alex.bennee@linaro.org>
* arm-virt: add secure pl061 for reset/power downMaxim Uvarov2021-01-291-0/+2
| | | | | | | | | | | Add secure pl061 for reset/power down machine from the secure world (Arm Trusted Firmware). Connect it with gpio-pwr driver. Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> [PMM: Added mention of the new device to the documentation] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Add cpu properties to control pauthRichard Henderson2021-01-191-0/+21
| | | | | | | | | | | | | | | | | | | The crypto overhead of emulating pauth can be significant for some workloads. Add two boolean properties that allows the feature to be turned off, on with the architected algorithm, or on with an implementation defined algorithm. We need two intermediate booleans to control the state while parsing properties lest we clobber ID_AA64ISAR1 into an invalid intermediate state. Tested-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210111235740.462469-3-richard.henderson@linaro.org [PMM: fixed docs typo, tweaked text to clarify that the impdef algorithm is specific to QEMU] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc: Add a PWM module for NPCM7XXHao Wu2021-01-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | The PWM module is part of NPCM7XX module. Each NPCM7XX module has two identical PWM modules. Each module contains 4 PWM entries. Each PWM has two outputs: frequency and duty_cycle. Both are computed using inputs from software side. This module does not model detail pulse signals since it is expensive. It also does not model interrupts and watchdogs that are dependant on the detail models. The interfaces for these are left in the module so that anyone in need for these functionalities can implement on their own. The user can read the duty cycle and frequency using qom-get command. Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-5-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/adc: Add an ADC module for NPCM7XXHao Wu2021-01-121-1/+1
| | | | | | | | | | | | | | | | The ADC is part of NPCM7XX Module. Its behavior is controled by the ADC_CON register. It converts one of the eight analog inputs into a digital input and stores it in the ADC_DATA register when enabled. Users can alter input value by using qom-set QMP command. Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-4-wuhaotsh@google.com [PMM: Added missing hw/adc/trace.h file] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system: arm: Add sabrelite board descriptionBin Meng2021-01-081-0/+119
| | | | | | | | | | This adds the target guide for SABRE Lite board, and documents how to boot a Linux kernel and U-Boot bootloader. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210106063504.10841-5-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/arm: Document the Sharp Zaurus SL-6000Philippe Mathieu-Daudé2020-11-231-7/+13
| | | | | | | | | List the 'tosa' machine with the XScale-based PDAs models. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120173953.2539469-5-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/arm: Document OpenPOWER Witherspoon BMC model Front LEDsPhilippe Mathieu-Daudé2020-11-231-0/+1
| | | | | | | | | | | Document the 3 front LEDs modeled on the OpenPOWER Witherspoon BMC (see commit 7cfbde5ea1c "hw/arm/aspeed: Add the 3 front LEDs drived by the PCA9552 #1"). Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120173953.2539469-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/arm: Document the various raspi boardsPhilippe Mathieu-Daudé2020-11-231-0/+43
| | | | | | | | | | | | | | | Document the following Raspberry Pi models: - raspi0 Raspberry Pi Zero (revision 1.2) - raspi1ap Raspberry Pi A+ (revision 1.1) - raspi2b Raspberry Pi 2B (revision 1.1) - raspi3ap Raspberry Pi 3A+ (revision 1.0) - raspi3b Raspberry Pi 3B (revision 1.2) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201120173953.2539469-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs: add some notes on the sbsa-ref machineAlex Bennée2020-11-101-0/+32
| | | | | | | | | | | | | We should at least document what this machine is about. Reviewed-by: Graeme Gregory <graeme@nuviainc.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20201104165254.24822-1-alex.bennee@linaro.org Cc: Leif Lindholm <leif@nuviainc.com> Cc: Shashi Mallela <shashi.mallela@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [PMM: fixed filename mismatch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/gpio: Add GPIO model for Nuvoton NPCM7xxHavard Skinnemoen2020-10-271-1/+1
| | | | | | | | | | | | | | | | The NPCM7xx chips have multiple GPIO controllers that are mostly identical except for some minor differences like the reset values of some registers. Each controller controls up to 32 pins. Each individual pin is modeled as a pair of unnamed GPIOs -- one for emitting the actual pin state, and one for driving the pin externally. Like the nRF51 GPIO controller, a gpio level may be negative, which means the pin is not driven, or floating. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/npcm7xx: Add EHCI and OHCI controllersHavard Skinnemoen2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The NPCM730 and NPCM750 chips have a single USB host port shared between a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This adds support for both of them. Testing notes: * With -device usb-kbd, qemu will automatically insert a full-speed hub, and the keyboard becomes controlled by the OHCI controller. * With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly attached to the port without any hubs, and the device becomes controlled by the EHCI controller since it's high speed capable. * With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the keyboard is directly attached to the port, but it only advertises itself as full-speed capable, so it becomes controlled by the OHCI controller. In all cases, the keyboard device enumerates correctly. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc: Add npcm7xx random number generatorHavard Skinnemoen2020-10-271-1/+1
| | | | | | | | | | | | | | | | The RNG module returns a byte of randomness when the Data Valid bit is set. This implementation ignores the prescaler setting, and loads a new value into RNGD every time RNGCS is read while the RNG is enabled and random data is available. A qtest featuring some simple randomness tests is included. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Implement kvm-steal-timeAndrew Jones2020-10-081-0/+11
| | | | | | | | | | | We add the kvm-steal-time CPU property and implement it for machvirt. A tiny bit of refactoring was also done to allow pmu and pvtime to use the same vcpu device helper functions. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-7-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch ↵Peter Maydell2020-09-221-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-5.2-pull-request' into staging Pull request trivial patches 20200919 # gpg: Signature made Sat 19 Sep 2020 19:43:35 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-5.2-pull-request: contrib/: fix some comment spelling errors qapi/: fix some comment spelling errors disas/: fix some comment spelling errors linux-user/: fix some comment spelling errors util/: fix some comment spelling errors scripts/: fix some comment spelling errors docs/: fix some comment spelling errors migration/: fix some comment spelling errors qemu/: fix some comment spelling errors scripts/git.orderfile: Display meson files along with buildsys ones hw/timer/hpet: Fix debug format strings hw/timer/hpet: Remove unused functions hpet_ram_readb, hpet_ram_readw meson: remove empty else and duplicated gio deps manual: escape backslashes in "parsed-literal" blocks ui/spice-input: Remove superfluous forward declaration hw/ppc/ppc4xx_pci: Replace magic value by the PCI_NUM_PINS definition hw/gpio/max7310: Remove impossible check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * docs/: fix some comment spelling errorszhaolichang2020-09-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | I found that there are many spelling errors in the comments of qemu, so I used the spellcheck tool to check the spelling errors and finally found some spelling errors in the docs folder. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200917075029.313-4-zhaolichang@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | hw/arm/aspeed: Add machine properties to define the flash modelsCédric Le Goater2020-09-181-0/+18
|/ | | | | | | | | | | | | | | | | Some machines don't have much differences a part from the flash model being used. Introduce new machine properties to change them from the command line. For instance, to start the ast2500-evb machine with a different FMC chip and a 64M SPI chip, use : -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f Cc: 郁雷 <yulei.sh@bytedance.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Lei YU <yulei.sh@bytedance.com> Message-Id: <20200915054859.2338477-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* docs/system: Add Nuvoton machine documentationHavard Skinnemoen2020-09-141-0/+92
| | | | | | | | Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-14-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/arm/mps2.rst: Make board list consistentPeter Maydell2020-09-141-7/+7
| | | | | | | | | | Make the list of MPS2 boards consistent in the phrasing of each entry, use the correct casing of "Arm", and move the mps2-an511 entry so the list is in numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-4-peter.maydell@linaro.org
* hw/arm/mps2: New board model mps2-an500Peter Maydell2020-09-141-2/+4
| | | | | | | | | | | | | | | Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
* hw/arm/mps2: New board model mps2-an386Peter Maydell2020-09-141-3/+5
| | | | | | | | | | | Implement a model of the MPS2 with the AN386 firmware. This is essentially identical to the AN385 firmware, but it has a Cortex-M4 rather than a Cortex-M3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-2-peter.maydell@linaro.org
* docs/system/arm: Document the Xilinx Versal Virt boardEdgar E. Iglesias2020-08-241-0/+176
| | | | | | | | | Document the Xilinx Versal Virt board. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20200803164749.301971-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/arm/virt: Document 'mte' machine optionPeter Maydell2020-07-271-0/+4
| | | | | | | | | | Commit 6a0b7505f1fd6769c which added documentation of the virt board crossed in the post with commit 6f4e1405b91da0d0 which added a new 'mte' machine option. Update the docs to include the new option. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* docs/system: Document the arm virt boardPeter Maydell2020-07-201-0/+161
| | | | | | | | | | Document the arm 'virt' board, which has been undocumented for far too long given that it is the main recommended board type for arm guests. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200713175746.5936-5-peter.maydell@linaro.org
* docs/system: Briefly document gumstix boardsPeter Maydell2020-07-201-0/+21
| | | | | | | | | | Add skeletal documentation of the gumstix boards ('connex' and 'verdex'). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200713175746.5936-4-peter.maydell@linaro.org
* docs/system: Briefly document collie boardPeter Maydell2020-07-201-0/+16
| | | | | | | | | Add skeletal documentation of the collie board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200713175746.5936-3-peter.maydell@linaro.org
* docs/system: Briefly document canon-a1100 boardPeter Maydell2020-07-201-0/+11
| | | | | | | | | Add skeletal documentation of the canon-a1100 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200713175746.5936-2-peter.maydell@linaro.org
* docs/orangepi: Add instructions for resizing SD image to power of twoNiek Linnenbank2020-07-141-3/+13
| | | | | | | | | | | | | SD cards need to have a size of a power of two. Update the Orange Pi machine documentation to include instructions for resizing downloaded images using the qemu-img command. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200712183708.15450-1-nieklinnenbank@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* docs/system: Document Aspeed boardsCédric Le Goater2020-06-051-0/+85
| | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200602135050.593692-1-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system: Document Musca boardsPeter Maydell2020-05-211-0/+31
| | | | | | | | | | Provide a minimal documentation of the Musca boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200507151819.28444-6-peter.maydell@linaro.org
* docs/system: Document the various MPS2 modelsPeter Maydell2020-05-211-0/+29
| | | | | | | | | | Add basic documentation of the MPS2 board models. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200507151819.28444-5-peter.maydell@linaro.org
* docs/system: Document Arm Versatile Express boardsPeter Maydell2020-05-211-0/+60
| | | | | | | | | | | Provide a minimal documentation of the Versatile Express boards (vexpress-a9, vexpress-a15). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200507151819.28444-4-peter.maydell@linaro.org
* docs/system: Add 'Arm' to the Integrator/CP document titlePeter Maydell2020-05-211-2/+2
| | | | | | | | | | | | Add 'Arm' to the Integrator/CP document title, for consistency with the titling of the other documentation of Arm devboard models (versatile, realview). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200507151819.28444-2-peter.maydell@linaro.org
* docs: add Orange Pi PC documentNiek Linnenbank2020-03-121-0/+253
| | | | | | | | | | | | | | | | | The Xunlong Orange Pi PC machine is a functional ARM machine based on the Allwinner H3 System-on-Chip. It supports mainline Linux, U-Boot, NetBSD and is covered by acceptance tests. This commit adds a documentation text file with a description of the machine and instructions for the user. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com [PMM: moved file into docs/system/arm to match the reorg of the arm target part of the docs; tweaked heading to match other boards] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs: Be consistent about capitalization of 'Arm'Peter Maydell2020-03-129-11/+11
| | | | | | | | | | | | | | | | The company 'Arm' went through a rebranding some years back involving a recapitalization from 'ARM' to 'Arm'. As a result our documentation is a bit inconsistent between the two forms. It's not worth trying to update everywhere in QEMU, but it's easy enough to make docs/ consistent. Note that "ARMv8" and similar architecture names, and older CPU names like "ARM926" still retain all-caps. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200309215818.2021-6-peter.maydell@linaro.org
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