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* target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'Peter Maydell2022-09-141-0/+1
| | | | | | | | | | Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 compliant PMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822132358.3524971-11-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Advertise FEAT_ETS for '-cpu max'Peter Maydell2022-09-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architectural feature FEAT_ETS (Enhanced Translation Synchronization) is a set of tightened guarantees about memory ordering involving translation table walks: * if memory access RW1 is ordered-before memory access RW2 then it is also ordered-before any translation table walk generated by RW2 that generates a translation fault, address size fault or access fault * TLB maintenance on non-exec-permission translations is guaranteed complete after a DSB (ie it does not need the context synchronization event that you have to have if you don’t have FEAT_ETS) For QEMU’s implementation we don’t reorder translation table walk accesses, and we guarantee to finish the TLB maintenance as soon as the TLB op is done (the tlb_flush functions will complete at the end of the TLB, and TLB ops always end the TB because they’re sysreg writes). So we’re already compliant and all we need to do is say so in the ID registers for the 'max' CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220819110052.2942289-6-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Add cortex-a35Hao Wu2022-09-141-0/+1
| | | | | | | | | | Add cortex A35 core and enable it for virt board. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220819002015.1663247-1-wuhaotsh@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu ↵Stefan Hajnoczi2022-09-061-2/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging baum: better document usb-braille configuration Samuel Thibault (1): usb-braille: Better explain that one also has to create a chardev backend # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZTSF1IMOAGwT71n/aHTOWK4tfj8FAmMWdVUACgkQaHTOWK4t # fj9dyQ/+PqiwRQktcbZ3/o4rvd0jCGRXduaJe/UD/AkVg1P2d6o6baViSMaiBry2 # 3t0Hmz+5CnSVQpYJqv0r+QARJUmYZSssrliekaPJ2Vi3KwaWgShw3t9vNO/xnTA4 # aesTtlnw2PvbNeqGZZyuNSqFkvMVKxItl01H7O8LfvqMsY7NBxOUqpLoOfBhr4EC # ncJ8tTyhTJLxly/RrS0S4LGasazmm3rlhkV/yhwX0/1rGfdZKoQDLPkOSjs+isrs # C6HmAyixarCKAgse3vJG322H459jFj/fkrmS+298HpFFQDIH0EH1VZbqYtkH7HBA # 0fGCaOHwVNBOzrx3KYCN7Aq0TwnzqfGhFuRwMj7lWVC3zppC52bxw8miVuZkhFfT # YyPxxZTlNfVYOJmpSQOtRpOFSJlBmVYux4Wdk5jmpEgGtX7q0ce6ysk/fyvVCItu # cGuKh//or3zrLJxy2BIfn9sl0/1Z1/gsD1sitsdrKJGTL2CDxq/vBvS9JH6FbwtN # JySiO90lj12WlhqtQWO6dtfHqdLwM1Rnl3YG//Trc82yssqdp6N2O5PJjEV1HATd # 6G6BONDSJgixqrKDCo4+FY4OCFhHvqw+VxeKYFlbD0Cc9aOOHx6IrOmRYDFR/svo # N/942smJJ+a9DW1IJoHmIa3LAtBO8Vd1LJysGcfz94Zj1i7RuqY= # =7mD0 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 05 Sep 2022 18:16:53 EDT # gpg: using RSA key 653485D4830E006C13EF59FF6874CE58AE2D7E3F # gpg: Good signature from "Samuel Thibault <samuel.thibault@ens-lyon.org>" [full] # gpg: aka "Samuel Thibault <sthibault@debian.org>" [full] # gpg: aka "Samuel Thibault <samuel.thibault@gnu.org>" [unknown] # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" [full] # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" [full] # gpg: aka "Samuel Thibault <samuel.thibault@u-bordeaux.fr>" [unknown] # gpg: aka "Samuel Thibault <samuel.thibault@aquilenet.fr>" [unknown] # gpg: aka "Samuel Thibault <sthibault@hypra.fr>" [unknown] # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: 6534 85D4 830E 006C 13EF 59FF 6874 CE58 AE2D 7E3F * tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu: usb-braille: Better explain that one also has to create a chardev backend Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * usb-braille: Better explain that one also has to create a chardev backendSamuel Thibault2022-09-061-2/+14
| | | | | | | | | | | | | | | | Users have reported not to understand the documentation. This completes it to give an explicit example how one is supposed to set up a virtual braille USB device. Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
* | docs/system: openrisc: Add OpenRISC documentationStafford Horne2022-09-046-0/+197
|/ | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
* ppc/ppc405: Remove taihu machineCédric Le Goater2022-08-311-1/+0Star
| | | | | | | | | It has been deprecated since 7.0. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220809153904.485018-2-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* pseries: Update SLOF firmware imageAlexey Kardashevskiy2022-08-301-1/+1
| | | | | | | | The only change is that now SLOF can also boot big endian zImage but kernel-addr=0 is still required. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* docs/system/loongarch: Update the LoongArch documentXiaojuan Yang2022-08-131-8/+96
| | | | | | | | | | | | | 1. Add some information about how to boot the LoongArch virt machine by uefi bios and linux kernel and how to access the source code or binary file. 2. Move the explanation of LoongArch system emulation in the target/loongarch/README to docs/system/loongarch/loongson3.rst Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220812091957.3338126-1-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Fix some typos in documentation (most of them found by codespell)Stefan Weil2022-08-122-10/+10
| | | | | | | | Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Hongren (Zenithal) Zheng <i@zenithal.me> Message-id: 20220812075642.1200578-1-sw@weilnetz.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* misc: fix commonly doubled up wordsDaniel P. Berrangé2022-08-014-4/+4
| | | | | | | Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20220707163720.1421716-5-berrange@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* usb: document pcap (aka usb traffic capture)Gerd Hoffmann2022-07-191-0/+12
| | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220711094437.3995927-3-kraxel@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* usb: document guest-reset and guest-reset-allGerd Hoffmann2022-07-191-0/+29
| | | | | | | | Suggested-by: Michal Prívozník <mprivozn@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michal Privoznik <mprivozn@redhat.com> Message-Id: <20220711094437.3995927-2-kraxel@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into ↵Peter Maydell2022-07-151-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging hw/nvme updates performance improvements by Jinhao ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * shadow doorbells * ioeventfd plus some misc fixes (Darren, Niklas). # gpg: Signature made Fri 15 Jul 2022 09:42:20 BST # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme: hw/nvme: Use ioeventfd to handle doorbell updates nvme: Fix misleading macro when mixed with ternary operator hw/nvme: force nvme-ns param 'shared' to false if no nvme-subsys node hw/nvme: fix example serial in documentation hw/nvme: Add trace events for shadow doorbell buffer hw/nvme: Implement shadow doorbell buffer support Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/nvme: fix example serial in documentationNiklas Cassel2022-07-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The serial prop on the controller is actually describing the nvme subsystem serial, which has to be identical for all controllers within the same nvme subsystem. This is enforced since commit a859eb9f8f64 ("hw/nvme: enforce common serial per subsystem"). Fix the documentation, so that people copying the qemu command line example won't get an error on qemu start. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* | docs: aspeed: Minor updatesCédric Le Goater2022-07-141-4/+10
| | | | | | | | | | | | | | | | | | | | | | Some more controllers have been modeled recently. Reflect that in the list of supported devices. New machines were also added. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20220706172131.809255-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | docs: aspeed: Add fby35 multi-SoC machine sectionPeter Delevoryas2022-07-141-0/+48
|/ | | | | | | | | | Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - fixed URL links - Moved Facebook Yosemite section at the end of the file ] Message-Id: <20220705191400.41632-10-peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* target/arm: Enable SME for -cpu maxRichard Henderson2022-07-111-0/+4
| | | | | | | | | | | Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: dt: add rng-seed propertyJason A. Donenfeld2022-07-071-6/+11
| | | | | | | | | | | | | | | | In 60592cfed2 ("hw/arm/virt: dt: add kaslr-seed property"), the kaslr-seed property was added, but the equally as important rng-seed property was forgotten about, which has identical semantics for a similar purpose. This commit implements it in exactly the same way as kaslr-seed. It then changes the name of the disabling option to reflect that this has more to do with randomness vs determinism, rather than something particular about kaslr. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [PMM: added deprecated.rst section for the deprecation] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/devices/usb/canokey: remove limitations on qemu-xhciHongren (Zenithal) Zheng2022-07-011-10/+0Star
| | | | | | Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> Message-Id: <YqcqeIpY4h7ZQPWH@Sun> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* target/arm: Add cpu properties for SMERichard Henderson2022-06-271-0/+56
| | | | | | | | | | | | | | | Mirror the properties for SVE. The main difference is that any arbitrary set of powers of 2 may be supported, and not the stricter constraints that apply to SVE. Include a property to control FEAT_SME_FA64, as failing to restrict the runtime to the proper subset of insns could be a major point for bugs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220620175235.60881-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs: Add documentation for SR-IOV and Virtualization EnhancementsLukasz Maniak2022-06-231-0/+82
| | | | | | | | | | | | | | | | | Documentation describes 5 new parameters being added regarding SR-IOV: sriov_max_vfs sriov_vq_flexible sriov_vi_flexible sriov_max_vi_per_vf sriov_max_vq_per_vf The description also includes the simplest possible QEMU invocation and the series of NVMe commands required to enable SR-IOV support. Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
* docs/cxl: Add switch documentationJonathan Cameron2022-06-161-2/+86
| | | | | | | | | | | | Switches were already introduced, but now we support them update the documentation to provide an example in diagram and qemu command line parameter forms. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220616145126.8002-4-Jonathan.Cameron@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* docs/system/devices/usb: Add CanoKey to USB devices examplesHongren (Zenithal) Zheng2022-06-141-0/+4
| | | | | | Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> Message-Id: <YoY6o+QFhzA7VHcZ@Sun> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* docs: Add CanoKey documentationHongren (Zenithal) Zheng2022-06-142-0/+169
| | | | | | Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> Message-Id: <YoY6ilQimrK+l5NN@Sun> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Richard Henderson2022-06-111-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging virtio,pc,pci: fixes,cleanups,features more CXL patches VIOT Igor's huge AML rework fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmKj4YcPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpkNcIAKTsMfUVueTjelC2RwIdegQkypycKhCweKzc # QxddaEr0w+N2164byT3IUy9h53hV3qAAmMuGE4d8B2r5rykf+SwDfIeNmHNqntnA # oLraXIxSSAf4/1cTsRCVL/BXo2E9P+WHI3huw37HClmPLdyMjQa1AtpTpKnIsbmO # sBZf7t5yHDJ2WGZwBQ1IbAxvsdGo1fa1TCt1jZ9g1dmnQSTteQG8DHkGoRnkwTi7 # 510jb0e8uQEgKytCdLTHqESHlfgjvoI73OFOAR2dzTKy6KelFmdLYSo2FtsIdtT5 # 1fZNaDjtl6zQ4b2iLBgPpHtikKch9BzzhDMbCsq7FpvasZ8u2FE= # =LXG0 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 10 Jun 2022 05:27:51 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) hw/vhost-user-scsi|blk: set `supports_config` flag correctly hw/virtio/vhost-user: don't use uninitialized variable tests/acpi: virt: update golden masters for VIOT hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_bus tests/acpi: virt: allow VIOT acpi table changes hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI table hw/acpi/viot: move the individual PCI host bridge entry generation to a new function hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges() hw/cxl: Fix missing write mask for HDM decoder target list registers pci: fix overflow in snprintf string formatting hw/machine: Drop cxl_supported flag as no longer useful hw/cxl: Move the CXLState from MachineState to machine type specific state. tests/acpi: Update q35/CEDT.cxl for new memory addresses. pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. tests/acpi: Allow modification of q35 CXL CEDT table. hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c hw/acpi/cxl: Pass in the CXLState directly rather than MachineState hw/cxl: Make the CXL fixed memory window setup a machine parameter. x86: acpi-build: do not include hw/isa/isa.h directly tests: acpi: update expected DSDT.tis.tpm2/DSDT.tis.tpm12 blobs ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/cxl: Make the CXL fixed memory window setup a machine parameter.Jonathan Cameron2022-06-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Paolo Bonzini requested this change to simplify the ongoing effort to allow machine setup entirely via RPC. Includes shortening the command line form cxl-fixed-memory-window to cxl-fmw as the command lines are extremely long even with this change. The json change is needed to ensure that there is a CXLFixedMemoryWindowOptionsList even though the actual element in the json is never used. Similar to existing SgxEpcProperties. Update qemu-options.hx to reflect that this is now a -machine parameter. The bulk of -M / -machine parameters are documented under machine, so use that in preference to M. Update cxl-test and bios-tables-test to reflect new parameters. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Message-Id: <20220608145440.26106-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | target/arm: Implement FEAT_DoubleFaultPeter Maydell2022-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FEAT_DoubleFault extension adds the following: * All external aborts on instruction fetches and translation table walks for instruction fetches must be synchronous. For QEMU this is already true. * SCR_EL3 has a new bit NMEA which disables the masking of SError interrupts by PSTATE.A when the SError interrupt is taken to EL3. For QEMU we only need to make the bit writable, because we have no sources of SError interrupts. * SCR_EL3 has a new bit EASE which causes synchronous external aborts taken to EL3 to be taken at the same entry point as SError. (Note that this does not mean that they are SErrors for purposes of PSTATE.A masking or that the syndrome register reports them as SErrors: it just means that the vector offset is different.) * The existing SCTLR_EL3.IESB has an effective value of 1 when SCR_EL3.NMEA is 1. For QEMU this is a no-op because we don't need different behaviour based on IESB (we don't need to do anything to ensure that error exceptions are synchronized). So for QEMU the things we need to change are: * Make SCR_EL3.{NMEA,EASE} writable * When taking a synchronous external abort at EL3, adjust the vector entry point if SCR_EL3.EASE is set * Advertise the feature in the ID registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220531151431.949322-1-peter.maydell@linaro.org
* | target/arm: Declare support for FEAT_RASv1p1Peter Maydell2022-06-081-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | The architectural feature RASv1p1 introduces the following new features: * new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1 * new bits in the fine-grained trap registers that control traps for these new registers * new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps for ERXPFGCDN_EL1, ERXPFGCTL_EL1, ERXPFGP_EL1 * a larger number of the ERXMISC<n>_EL1 registers * the format of ERR<n>STATUS registers changes The architecture permits that if ERRIDR_EL1.NUM is 0 (as it is for QEMU) then all these new registers may UNDEF, and the HCR_EL2.FIEN and SCR_EL3.FIEN bits may be RES0. We don't have any ERR<n>STATUS registers (again, because ERRIDR_EL1.NUM is 0). QEMU does not yet implement the fine-grained-trap extension. So there is nothing we need to implement to be compliant with the feature spec. Make the 'max' CPU report the feature in its ID registers, and document it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220531114258.855804-1-peter.maydell@linaro.org
* target/loongarch: Add system emulation introductionXiaojuan Yang2022-06-061-0/+41
| | | | | | | | Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-19-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* docs: move replay docs to docs/system/replay.rstPavel Dovgalyuk2022-06-062-0/+238
| | | | | | | | | | | | This patch adds replay description page, converting prior text from docs/replay.txt. The text was also updated and some sections were moved to devel part of the docs. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165364839601.688121.5131456980322853233.stgit@pasha-ThinkPad-X280> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* docs/system/arm: Add FEAT_HCX to list of emulated featuresPeter Maydell2022-05-301-0/+1
| | | | | | | | | | | | In commit 5814d587fe861fe9 we added support for emulating FEAT_HCX (Support for the HCRX_EL2 register). However we forgot to add it to the list in emulated.rst. Correct the omission. Fixes: 5814d587fe861fe9 ("target/arm: Enable FEAT_HCX for -cpu max") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220520084320.424166-1-peter.maydell@linaro.org
* spapr/docs: Add a few words about x-vofAlexey Kardashevskiy2022-05-261-0/+29
| | | | | | | | | | | The alternative small firmware needs a few words of what it can and absolutely cannot do; this adds those words. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20220506055124.3822112-1-aik@ozlabs.ru> [danielhb: added linebreaks before and after table] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson2022-05-252-0/+289
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ac97 cleanups (Zoltan) * default the amount of prealloc-threads to smp-cpus (Jaroslav) * fix disabling MPX on "-cpu host" with MPX-capable host (Maciej) * thread-pool performance optimizations (myself) * Hyper-V enlightenment enabling and docs (Vitaly) * check ELF header in elf2dmp (Viktor) * tweak LBREn migration (Weijiang) # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmKOgwgUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOO3Qf7Btcvr2ex9qZ1yThlmZ6hl20WvQZe # GlKBq5xJnx2FUpvrH/AiNl2qfiBN5emhzJp1oBieQusDDsWVblmRpWgzUkUZvh0H # s5rKsNuOPdhqaxLH4sRCXS2FCVOy81d+lc9yYe5bzy3EHDO/qzMjye+JoBhXtQve # 3gOcOb1srIB/xSGNur2iCJkcauhBOipOo77kryfWekfReA3glHGnwhuEO+F+gXT3 # hiEO6TuRHjVrVCExbsDJb2pV2sSH6FxOP09BZ84IT0puv/FfgnUGCiNVfVNmMgNq # KYysG7vPlRSaDX17bt3UlS4Y6yKb1vZpnvymRRkWxWLIfuAVVNm0vgHBpg== # =gX2j # -----END PGP SIGNATURE----- # gpg: Signature made Wed 25 May 2022 12:27:04 PM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: i386: docs: Convert hyperv.txt to rST i386: Hyper-V Direct TLB flush hypercall i386: Hyper-V Support extended GVA ranges for TLB flush hypercalls i386: Hyper-V XMM fast hypercall input feature i386: Hyper-V Enlightened MSR bitmap feature i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURES ide_ioport_read: Return lower octet of data register instead of 0xFF target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable host hw/audio/ac97: Remove unneeded local variables hw/audio/ac97: Remove unimplemented reset functions hw/audio/ac97: Coding style fixes to avoid checkpatch errors contrib/elf2dmp: add ELF dump header checking thread-pool: remove stopping variable thread-pool: replace semaphore with condition variable thread-pool: optimize scheduling of completion bottom half hostmem: default the amount of prealloc-threads to smp-cpus target/i386: Remove LBREn bit check when access Arch LBR MSRs Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * i386: docs: Convert hyperv.txt to rSTVitaly Kuznetsov2022-05-252-0/+289
| | | | | | | | | | | | | | | | rSTify docs/hyperv.txt and link it from docs/system/target-i386.rst. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20220525115949.1294004-7-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | docs: aspeed: Add fby35 boardPeter Delevoryas2022-05-251-0/+1
| | | | | | | | | | | | | | | | Add fby35 to the list of Aspeed boards. Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220506193354.990532-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | docs: add minibmc section in aspeed documentJamin Lin2022-05-251-0/+61
|/ | | | | | | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220506031521.13254-2-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* target/arm: Implement FEAT_IDSTPeter Maydell2022-05-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The Armv8.4 feature FEAT_IDST specifies that exceptions generated by read accesses to the feature ID space should report a syndrome code of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED). The feature ID space is defined to be: op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7} In our implementation we might return the EC_UNCATEGORIZED syndrome value for a system register access in four cases: * no reginfo struct in the hashtable * cp_access_ok() fails (ie ri->access doesn't permit the access) * ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime * ri->type includes ARM_CP_RAISES_EXC, and the readfn raises an UNDEF exception at runtime We have very few regdefs that set ARM_CP_RAISES_EXC, and none of them are in the feature ID space. (In the unlikely event that any are added in future they would need to take care of setting the correct syndrome themselves.) This patch deals with the other three cases, and enables FEAT_IDST for AArch64 -cpu max. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
* target/arm: Enable FEAT_S2FWB for -cpu maxPeter Maydell2022-05-191-0/+1
| | | | | | | | | | Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the inherited CLIDR_EL1 value from the Cortex-A57 has them as 1). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
* docs/cxl: Add initial Compute eXpress Link (CXL) documentation.Jonathan Cameron2022-05-132-0/+303
| | | | | | | | | | | | | | | | | | | Provide an introduction to the main components of a CXL system, with detailed explanation of memory interleaving, example command lines and kernel configuration. This was a challenging document to write due to the need to extract only that subset of CXL information which is relevant to either users of QEMU emulation of CXL or to those interested in the implementation. Much of CXL is concerned with specific elements of the protocol, management of memory pooling etc which is simply not relevant to what is currently planned for CXL emulation in QEMU. All comments welcome Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220429144110.25167-43-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* target/arm: Define neoverse-n1Richard Henderson2022-05-091-0/+1
| | | | | | | | | Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Define cortex-a76Richard Henderson2022-05-091-0/+1
| | | | | | | | | Enable the a76 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_DGH for -cpu maxRichard Henderson2022-05-091-0/+1
| | | | | | | | | | | This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_CSV3 for -cpu maxRichard Henderson2022-05-091-0/+1
| | | | | | | | | | This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_CSV2_2 for -cpu maxRichard Henderson2022-05-091-0/+3
| | | | | | | | | | | There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_CSV2 for -cpu maxRichard Henderson2022-05-091-0/+1
| | | | | | | | | | This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_IESB for -cpu maxRichard Henderson2022-05-091-0/+1
| | | | | | | | | | This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_RAS for -cpu maxRichard Henderson2022-05-091-0/+1
| | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_Debugv8p4 for -cpu maxRichard Henderson2022-05-091-0/+1
| | | | | | | | | | | | This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_Debugv8p2 for -cpu maxRichard Henderson2022-05-091-0/+1
| | | | | | | | | | | | The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-03 19:20:22 +0200